1[root]
2type=Root
3children=system
4full_system=true
5time_sync_enable=false
6time_sync_period=100000000000
7time_sync_spin_threshold=100000000
8
9[system]
10type=LinuxArmSystem
| 1[root]
2type=Root
3children=system
4full_system=true
5time_sync_enable=false
6time_sync_period=100000000000
7time_sync_spin_threshold=100000000
8
9[system]
10type=LinuxArmSystem
|
11children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
| 11children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
|
12atags_addr=256
13boot_loader=/dist/m5/system/binaries/boot.arm
14boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
| 12atags_addr=256
13boot_loader=/dist/m5/system/binaries/boot.arm
14boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
15clock=1000
| 15cache_line_size=64
16clk_domain=system.clk_domain
|
16dtb_filename=False
17early_kernel_symbols=false
18enable_context_switch_stats_dump=false
19flags_addr=268435504
20gic_cpu_addr=520093952
21init_param=0
22kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
23load_addr_mask=268435455
24machine_type=RealView_PBX
25mem_mode=timing
26mem_ranges=0:134217727
| 17dtb_filename=False
18early_kernel_symbols=false
19enable_context_switch_stats_dump=false
20flags_addr=268435504
21gic_cpu_addr=520093952
22init_param=0
23kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
24load_addr_mask=268435455
25machine_type=RealView_PBX
26mem_mode=timing
27mem_ranges=0:134217727
|
27memories=system.physmem system.realview.nvmem
| 28memories=system.realview.nvmem system.physmem
|
28multi_proc=true
29num_work_ids=16
30panic_on_oops=true
31panic_on_panic=true
32readfile=tests/halt.sh
33symbolfile=
34work_begin_ckpt_count=0
35work_begin_cpu_id_exit=-1
36work_begin_exit_count=0
37work_cpus_ckpt_count=0
38work_end_ckpt_count=0
39work_end_exit_count=0
40work_item_id=-1
41system_port=system.membus.slave[0]
42
43[system.bridge]
44type=Bridge
| 29multi_proc=true
30num_work_ids=16
31panic_on_oops=true
32panic_on_panic=true
33readfile=tests/halt.sh
34symbolfile=
35work_begin_ckpt_count=0
36work_begin_cpu_id_exit=-1
37work_begin_exit_count=0
38work_cpus_ckpt_count=0
39work_end_ckpt_count=0
40work_end_exit_count=0
41work_item_id=-1
42system_port=system.membus.slave[0]
43
44[system.bridge]
45type=Bridge
|
45clock=1000
| 46clk_domain=system.clk_domain
|
46delay=50000
47ranges=268435456:520093695 1073741824:1610612735
48req_size=16
49resp_size=16
50master=system.iobus.slave[0]
51slave=system.membus.master[0]
52
53[system.cf0]
54type=IdeDisk
55children=image
56delay=1000000
57driveID=master
58image=system.cf0.image
59
60[system.cf0.image]
61type=CowDiskImage
62children=child
63child=system.cf0.image.child
64image_file=
65read_only=false
66table_size=65536
67
68[system.cf0.image.child]
69type=RawDiskImage
70image_file=/dist/m5/system/disks/linux-arm-ael.img
71read_only=true
72
| 47delay=50000
48ranges=268435456:520093695 1073741824:1610612735
49req_size=16
50resp_size=16
51master=system.iobus.slave[0]
52slave=system.membus.master[0]
53
54[system.cf0]
55type=IdeDisk
56children=image
57delay=1000000
58driveID=master
59image=system.cf0.image
60
61[system.cf0.image]
62type=CowDiskImage
63children=child
64child=system.cf0.image.child
65image_file=
66read_only=false
67table_size=65536
68
69[system.cf0.image.child]
70type=RawDiskImage
71image_file=/dist/m5/system/disks/linux-arm-ael.img
72read_only=true
73
|
| 74[system.clk_domain]
75type=SrcClockDomain
76clock=1000
77voltage_domain=system.voltage_domain
78
|
73[system.cpu0]
74type=DerivO3CPU
75children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
76LFSTSize=1024
77LQEntries=32
78LSQCheckLoads=true
79LSQDepCheckShift=4
80SQEntries=32
81SSITSize=1024
82activity=0
83backComSize=5
84branchPred=system.cpu0.branchPred
85cachePorts=200
86checker=Null
| 79[system.cpu0]
80type=DerivO3CPU
81children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
82LFSTSize=1024
83LQEntries=32
84LSQCheckLoads=true
85LSQDepCheckShift=4
86SQEntries=32
87SSITSize=1024
88activity=0
89backComSize=5
90branchPred=system.cpu0.branchPred
91cachePorts=200
92checker=Null
|
87clock=500
| 93clk_domain=system.cpu_clk_domain
|
88commitToDecodeDelay=1
89commitToFetchDelay=1
90commitToIEWDelay=1
91commitToRenameDelay=1
92commitWidth=8
93cpu_id=0
94decodeToFetchDelay=1
95decodeToRenameDelay=1
96decodeWidth=8
97dispatchWidth=8
98do_checkpoint_insts=true
99do_quiesce=true
100do_statistics_insts=true
101dtb=system.cpu0.dtb
102fetchToDecodeDelay=1
103fetchTrapLatency=1
104fetchWidth=8
105forwardComSize=5
106fuPool=system.cpu0.fuPool
107function_trace=false
108function_trace_start=0
109iewToCommitDelay=1
110iewToDecodeDelay=1
111iewToFetchDelay=1
112iewToRenameDelay=1
113interrupts=system.cpu0.interrupts
114isa=system.cpu0.isa
115issueToExecuteDelay=1
116issueWidth=8
117itb=system.cpu0.itb
118max_insts_all_threads=0
119max_insts_any_thread=0
120max_loads_all_threads=0
121max_loads_any_thread=0
122needsTSO=false
123numIQEntries=64
124numPhysFloatRegs=256
125numPhysIntRegs=256
126numROBEntries=192
127numRobs=1
128numThreads=1
129profile=0
130progress_interval=0
131renameToDecodeDelay=1
132renameToFetchDelay=1
133renameToIEWDelay=2
134renameToROBDelay=1
135renameWidth=8
136simpoint_start_insts=
137smtCommitPolicy=RoundRobin
138smtFetchPolicy=SingleThread
139smtIQPolicy=Partitioned
140smtIQThreshold=100
141smtLSQPolicy=Partitioned
142smtLSQThreshold=100
143smtNumFetchingThreads=1
144smtROBPolicy=Partitioned
145smtROBThreshold=100
146squashWidth=8
147store_set_clear_period=250000
148switched_out=false
149system=system
150tracer=system.cpu0.tracer
151trapLatency=13
152wbDepth=1
153wbWidth=8
154workload=
155dcache_port=system.cpu0.dcache.cpu_side
156icache_port=system.cpu0.icache.cpu_side
157
158[system.cpu0.branchPred]
159type=BranchPredictor
160BTBEntries=4096
161BTBTagSize=16
162RASSize=16
163choiceCtrBits=2
164choicePredictorSize=8192
165globalCtrBits=2
| 94commitToDecodeDelay=1
95commitToFetchDelay=1
96commitToIEWDelay=1
97commitToRenameDelay=1
98commitWidth=8
99cpu_id=0
100decodeToFetchDelay=1
101decodeToRenameDelay=1
102decodeWidth=8
103dispatchWidth=8
104do_checkpoint_insts=true
105do_quiesce=true
106do_statistics_insts=true
107dtb=system.cpu0.dtb
108fetchToDecodeDelay=1
109fetchTrapLatency=1
110fetchWidth=8
111forwardComSize=5
112fuPool=system.cpu0.fuPool
113function_trace=false
114function_trace_start=0
115iewToCommitDelay=1
116iewToDecodeDelay=1
117iewToFetchDelay=1
118iewToRenameDelay=1
119interrupts=system.cpu0.interrupts
120isa=system.cpu0.isa
121issueToExecuteDelay=1
122issueWidth=8
123itb=system.cpu0.itb
124max_insts_all_threads=0
125max_insts_any_thread=0
126max_loads_all_threads=0
127max_loads_any_thread=0
128needsTSO=false
129numIQEntries=64
130numPhysFloatRegs=256
131numPhysIntRegs=256
132numROBEntries=192
133numRobs=1
134numThreads=1
135profile=0
136progress_interval=0
137renameToDecodeDelay=1
138renameToFetchDelay=1
139renameToIEWDelay=2
140renameToROBDelay=1
141renameWidth=8
142simpoint_start_insts=
143smtCommitPolicy=RoundRobin
144smtFetchPolicy=SingleThread
145smtIQPolicy=Partitioned
146smtIQThreshold=100
147smtLSQPolicy=Partitioned
148smtLSQThreshold=100
149smtNumFetchingThreads=1
150smtROBPolicy=Partitioned
151smtROBThreshold=100
152squashWidth=8
153store_set_clear_period=250000
154switched_out=false
155system=system
156tracer=system.cpu0.tracer
157trapLatency=13
158wbDepth=1
159wbWidth=8
160workload=
161dcache_port=system.cpu0.dcache.cpu_side
162icache_port=system.cpu0.icache.cpu_side
163
164[system.cpu0.branchPred]
165type=BranchPredictor
166BTBEntries=4096
167BTBTagSize=16
168RASSize=16
169choiceCtrBits=2
170choicePredictorSize=8192
171globalCtrBits=2
|
166globalHistoryBits=13
| |
167globalPredictorSize=8192
168instShiftAmt=2
169localCtrBits=2
| 172globalPredictorSize=8192
173instShiftAmt=2
174localCtrBits=2
|
170localHistoryBits=11
| |
171localHistoryTableSize=2048
172localPredictorSize=2048
173numThreads=1
174predType=tournament
175
176[system.cpu0.dcache]
177type=BaseCache
| 175localHistoryTableSize=2048
176localPredictorSize=2048
177numThreads=1
178predType=tournament
179
180[system.cpu0.dcache]
181type=BaseCache
|
| 182children=tags
|
178addr_ranges=0:18446744073709551615
179assoc=4
| 183addr_ranges=0:18446744073709551615
184assoc=4
|
180block_size=64
181clock=500
| 185clk_domain=system.cpu_clk_domain
|
182forward_snoops=true
183hit_latency=2
184is_top_level=true
185max_miss_count=0
186mshrs=4
187prefetch_on_access=false
188prefetcher=Null
189response_latency=2
190size=32768
191system=system
| 186forward_snoops=true
187hit_latency=2
188is_top_level=true
189max_miss_count=0
190mshrs=4
191prefetch_on_access=false
192prefetcher=Null
193response_latency=2
194size=32768
195system=system
|
| 196tags=system.cpu0.dcache.tags
|
192tgts_per_mshr=20
193two_queue=false
194write_buffers=8
195cpu_side=system.cpu0.dcache_port
196mem_side=system.toL2Bus.slave[1]
197
| 197tgts_per_mshr=20
198two_queue=false
199write_buffers=8
200cpu_side=system.cpu0.dcache_port
201mem_side=system.toL2Bus.slave[1]
202
|
| 203[system.cpu0.dcache.tags]
204type=LRU
205assoc=4
206block_size=64
207clk_domain=system.cpu_clk_domain
208hit_latency=2
209size=32768
210
|
198[system.cpu0.dtb]
199type=ArmTLB
200children=walker
201size=64
202walker=system.cpu0.dtb.walker
203
204[system.cpu0.dtb.walker]
205type=ArmTableWalker
| 211[system.cpu0.dtb]
212type=ArmTLB
213children=walker
214size=64
215walker=system.cpu0.dtb.walker
216
217[system.cpu0.dtb.walker]
218type=ArmTableWalker
|
206clock=500
| 219clk_domain=system.cpu_clk_domain
|
207num_squash_per_cycle=2
208sys=system
209port=system.toL2Bus.slave[3]
210
211[system.cpu0.fuPool]
212type=FUPool
213children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
214FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
215
216[system.cpu0.fuPool.FUList0]
217type=FUDesc
218children=opList
219count=6
220opList=system.cpu0.fuPool.FUList0.opList
221
222[system.cpu0.fuPool.FUList0.opList]
223type=OpDesc
224issueLat=1
225opClass=IntAlu
226opLat=1
227
228[system.cpu0.fuPool.FUList1]
229type=FUDesc
230children=opList0 opList1
231count=2
232opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
233
234[system.cpu0.fuPool.FUList1.opList0]
235type=OpDesc
236issueLat=1
237opClass=IntMult
238opLat=3
239
240[system.cpu0.fuPool.FUList1.opList1]
241type=OpDesc
242issueLat=19
243opClass=IntDiv
244opLat=20
245
246[system.cpu0.fuPool.FUList2]
247type=FUDesc
248children=opList0 opList1 opList2
249count=4
250opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
251
252[system.cpu0.fuPool.FUList2.opList0]
253type=OpDesc
254issueLat=1
255opClass=FloatAdd
256opLat=2
257
258[system.cpu0.fuPool.FUList2.opList1]
259type=OpDesc
260issueLat=1
261opClass=FloatCmp
262opLat=2
263
264[system.cpu0.fuPool.FUList2.opList2]
265type=OpDesc
266issueLat=1
267opClass=FloatCvt
268opLat=2
269
270[system.cpu0.fuPool.FUList3]
271type=FUDesc
272children=opList0 opList1 opList2
273count=2
274opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
275
276[system.cpu0.fuPool.FUList3.opList0]
277type=OpDesc
278issueLat=1
279opClass=FloatMult
280opLat=4
281
282[system.cpu0.fuPool.FUList3.opList1]
283type=OpDesc
284issueLat=12
285opClass=FloatDiv
286opLat=12
287
288[system.cpu0.fuPool.FUList3.opList2]
289type=OpDesc
290issueLat=24
291opClass=FloatSqrt
292opLat=24
293
294[system.cpu0.fuPool.FUList4]
295type=FUDesc
296children=opList
297count=0
298opList=system.cpu0.fuPool.FUList4.opList
299
300[system.cpu0.fuPool.FUList4.opList]
301type=OpDesc
302issueLat=1
303opClass=MemRead
304opLat=1
305
306[system.cpu0.fuPool.FUList5]
307type=FUDesc
308children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
309count=4
310opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
311
312[system.cpu0.fuPool.FUList5.opList00]
313type=OpDesc
314issueLat=1
315opClass=SimdAdd
316opLat=1
317
318[system.cpu0.fuPool.FUList5.opList01]
319type=OpDesc
320issueLat=1
321opClass=SimdAddAcc
322opLat=1
323
324[system.cpu0.fuPool.FUList5.opList02]
325type=OpDesc
326issueLat=1
327opClass=SimdAlu
328opLat=1
329
330[system.cpu0.fuPool.FUList5.opList03]
331type=OpDesc
332issueLat=1
333opClass=SimdCmp
334opLat=1
335
336[system.cpu0.fuPool.FUList5.opList04]
337type=OpDesc
338issueLat=1
339opClass=SimdCvt
340opLat=1
341
342[system.cpu0.fuPool.FUList5.opList05]
343type=OpDesc
344issueLat=1
345opClass=SimdMisc
346opLat=1
347
348[system.cpu0.fuPool.FUList5.opList06]
349type=OpDesc
350issueLat=1
351opClass=SimdMult
352opLat=1
353
354[system.cpu0.fuPool.FUList5.opList07]
355type=OpDesc
356issueLat=1
357opClass=SimdMultAcc
358opLat=1
359
360[system.cpu0.fuPool.FUList5.opList08]
361type=OpDesc
362issueLat=1
363opClass=SimdShift
364opLat=1
365
366[system.cpu0.fuPool.FUList5.opList09]
367type=OpDesc
368issueLat=1
369opClass=SimdShiftAcc
370opLat=1
371
372[system.cpu0.fuPool.FUList5.opList10]
373type=OpDesc
374issueLat=1
375opClass=SimdSqrt
376opLat=1
377
378[system.cpu0.fuPool.FUList5.opList11]
379type=OpDesc
380issueLat=1
381opClass=SimdFloatAdd
382opLat=1
383
384[system.cpu0.fuPool.FUList5.opList12]
385type=OpDesc
386issueLat=1
387opClass=SimdFloatAlu
388opLat=1
389
390[system.cpu0.fuPool.FUList5.opList13]
391type=OpDesc
392issueLat=1
393opClass=SimdFloatCmp
394opLat=1
395
396[system.cpu0.fuPool.FUList5.opList14]
397type=OpDesc
398issueLat=1
399opClass=SimdFloatCvt
400opLat=1
401
402[system.cpu0.fuPool.FUList5.opList15]
403type=OpDesc
404issueLat=1
405opClass=SimdFloatDiv
406opLat=1
407
408[system.cpu0.fuPool.FUList5.opList16]
409type=OpDesc
410issueLat=1
411opClass=SimdFloatMisc
412opLat=1
413
414[system.cpu0.fuPool.FUList5.opList17]
415type=OpDesc
416issueLat=1
417opClass=SimdFloatMult
418opLat=1
419
420[system.cpu0.fuPool.FUList5.opList18]
421type=OpDesc
422issueLat=1
423opClass=SimdFloatMultAcc
424opLat=1
425
426[system.cpu0.fuPool.FUList5.opList19]
427type=OpDesc
428issueLat=1
429opClass=SimdFloatSqrt
430opLat=1
431
432[system.cpu0.fuPool.FUList6]
433type=FUDesc
434children=opList
435count=0
436opList=system.cpu0.fuPool.FUList6.opList
437
438[system.cpu0.fuPool.FUList6.opList]
439type=OpDesc
440issueLat=1
441opClass=MemWrite
442opLat=1
443
444[system.cpu0.fuPool.FUList7]
445type=FUDesc
446children=opList0 opList1
447count=4
448opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
449
450[system.cpu0.fuPool.FUList7.opList0]
451type=OpDesc
452issueLat=1
453opClass=MemRead
454opLat=1
455
456[system.cpu0.fuPool.FUList7.opList1]
457type=OpDesc
458issueLat=1
459opClass=MemWrite
460opLat=1
461
462[system.cpu0.fuPool.FUList8]
463type=FUDesc
464children=opList
465count=1
466opList=system.cpu0.fuPool.FUList8.opList
467
468[system.cpu0.fuPool.FUList8.opList]
469type=OpDesc
470issueLat=3
471opClass=IprAccess
472opLat=3
473
474[system.cpu0.icache]
475type=BaseCache
| 220num_squash_per_cycle=2
221sys=system
222port=system.toL2Bus.slave[3]
223
224[system.cpu0.fuPool]
225type=FUPool
226children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
227FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
228
229[system.cpu0.fuPool.FUList0]
230type=FUDesc
231children=opList
232count=6
233opList=system.cpu0.fuPool.FUList0.opList
234
235[system.cpu0.fuPool.FUList0.opList]
236type=OpDesc
237issueLat=1
238opClass=IntAlu
239opLat=1
240
241[system.cpu0.fuPool.FUList1]
242type=FUDesc
243children=opList0 opList1
244count=2
245opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
246
247[system.cpu0.fuPool.FUList1.opList0]
248type=OpDesc
249issueLat=1
250opClass=IntMult
251opLat=3
252
253[system.cpu0.fuPool.FUList1.opList1]
254type=OpDesc
255issueLat=19
256opClass=IntDiv
257opLat=20
258
259[system.cpu0.fuPool.FUList2]
260type=FUDesc
261children=opList0 opList1 opList2
262count=4
263opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
264
265[system.cpu0.fuPool.FUList2.opList0]
266type=OpDesc
267issueLat=1
268opClass=FloatAdd
269opLat=2
270
271[system.cpu0.fuPool.FUList2.opList1]
272type=OpDesc
273issueLat=1
274opClass=FloatCmp
275opLat=2
276
277[system.cpu0.fuPool.FUList2.opList2]
278type=OpDesc
279issueLat=1
280opClass=FloatCvt
281opLat=2
282
283[system.cpu0.fuPool.FUList3]
284type=FUDesc
285children=opList0 opList1 opList2
286count=2
287opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
288
289[system.cpu0.fuPool.FUList3.opList0]
290type=OpDesc
291issueLat=1
292opClass=FloatMult
293opLat=4
294
295[system.cpu0.fuPool.FUList3.opList1]
296type=OpDesc
297issueLat=12
298opClass=FloatDiv
299opLat=12
300
301[system.cpu0.fuPool.FUList3.opList2]
302type=OpDesc
303issueLat=24
304opClass=FloatSqrt
305opLat=24
306
307[system.cpu0.fuPool.FUList4]
308type=FUDesc
309children=opList
310count=0
311opList=system.cpu0.fuPool.FUList4.opList
312
313[system.cpu0.fuPool.FUList4.opList]
314type=OpDesc
315issueLat=1
316opClass=MemRead
317opLat=1
318
319[system.cpu0.fuPool.FUList5]
320type=FUDesc
321children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
322count=4
323opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
324
325[system.cpu0.fuPool.FUList5.opList00]
326type=OpDesc
327issueLat=1
328opClass=SimdAdd
329opLat=1
330
331[system.cpu0.fuPool.FUList5.opList01]
332type=OpDesc
333issueLat=1
334opClass=SimdAddAcc
335opLat=1
336
337[system.cpu0.fuPool.FUList5.opList02]
338type=OpDesc
339issueLat=1
340opClass=SimdAlu
341opLat=1
342
343[system.cpu0.fuPool.FUList5.opList03]
344type=OpDesc
345issueLat=1
346opClass=SimdCmp
347opLat=1
348
349[system.cpu0.fuPool.FUList5.opList04]
350type=OpDesc
351issueLat=1
352opClass=SimdCvt
353opLat=1
354
355[system.cpu0.fuPool.FUList5.opList05]
356type=OpDesc
357issueLat=1
358opClass=SimdMisc
359opLat=1
360
361[system.cpu0.fuPool.FUList5.opList06]
362type=OpDesc
363issueLat=1
364opClass=SimdMult
365opLat=1
366
367[system.cpu0.fuPool.FUList5.opList07]
368type=OpDesc
369issueLat=1
370opClass=SimdMultAcc
371opLat=1
372
373[system.cpu0.fuPool.FUList5.opList08]
374type=OpDesc
375issueLat=1
376opClass=SimdShift
377opLat=1
378
379[system.cpu0.fuPool.FUList5.opList09]
380type=OpDesc
381issueLat=1
382opClass=SimdShiftAcc
383opLat=1
384
385[system.cpu0.fuPool.FUList5.opList10]
386type=OpDesc
387issueLat=1
388opClass=SimdSqrt
389opLat=1
390
391[system.cpu0.fuPool.FUList5.opList11]
392type=OpDesc
393issueLat=1
394opClass=SimdFloatAdd
395opLat=1
396
397[system.cpu0.fuPool.FUList5.opList12]
398type=OpDesc
399issueLat=1
400opClass=SimdFloatAlu
401opLat=1
402
403[system.cpu0.fuPool.FUList5.opList13]
404type=OpDesc
405issueLat=1
406opClass=SimdFloatCmp
407opLat=1
408
409[system.cpu0.fuPool.FUList5.opList14]
410type=OpDesc
411issueLat=1
412opClass=SimdFloatCvt
413opLat=1
414
415[system.cpu0.fuPool.FUList5.opList15]
416type=OpDesc
417issueLat=1
418opClass=SimdFloatDiv
419opLat=1
420
421[system.cpu0.fuPool.FUList5.opList16]
422type=OpDesc
423issueLat=1
424opClass=SimdFloatMisc
425opLat=1
426
427[system.cpu0.fuPool.FUList5.opList17]
428type=OpDesc
429issueLat=1
430opClass=SimdFloatMult
431opLat=1
432
433[system.cpu0.fuPool.FUList5.opList18]
434type=OpDesc
435issueLat=1
436opClass=SimdFloatMultAcc
437opLat=1
438
439[system.cpu0.fuPool.FUList5.opList19]
440type=OpDesc
441issueLat=1
442opClass=SimdFloatSqrt
443opLat=1
444
445[system.cpu0.fuPool.FUList6]
446type=FUDesc
447children=opList
448count=0
449opList=system.cpu0.fuPool.FUList6.opList
450
451[system.cpu0.fuPool.FUList6.opList]
452type=OpDesc
453issueLat=1
454opClass=MemWrite
455opLat=1
456
457[system.cpu0.fuPool.FUList7]
458type=FUDesc
459children=opList0 opList1
460count=4
461opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
462
463[system.cpu0.fuPool.FUList7.opList0]
464type=OpDesc
465issueLat=1
466opClass=MemRead
467opLat=1
468
469[system.cpu0.fuPool.FUList7.opList1]
470type=OpDesc
471issueLat=1
472opClass=MemWrite
473opLat=1
474
475[system.cpu0.fuPool.FUList8]
476type=FUDesc
477children=opList
478count=1
479opList=system.cpu0.fuPool.FUList8.opList
480
481[system.cpu0.fuPool.FUList8.opList]
482type=OpDesc
483issueLat=3
484opClass=IprAccess
485opLat=3
486
487[system.cpu0.icache]
488type=BaseCache
|
| 489children=tags
|
476addr_ranges=0:18446744073709551615
477assoc=1
| 490addr_ranges=0:18446744073709551615
491assoc=1
|
478block_size=64
479clock=500
| 492clk_domain=system.cpu_clk_domain
|
480forward_snoops=true
481hit_latency=2
482is_top_level=true
483max_miss_count=0
484mshrs=4
485prefetch_on_access=false
486prefetcher=Null
487response_latency=2
488size=32768
489system=system
| 493forward_snoops=true
494hit_latency=2
495is_top_level=true
496max_miss_count=0
497mshrs=4
498prefetch_on_access=false
499prefetcher=Null
500response_latency=2
501size=32768
502system=system
|
| 503tags=system.cpu0.icache.tags
|
490tgts_per_mshr=20
491two_queue=false
492write_buffers=8
493cpu_side=system.cpu0.icache_port
494mem_side=system.toL2Bus.slave[0]
495
| 504tgts_per_mshr=20
505two_queue=false
506write_buffers=8
507cpu_side=system.cpu0.icache_port
508mem_side=system.toL2Bus.slave[0]
509
|
| 510[system.cpu0.icache.tags]
511type=LRU
512assoc=1
513block_size=64
514clk_domain=system.cpu_clk_domain
515hit_latency=2
516size=32768
517
|
496[system.cpu0.interrupts]
497type=ArmInterrupts
498
499[system.cpu0.isa]
500type=ArmISA
501fpsid=1090793632
502id_isar0=34607377
503id_isar1=34677009
504id_isar2=555950401
505id_isar3=17899825
506id_isar4=268501314
507id_isar5=0
508id_mmfr0=3
509id_mmfr1=0
510id_mmfr2=19070976
511id_mmfr3=4027589137
512id_pfr0=49
513id_pfr1=1
514midr=890224640
515
516[system.cpu0.itb]
517type=ArmTLB
518children=walker
519size=64
520walker=system.cpu0.itb.walker
521
522[system.cpu0.itb.walker]
523type=ArmTableWalker
| 518[system.cpu0.interrupts]
519type=ArmInterrupts
520
521[system.cpu0.isa]
522type=ArmISA
523fpsid=1090793632
524id_isar0=34607377
525id_isar1=34677009
526id_isar2=555950401
527id_isar3=17899825
528id_isar4=268501314
529id_isar5=0
530id_mmfr0=3
531id_mmfr1=0
532id_mmfr2=19070976
533id_mmfr3=4027589137
534id_pfr0=49
535id_pfr1=1
536midr=890224640
537
538[system.cpu0.itb]
539type=ArmTLB
540children=walker
541size=64
542walker=system.cpu0.itb.walker
543
544[system.cpu0.itb.walker]
545type=ArmTableWalker
|
524clock=500
| 546clk_domain=system.cpu_clk_domain
|
525num_squash_per_cycle=2
526sys=system
527port=system.toL2Bus.slave[2]
528
529[system.cpu0.tracer]
530type=ExeTracer
531
532[system.cpu1]
533type=DerivO3CPU
534children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
535LFSTSize=1024
536LQEntries=32
537LSQCheckLoads=true
538LSQDepCheckShift=4
539SQEntries=32
540SSITSize=1024
541activity=0
542backComSize=5
543branchPred=system.cpu1.branchPred
544cachePorts=200
545checker=Null
| 547num_squash_per_cycle=2
548sys=system
549port=system.toL2Bus.slave[2]
550
551[system.cpu0.tracer]
552type=ExeTracer
553
554[system.cpu1]
555type=DerivO3CPU
556children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
557LFSTSize=1024
558LQEntries=32
559LSQCheckLoads=true
560LSQDepCheckShift=4
561SQEntries=32
562SSITSize=1024
563activity=0
564backComSize=5
565branchPred=system.cpu1.branchPred
566cachePorts=200
567checker=Null
|
546clock=500
| 568clk_domain=system.cpu_clk_domain
|
547commitToDecodeDelay=1
548commitToFetchDelay=1
549commitToIEWDelay=1
550commitToRenameDelay=1
551commitWidth=8
552cpu_id=1
553decodeToFetchDelay=1
554decodeToRenameDelay=1
555decodeWidth=8
556dispatchWidth=8
557do_checkpoint_insts=true
558do_quiesce=true
559do_statistics_insts=true
560dtb=system.cpu1.dtb
561fetchToDecodeDelay=1
562fetchTrapLatency=1
563fetchWidth=8
564forwardComSize=5
565fuPool=system.cpu1.fuPool
566function_trace=false
567function_trace_start=0
568iewToCommitDelay=1
569iewToDecodeDelay=1
570iewToFetchDelay=1
571iewToRenameDelay=1
572interrupts=system.cpu1.interrupts
573isa=system.cpu1.isa
574issueToExecuteDelay=1
575issueWidth=8
576itb=system.cpu1.itb
577max_insts_all_threads=0
578max_insts_any_thread=0
579max_loads_all_threads=0
580max_loads_any_thread=0
581needsTSO=false
582numIQEntries=64
583numPhysFloatRegs=256
584numPhysIntRegs=256
585numROBEntries=192
586numRobs=1
587numThreads=1
588profile=0
589progress_interval=0
590renameToDecodeDelay=1
591renameToFetchDelay=1
592renameToIEWDelay=2
593renameToROBDelay=1
594renameWidth=8
595simpoint_start_insts=
596smtCommitPolicy=RoundRobin
597smtFetchPolicy=SingleThread
598smtIQPolicy=Partitioned
599smtIQThreshold=100
600smtLSQPolicy=Partitioned
601smtLSQThreshold=100
602smtNumFetchingThreads=1
603smtROBPolicy=Partitioned
604smtROBThreshold=100
605squashWidth=8
606store_set_clear_period=250000
607switched_out=false
608system=system
609tracer=system.cpu1.tracer
610trapLatency=13
611wbDepth=1
612wbWidth=8
613workload=
614dcache_port=system.cpu1.dcache.cpu_side
615icache_port=system.cpu1.icache.cpu_side
616
617[system.cpu1.branchPred]
618type=BranchPredictor
619BTBEntries=4096
620BTBTagSize=16
621RASSize=16
622choiceCtrBits=2
623choicePredictorSize=8192
624globalCtrBits=2
| 569commitToDecodeDelay=1
570commitToFetchDelay=1
571commitToIEWDelay=1
572commitToRenameDelay=1
573commitWidth=8
574cpu_id=1
575decodeToFetchDelay=1
576decodeToRenameDelay=1
577decodeWidth=8
578dispatchWidth=8
579do_checkpoint_insts=true
580do_quiesce=true
581do_statistics_insts=true
582dtb=system.cpu1.dtb
583fetchToDecodeDelay=1
584fetchTrapLatency=1
585fetchWidth=8
586forwardComSize=5
587fuPool=system.cpu1.fuPool
588function_trace=false
589function_trace_start=0
590iewToCommitDelay=1
591iewToDecodeDelay=1
592iewToFetchDelay=1
593iewToRenameDelay=1
594interrupts=system.cpu1.interrupts
595isa=system.cpu1.isa
596issueToExecuteDelay=1
597issueWidth=8
598itb=system.cpu1.itb
599max_insts_all_threads=0
600max_insts_any_thread=0
601max_loads_all_threads=0
602max_loads_any_thread=0
603needsTSO=false
604numIQEntries=64
605numPhysFloatRegs=256
606numPhysIntRegs=256
607numROBEntries=192
608numRobs=1
609numThreads=1
610profile=0
611progress_interval=0
612renameToDecodeDelay=1
613renameToFetchDelay=1
614renameToIEWDelay=2
615renameToROBDelay=1
616renameWidth=8
617simpoint_start_insts=
618smtCommitPolicy=RoundRobin
619smtFetchPolicy=SingleThread
620smtIQPolicy=Partitioned
621smtIQThreshold=100
622smtLSQPolicy=Partitioned
623smtLSQThreshold=100
624smtNumFetchingThreads=1
625smtROBPolicy=Partitioned
626smtROBThreshold=100
627squashWidth=8
628store_set_clear_period=250000
629switched_out=false
630system=system
631tracer=system.cpu1.tracer
632trapLatency=13
633wbDepth=1
634wbWidth=8
635workload=
636dcache_port=system.cpu1.dcache.cpu_side
637icache_port=system.cpu1.icache.cpu_side
638
639[system.cpu1.branchPred]
640type=BranchPredictor
641BTBEntries=4096
642BTBTagSize=16
643RASSize=16
644choiceCtrBits=2
645choicePredictorSize=8192
646globalCtrBits=2
|
625globalHistoryBits=13
| |
626globalPredictorSize=8192
627instShiftAmt=2
628localCtrBits=2
| 647globalPredictorSize=8192
648instShiftAmt=2
649localCtrBits=2
|
629localHistoryBits=11
| |
630localHistoryTableSize=2048
631localPredictorSize=2048
632numThreads=1
633predType=tournament
634
635[system.cpu1.dcache]
636type=BaseCache
| 650localHistoryTableSize=2048
651localPredictorSize=2048
652numThreads=1
653predType=tournament
654
655[system.cpu1.dcache]
656type=BaseCache
|
| 657children=tags
|
637addr_ranges=0:18446744073709551615
638assoc=4
| 658addr_ranges=0:18446744073709551615
659assoc=4
|
639block_size=64
640clock=500
| 660clk_domain=system.cpu_clk_domain
|
641forward_snoops=true
642hit_latency=2
643is_top_level=true
644max_miss_count=0
645mshrs=4
646prefetch_on_access=false
647prefetcher=Null
648response_latency=2
649size=32768
650system=system
| 661forward_snoops=true
662hit_latency=2
663is_top_level=true
664max_miss_count=0
665mshrs=4
666prefetch_on_access=false
667prefetcher=Null
668response_latency=2
669size=32768
670system=system
|
| 671tags=system.cpu1.dcache.tags
|
651tgts_per_mshr=20
652two_queue=false
653write_buffers=8
654cpu_side=system.cpu1.dcache_port
655mem_side=system.toL2Bus.slave[5]
656
| 672tgts_per_mshr=20
673two_queue=false
674write_buffers=8
675cpu_side=system.cpu1.dcache_port
676mem_side=system.toL2Bus.slave[5]
677
|
| 678[system.cpu1.dcache.tags]
679type=LRU
680assoc=4
681block_size=64
682clk_domain=system.cpu_clk_domain
683hit_latency=2
684size=32768
685
|
657[system.cpu1.dtb]
658type=ArmTLB
659children=walker
660size=64
661walker=system.cpu1.dtb.walker
662
663[system.cpu1.dtb.walker]
664type=ArmTableWalker
| 686[system.cpu1.dtb]
687type=ArmTLB
688children=walker
689size=64
690walker=system.cpu1.dtb.walker
691
692[system.cpu1.dtb.walker]
693type=ArmTableWalker
|
665clock=500
| 694clk_domain=system.cpu_clk_domain
|
666num_squash_per_cycle=2
667sys=system
668port=system.toL2Bus.slave[7]
669
670[system.cpu1.fuPool]
671type=FUPool
672children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
673FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8
674
675[system.cpu1.fuPool.FUList0]
676type=FUDesc
677children=opList
678count=6
679opList=system.cpu1.fuPool.FUList0.opList
680
681[system.cpu1.fuPool.FUList0.opList]
682type=OpDesc
683issueLat=1
684opClass=IntAlu
685opLat=1
686
687[system.cpu1.fuPool.FUList1]
688type=FUDesc
689children=opList0 opList1
690count=2
691opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
692
693[system.cpu1.fuPool.FUList1.opList0]
694type=OpDesc
695issueLat=1
696opClass=IntMult
697opLat=3
698
699[system.cpu1.fuPool.FUList1.opList1]
700type=OpDesc
701issueLat=19
702opClass=IntDiv
703opLat=20
704
705[system.cpu1.fuPool.FUList2]
706type=FUDesc
707children=opList0 opList1 opList2
708count=4
709opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2
710
711[system.cpu1.fuPool.FUList2.opList0]
712type=OpDesc
713issueLat=1
714opClass=FloatAdd
715opLat=2
716
717[system.cpu1.fuPool.FUList2.opList1]
718type=OpDesc
719issueLat=1
720opClass=FloatCmp
721opLat=2
722
723[system.cpu1.fuPool.FUList2.opList2]
724type=OpDesc
725issueLat=1
726opClass=FloatCvt
727opLat=2
728
729[system.cpu1.fuPool.FUList3]
730type=FUDesc
731children=opList0 opList1 opList2
732count=2
733opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
734
735[system.cpu1.fuPool.FUList3.opList0]
736type=OpDesc
737issueLat=1
738opClass=FloatMult
739opLat=4
740
741[system.cpu1.fuPool.FUList3.opList1]
742type=OpDesc
743issueLat=12
744opClass=FloatDiv
745opLat=12
746
747[system.cpu1.fuPool.FUList3.opList2]
748type=OpDesc
749issueLat=24
750opClass=FloatSqrt
751opLat=24
752
753[system.cpu1.fuPool.FUList4]
754type=FUDesc
755children=opList
756count=0
757opList=system.cpu1.fuPool.FUList4.opList
758
759[system.cpu1.fuPool.FUList4.opList]
760type=OpDesc
761issueLat=1
762opClass=MemRead
763opLat=1
764
765[system.cpu1.fuPool.FUList5]
766type=FUDesc
767children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
768count=4
769opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
770
771[system.cpu1.fuPool.FUList5.opList00]
772type=OpDesc
773issueLat=1
774opClass=SimdAdd
775opLat=1
776
777[system.cpu1.fuPool.FUList5.opList01]
778type=OpDesc
779issueLat=1
780opClass=SimdAddAcc
781opLat=1
782
783[system.cpu1.fuPool.FUList5.opList02]
784type=OpDesc
785issueLat=1
786opClass=SimdAlu
787opLat=1
788
789[system.cpu1.fuPool.FUList5.opList03]
790type=OpDesc
791issueLat=1
792opClass=SimdCmp
793opLat=1
794
795[system.cpu1.fuPool.FUList5.opList04]
796type=OpDesc
797issueLat=1
798opClass=SimdCvt
799opLat=1
800
801[system.cpu1.fuPool.FUList5.opList05]
802type=OpDesc
803issueLat=1
804opClass=SimdMisc
805opLat=1
806
807[system.cpu1.fuPool.FUList5.opList06]
808type=OpDesc
809issueLat=1
810opClass=SimdMult
811opLat=1
812
813[system.cpu1.fuPool.FUList5.opList07]
814type=OpDesc
815issueLat=1
816opClass=SimdMultAcc
817opLat=1
818
819[system.cpu1.fuPool.FUList5.opList08]
820type=OpDesc
821issueLat=1
822opClass=SimdShift
823opLat=1
824
825[system.cpu1.fuPool.FUList5.opList09]
826type=OpDesc
827issueLat=1
828opClass=SimdShiftAcc
829opLat=1
830
831[system.cpu1.fuPool.FUList5.opList10]
832type=OpDesc
833issueLat=1
834opClass=SimdSqrt
835opLat=1
836
837[system.cpu1.fuPool.FUList5.opList11]
838type=OpDesc
839issueLat=1
840opClass=SimdFloatAdd
841opLat=1
842
843[system.cpu1.fuPool.FUList5.opList12]
844type=OpDesc
845issueLat=1
846opClass=SimdFloatAlu
847opLat=1
848
849[system.cpu1.fuPool.FUList5.opList13]
850type=OpDesc
851issueLat=1
852opClass=SimdFloatCmp
853opLat=1
854
855[system.cpu1.fuPool.FUList5.opList14]
856type=OpDesc
857issueLat=1
858opClass=SimdFloatCvt
859opLat=1
860
861[system.cpu1.fuPool.FUList5.opList15]
862type=OpDesc
863issueLat=1
864opClass=SimdFloatDiv
865opLat=1
866
867[system.cpu1.fuPool.FUList5.opList16]
868type=OpDesc
869issueLat=1
870opClass=SimdFloatMisc
871opLat=1
872
873[system.cpu1.fuPool.FUList5.opList17]
874type=OpDesc
875issueLat=1
876opClass=SimdFloatMult
877opLat=1
878
879[system.cpu1.fuPool.FUList5.opList18]
880type=OpDesc
881issueLat=1
882opClass=SimdFloatMultAcc
883opLat=1
884
885[system.cpu1.fuPool.FUList5.opList19]
886type=OpDesc
887issueLat=1
888opClass=SimdFloatSqrt
889opLat=1
890
891[system.cpu1.fuPool.FUList6]
892type=FUDesc
893children=opList
894count=0
895opList=system.cpu1.fuPool.FUList6.opList
896
897[system.cpu1.fuPool.FUList6.opList]
898type=OpDesc
899issueLat=1
900opClass=MemWrite
901opLat=1
902
903[system.cpu1.fuPool.FUList7]
904type=FUDesc
905children=opList0 opList1
906count=4
907opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
908
909[system.cpu1.fuPool.FUList7.opList0]
910type=OpDesc
911issueLat=1
912opClass=MemRead
913opLat=1
914
915[system.cpu1.fuPool.FUList7.opList1]
916type=OpDesc
917issueLat=1
918opClass=MemWrite
919opLat=1
920
921[system.cpu1.fuPool.FUList8]
922type=FUDesc
923children=opList
924count=1
925opList=system.cpu1.fuPool.FUList8.opList
926
927[system.cpu1.fuPool.FUList8.opList]
928type=OpDesc
929issueLat=3
930opClass=IprAccess
931opLat=3
932
933[system.cpu1.icache]
934type=BaseCache
| 695num_squash_per_cycle=2
696sys=system
697port=system.toL2Bus.slave[7]
698
699[system.cpu1.fuPool]
700type=FUPool
701children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
702FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8
703
704[system.cpu1.fuPool.FUList0]
705type=FUDesc
706children=opList
707count=6
708opList=system.cpu1.fuPool.FUList0.opList
709
710[system.cpu1.fuPool.FUList0.opList]
711type=OpDesc
712issueLat=1
713opClass=IntAlu
714opLat=1
715
716[system.cpu1.fuPool.FUList1]
717type=FUDesc
718children=opList0 opList1
719count=2
720opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
721
722[system.cpu1.fuPool.FUList1.opList0]
723type=OpDesc
724issueLat=1
725opClass=IntMult
726opLat=3
727
728[system.cpu1.fuPool.FUList1.opList1]
729type=OpDesc
730issueLat=19
731opClass=IntDiv
732opLat=20
733
734[system.cpu1.fuPool.FUList2]
735type=FUDesc
736children=opList0 opList1 opList2
737count=4
738opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2
739
740[system.cpu1.fuPool.FUList2.opList0]
741type=OpDesc
742issueLat=1
743opClass=FloatAdd
744opLat=2
745
746[system.cpu1.fuPool.FUList2.opList1]
747type=OpDesc
748issueLat=1
749opClass=FloatCmp
750opLat=2
751
752[system.cpu1.fuPool.FUList2.opList2]
753type=OpDesc
754issueLat=1
755opClass=FloatCvt
756opLat=2
757
758[system.cpu1.fuPool.FUList3]
759type=FUDesc
760children=opList0 opList1 opList2
761count=2
762opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
763
764[system.cpu1.fuPool.FUList3.opList0]
765type=OpDesc
766issueLat=1
767opClass=FloatMult
768opLat=4
769
770[system.cpu1.fuPool.FUList3.opList1]
771type=OpDesc
772issueLat=12
773opClass=FloatDiv
774opLat=12
775
776[system.cpu1.fuPool.FUList3.opList2]
777type=OpDesc
778issueLat=24
779opClass=FloatSqrt
780opLat=24
781
782[system.cpu1.fuPool.FUList4]
783type=FUDesc
784children=opList
785count=0
786opList=system.cpu1.fuPool.FUList4.opList
787
788[system.cpu1.fuPool.FUList4.opList]
789type=OpDesc
790issueLat=1
791opClass=MemRead
792opLat=1
793
794[system.cpu1.fuPool.FUList5]
795type=FUDesc
796children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
797count=4
798opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
799
800[system.cpu1.fuPool.FUList5.opList00]
801type=OpDesc
802issueLat=1
803opClass=SimdAdd
804opLat=1
805
806[system.cpu1.fuPool.FUList5.opList01]
807type=OpDesc
808issueLat=1
809opClass=SimdAddAcc
810opLat=1
811
812[system.cpu1.fuPool.FUList5.opList02]
813type=OpDesc
814issueLat=1
815opClass=SimdAlu
816opLat=1
817
818[system.cpu1.fuPool.FUList5.opList03]
819type=OpDesc
820issueLat=1
821opClass=SimdCmp
822opLat=1
823
824[system.cpu1.fuPool.FUList5.opList04]
825type=OpDesc
826issueLat=1
827opClass=SimdCvt
828opLat=1
829
830[system.cpu1.fuPool.FUList5.opList05]
831type=OpDesc
832issueLat=1
833opClass=SimdMisc
834opLat=1
835
836[system.cpu1.fuPool.FUList5.opList06]
837type=OpDesc
838issueLat=1
839opClass=SimdMult
840opLat=1
841
842[system.cpu1.fuPool.FUList5.opList07]
843type=OpDesc
844issueLat=1
845opClass=SimdMultAcc
846opLat=1
847
848[system.cpu1.fuPool.FUList5.opList08]
849type=OpDesc
850issueLat=1
851opClass=SimdShift
852opLat=1
853
854[system.cpu1.fuPool.FUList5.opList09]
855type=OpDesc
856issueLat=1
857opClass=SimdShiftAcc
858opLat=1
859
860[system.cpu1.fuPool.FUList5.opList10]
861type=OpDesc
862issueLat=1
863opClass=SimdSqrt
864opLat=1
865
866[system.cpu1.fuPool.FUList5.opList11]
867type=OpDesc
868issueLat=1
869opClass=SimdFloatAdd
870opLat=1
871
872[system.cpu1.fuPool.FUList5.opList12]
873type=OpDesc
874issueLat=1
875opClass=SimdFloatAlu
876opLat=1
877
878[system.cpu1.fuPool.FUList5.opList13]
879type=OpDesc
880issueLat=1
881opClass=SimdFloatCmp
882opLat=1
883
884[system.cpu1.fuPool.FUList5.opList14]
885type=OpDesc
886issueLat=1
887opClass=SimdFloatCvt
888opLat=1
889
890[system.cpu1.fuPool.FUList5.opList15]
891type=OpDesc
892issueLat=1
893opClass=SimdFloatDiv
894opLat=1
895
896[system.cpu1.fuPool.FUList5.opList16]
897type=OpDesc
898issueLat=1
899opClass=SimdFloatMisc
900opLat=1
901
902[system.cpu1.fuPool.FUList5.opList17]
903type=OpDesc
904issueLat=1
905opClass=SimdFloatMult
906opLat=1
907
908[system.cpu1.fuPool.FUList5.opList18]
909type=OpDesc
910issueLat=1
911opClass=SimdFloatMultAcc
912opLat=1
913
914[system.cpu1.fuPool.FUList5.opList19]
915type=OpDesc
916issueLat=1
917opClass=SimdFloatSqrt
918opLat=1
919
920[system.cpu1.fuPool.FUList6]
921type=FUDesc
922children=opList
923count=0
924opList=system.cpu1.fuPool.FUList6.opList
925
926[system.cpu1.fuPool.FUList6.opList]
927type=OpDesc
928issueLat=1
929opClass=MemWrite
930opLat=1
931
932[system.cpu1.fuPool.FUList7]
933type=FUDesc
934children=opList0 opList1
935count=4
936opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
937
938[system.cpu1.fuPool.FUList7.opList0]
939type=OpDesc
940issueLat=1
941opClass=MemRead
942opLat=1
943
944[system.cpu1.fuPool.FUList7.opList1]
945type=OpDesc
946issueLat=1
947opClass=MemWrite
948opLat=1
949
950[system.cpu1.fuPool.FUList8]
951type=FUDesc
952children=opList
953count=1
954opList=system.cpu1.fuPool.FUList8.opList
955
956[system.cpu1.fuPool.FUList8.opList]
957type=OpDesc
958issueLat=3
959opClass=IprAccess
960opLat=3
961
962[system.cpu1.icache]
963type=BaseCache
|
| 964children=tags
|
935addr_ranges=0:18446744073709551615
936assoc=1
| 965addr_ranges=0:18446744073709551615
966assoc=1
|
937block_size=64
938clock=500
| 967clk_domain=system.cpu_clk_domain
|
939forward_snoops=true
940hit_latency=2
941is_top_level=true
942max_miss_count=0
943mshrs=4
944prefetch_on_access=false
945prefetcher=Null
946response_latency=2
947size=32768
948system=system
| 968forward_snoops=true
969hit_latency=2
970is_top_level=true
971max_miss_count=0
972mshrs=4
973prefetch_on_access=false
974prefetcher=Null
975response_latency=2
976size=32768
977system=system
|
| 978tags=system.cpu1.icache.tags
|
949tgts_per_mshr=20
950two_queue=false
951write_buffers=8
952cpu_side=system.cpu1.icache_port
953mem_side=system.toL2Bus.slave[4]
954
| 979tgts_per_mshr=20
980two_queue=false
981write_buffers=8
982cpu_side=system.cpu1.icache_port
983mem_side=system.toL2Bus.slave[4]
984
|
| 985[system.cpu1.icache.tags]
986type=LRU
987assoc=1
988block_size=64
989clk_domain=system.cpu_clk_domain
990hit_latency=2
991size=32768
992
|
955[system.cpu1.interrupts]
956type=ArmInterrupts
957
958[system.cpu1.isa]
959type=ArmISA
960fpsid=1090793632
961id_isar0=34607377
962id_isar1=34677009
963id_isar2=555950401
964id_isar3=17899825
965id_isar4=268501314
966id_isar5=0
967id_mmfr0=3
968id_mmfr1=0
969id_mmfr2=19070976
970id_mmfr3=4027589137
971id_pfr0=49
972id_pfr1=1
973midr=890224640
974
975[system.cpu1.itb]
976type=ArmTLB
977children=walker
978size=64
979walker=system.cpu1.itb.walker
980
981[system.cpu1.itb.walker]
982type=ArmTableWalker
| 993[system.cpu1.interrupts]
994type=ArmInterrupts
995
996[system.cpu1.isa]
997type=ArmISA
998fpsid=1090793632
999id_isar0=34607377
1000id_isar1=34677009
1001id_isar2=555950401
1002id_isar3=17899825
1003id_isar4=268501314
1004id_isar5=0
1005id_mmfr0=3
1006id_mmfr1=0
1007id_mmfr2=19070976
1008id_mmfr3=4027589137
1009id_pfr0=49
1010id_pfr1=1
1011midr=890224640
1012
1013[system.cpu1.itb]
1014type=ArmTLB
1015children=walker
1016size=64
1017walker=system.cpu1.itb.walker
1018
1019[system.cpu1.itb.walker]
1020type=ArmTableWalker
|
983clock=500
| 1021clk_domain=system.cpu_clk_domain
|
984num_squash_per_cycle=2
985sys=system
986port=system.toL2Bus.slave[6]
987
988[system.cpu1.tracer]
989type=ExeTracer
990
| 1022num_squash_per_cycle=2
1023sys=system
1024port=system.toL2Bus.slave[6]
1025
1026[system.cpu1.tracer]
1027type=ExeTracer
1028
|
| 1029[system.cpu_clk_domain]
1030type=SrcClockDomain
1031clock=500
1032voltage_domain=system.voltage_domain
1033
|
991[system.intrctrl]
992type=IntrControl
993sys=system
994
995[system.iobus]
996type=NoncoherentBus
| 1034[system.intrctrl]
1035type=IntrControl
1036sys=system
1037
1038[system.iobus]
1039type=NoncoherentBus
|
997block_size=64
998clock=1000
| 1040clk_domain=system.clk_domain
|
999header_cycles=1
1000use_default_range=false
1001width=8
1002master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
1003slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
1004
1005[system.iocache]
1006type=BaseCache
| 1041header_cycles=1
1042use_default_range=false
1043width=8
1044master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
1045slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
1046
1047[system.iocache]
1048type=BaseCache
|
| 1049children=tags
|
1007addr_ranges=0:134217727
1008assoc=8
| 1050addr_ranges=0:134217727
1051assoc=8
|
1009block_size=64
1010clock=1000
| 1052clk_domain=system.clk_domain
|
1011forward_snoops=false
1012hit_latency=50
1013is_top_level=true
1014max_miss_count=0
1015mshrs=20
1016prefetch_on_access=false
1017prefetcher=Null
1018response_latency=50
1019size=1024
1020system=system
| 1053forward_snoops=false
1054hit_latency=50
1055is_top_level=true
1056max_miss_count=0
1057mshrs=20
1058prefetch_on_access=false
1059prefetcher=Null
1060response_latency=50
1061size=1024
1062system=system
|
| 1063tags=system.iocache.tags
|
1021tgts_per_mshr=12
1022two_queue=false
1023write_buffers=8
1024cpu_side=system.iobus.master[25]
1025mem_side=system.membus.slave[2]
1026
| 1064tgts_per_mshr=12
1065two_queue=false
1066write_buffers=8
1067cpu_side=system.iobus.master[25]
1068mem_side=system.membus.slave[2]
1069
|
| 1070[system.iocache.tags]
1071type=LRU
1072assoc=8
1073block_size=64
1074clk_domain=system.clk_domain
1075hit_latency=50
1076size=1024
1077
|
1027[system.l2c]
1028type=BaseCache
| 1078[system.l2c]
1079type=BaseCache
|
| 1080children=tags
|
1029addr_ranges=0:18446744073709551615
1030assoc=8
| 1081addr_ranges=0:18446744073709551615
1082assoc=8
|
1031block_size=64
1032clock=500
| 1083clk_domain=system.cpu_clk_domain
|
1033forward_snoops=true
1034hit_latency=20
1035is_top_level=false
1036max_miss_count=0
1037mshrs=20
1038prefetch_on_access=false
1039prefetcher=Null
1040response_latency=20
1041size=4194304
1042system=system
| 1084forward_snoops=true
1085hit_latency=20
1086is_top_level=false
1087max_miss_count=0
1088mshrs=20
1089prefetch_on_access=false
1090prefetcher=Null
1091response_latency=20
1092size=4194304
1093system=system
|
| 1094tags=system.l2c.tags
|
1043tgts_per_mshr=12
1044two_queue=false
1045write_buffers=8
1046cpu_side=system.toL2Bus.master[0]
1047mem_side=system.membus.slave[1]
1048
| 1095tgts_per_mshr=12
1096two_queue=false
1097write_buffers=8
1098cpu_side=system.toL2Bus.master[0]
1099mem_side=system.membus.slave[1]
1100
|
| 1101[system.l2c.tags]
1102type=LRU
1103assoc=8
1104block_size=64
1105clk_domain=system.cpu_clk_domain
1106hit_latency=20
1107size=4194304
1108
|
1049[system.membus]
1050type=CoherentBus
1051children=badaddr_responder
| 1109[system.membus]
1110type=CoherentBus
1111children=badaddr_responder
|
1052block_size=64
1053clock=1000
| 1112clk_domain=system.clk_domain
|
1054header_cycles=1
1055system=system
1056use_default_range=false
1057width=8
1058default=system.membus.badaddr_responder.pio
| 1113header_cycles=1
1114system=system
1115use_default_range=false
1116width=8
1117default=system.membus.badaddr_responder.pio
|
1059master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
| 1118master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
|
1060slave=system.system_port system.l2c.mem_side system.iocache.mem_side
1061
1062[system.membus.badaddr_responder]
1063type=IsaFake
| 1119slave=system.system_port system.l2c.mem_side system.iocache.mem_side
1120
1121[system.membus.badaddr_responder]
1122type=IsaFake
|
1064clock=1000
| 1123clk_domain=system.clk_domain
|
1065fake_mem=false
1066pio_addr=0
1067pio_latency=100000
1068pio_size=8
1069ret_bad_addr=true
1070ret_data16=65535
1071ret_data32=4294967295
1072ret_data64=18446744073709551615
1073ret_data8=255
1074system=system
1075update_data=false
1076warn_access=warn
1077pio=system.membus.default
1078
1079[system.physmem]
1080type=SimpleDRAM
1081activation_limit=4
| 1124fake_mem=false
1125pio_addr=0
1126pio_latency=100000
1127pio_size=8
1128ret_bad_addr=true
1129ret_data16=65535
1130ret_data32=4294967295
1131ret_data64=18446744073709551615
1132ret_data8=255
1133system=system
1134update_data=false
1135warn_access=warn
1136pio=system.membus.default
1137
1138[system.physmem]
1139type=SimpleDRAM
1140activation_limit=4
|
1082addr_mapping=openmap
| 1141addr_mapping=RaBaChCo
|
1083banks_per_rank=8
| 1142banks_per_rank=8
|
| 1143burst_length=8
|
1084channels=1
| 1144channels=1
|
1085clock=1000
| 1145clk_domain=system.clk_domain
|
1086conf_table_reported=true
| 1146conf_table_reported=true
|
| 1147device_bus_width=8
1148device_rowbuffer_size=1024
1149devices_per_rank=8
|
1087in_addr_map=true
| 1150in_addr_map=true
|
1088lines_per_rowbuffer=32
| |
1089mem_sched_policy=frfcfs
1090null=false
1091page_policy=open
1092range=0:134217727
1093ranks_per_channel=2
1094read_buffer_size=32
| 1151mem_sched_policy=frfcfs
1152null=false
1153page_policy=open
1154range=0:134217727
1155ranks_per_channel=2
1156read_buffer_size=32
|
| 1157static_backend_latency=10000
1158static_frontend_latency=10000
|
1095tBURST=5000
1096tCL=13750
1097tRCD=13750
1098tREFI=7800000
1099tRFC=300000
1100tRP=13750
1101tWTR=7500
1102tXAW=40000
1103write_buffer_size=32
1104write_thresh_perc=70
| 1159tBURST=5000
1160tCL=13750
1161tRCD=13750
1162tREFI=7800000
1163tRFC=300000
1164tRP=13750
1165tWTR=7500
1166tXAW=40000
1167write_buffer_size=32
1168write_thresh_perc=70
|
1105zero=false
1106port=system.membus.master[2]
| 1169port=system.membus.master[6]
|
1107
1108[system.realview]
1109type=RealView
1110children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
1111intrctrl=system.intrctrl
1112max_mem_size=268435456
1113mem_start_addr=0
1114pci_cfg_base=0
1115system=system
1116
1117[system.realview.a9scu]
1118type=A9SCU
| 1170
1171[system.realview]
1172type=RealView
1173children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
1174intrctrl=system.intrctrl
1175max_mem_size=268435456
1176mem_start_addr=0
1177pci_cfg_base=0
1178system=system
1179
1180[system.realview.a9scu]
1181type=A9SCU
|
1119clock=1000
| 1182clk_domain=system.clk_domain
|
1120pio_addr=520093696
1121pio_latency=100000
1122system=system
| 1183pio_addr=520093696
1184pio_latency=100000
1185system=system
|
1123pio=system.membus.master[5]
| 1186pio=system.membus.master[4]
|
1124
1125[system.realview.aaci_fake]
1126type=AmbaFake
1127amba_id=0
| 1187
1188[system.realview.aaci_fake]
1189type=AmbaFake
1190amba_id=0
|
1128clock=1000
| 1191clk_domain=system.clk_domain
|
1129ignore_access=false
1130pio_addr=268451840
1131pio_latency=100000
1132system=system
1133pio=system.iobus.master[21]
1134
1135[system.realview.cf_ctrl]
1136type=IdeController
1137BAR0=402653184
1138BAR0LegacyIO=true
1139BAR0Size=16
1140BAR1=402653440
1141BAR1LegacyIO=true
1142BAR1Size=1
1143BAR2=1
1144BAR2LegacyIO=false
1145BAR2Size=8
1146BAR3=1
1147BAR3LegacyIO=false
1148BAR3Size=4
1149BAR4=1
1150BAR4LegacyIO=false
1151BAR4Size=16
1152BAR5=1
1153BAR5LegacyIO=false
1154BAR5Size=0
1155BIST=0
1156CacheLineSize=0
1157CardbusCIS=0
1158ClassCode=1
1159Command=1
1160DeviceID=28945
1161ExpansionROM=0
1162HeaderType=0
1163InterruptLine=31
1164InterruptPin=1
1165LatencyTimer=0
1166MaximumLatency=0
1167MinimumGrant=0
1168ProgIF=133
1169Revision=0
1170Status=640
1171SubClassCode=1
1172SubsystemID=0
1173SubsystemVendorID=0
1174VendorID=32902
| 1192ignore_access=false
1193pio_addr=268451840
1194pio_latency=100000
1195system=system
1196pio=system.iobus.master[21]
1197
1198[system.realview.cf_ctrl]
1199type=IdeController
1200BAR0=402653184
1201BAR0LegacyIO=true
1202BAR0Size=16
1203BAR1=402653440
1204BAR1LegacyIO=true
1205BAR1Size=1
1206BAR2=1
1207BAR2LegacyIO=false
1208BAR2Size=8
1209BAR3=1
1210BAR3LegacyIO=false
1211BAR3Size=4
1212BAR4=1
1213BAR4LegacyIO=false
1214BAR4Size=16
1215BAR5=1
1216BAR5LegacyIO=false
1217BAR5Size=0
1218BIST=0
1219CacheLineSize=0
1220CardbusCIS=0
1221ClassCode=1
1222Command=1
1223DeviceID=28945
1224ExpansionROM=0
1225HeaderType=0
1226InterruptLine=31
1227InterruptPin=1
1228LatencyTimer=0
1229MaximumLatency=0
1230MinimumGrant=0
1231ProgIF=133
1232Revision=0
1233Status=640
1234SubClassCode=1
1235SubsystemID=0
1236SubsystemVendorID=0
1237VendorID=32902
|
1175clock=1000
| 1238clk_domain=system.clk_domain
|
1176config_latency=20000
1177ctrl_offset=2
1178disks=system.cf0
1179io_shift=1
1180pci_bus=2
1181pci_dev=7
1182pci_func=0
1183pio_latency=30000
1184platform=system.realview
1185system=system
1186config=system.iobus.master[8]
1187dma=system.iobus.slave[2]
1188pio=system.iobus.master[7]
1189
1190[system.realview.clcd]
1191type=Pl111
1192amba_id=1315089
| 1239config_latency=20000
1240ctrl_offset=2
1241disks=system.cf0
1242io_shift=1
1243pci_bus=2
1244pci_dev=7
1245pci_func=0
1246pio_latency=30000
1247platform=system.realview
1248system=system
1249config=system.iobus.master[8]
1250dma=system.iobus.slave[2]
1251pio=system.iobus.master[7]
1252
1253[system.realview.clcd]
1254type=Pl111
1255amba_id=1315089
|
1193clock=1000
| 1256clk_domain=system.clk_domain
|
1194gic=system.realview.gic
1195int_num=55
1196pio_addr=268566528
1197pio_latency=10000
1198pixel_clock=41667
1199system=system
1200vnc=system.vncserver
1201dma=system.iobus.slave[1]
1202pio=system.iobus.master[4]
1203
1204[system.realview.dmac_fake]
1205type=AmbaFake
1206amba_id=0
| 1257gic=system.realview.gic
1258int_num=55
1259pio_addr=268566528
1260pio_latency=10000
1261pixel_clock=41667
1262system=system
1263vnc=system.vncserver
1264dma=system.iobus.slave[1]
1265pio=system.iobus.master[4]
1266
1267[system.realview.dmac_fake]
1268type=AmbaFake
1269amba_id=0
|
1207clock=1000
| 1270clk_domain=system.clk_domain
|
1208ignore_access=false
1209pio_addr=268632064
1210pio_latency=100000
1211system=system
1212pio=system.iobus.master[9]
1213
1214[system.realview.flash_fake]
1215type=IsaFake
| 1271ignore_access=false
1272pio_addr=268632064
1273pio_latency=100000
1274system=system
1275pio=system.iobus.master[9]
1276
1277[system.realview.flash_fake]
1278type=IsaFake
|
1216clock=1000
| 1279clk_domain=system.clk_domain
|
1217fake_mem=true
1218pio_addr=1073741824
1219pio_latency=100000
1220pio_size=536870912
1221ret_bad_addr=false
1222ret_data16=65535
1223ret_data32=4294967295
1224ret_data64=18446744073709551615
1225ret_data8=255
1226system=system
1227update_data=false
1228warn_access=
1229pio=system.iobus.master[24]
1230
1231[system.realview.gic]
1232type=Pl390
| 1280fake_mem=true
1281pio_addr=1073741824
1282pio_latency=100000
1283pio_size=536870912
1284ret_bad_addr=false
1285ret_data16=65535
1286ret_data32=4294967295
1287ret_data64=18446744073709551615
1288ret_data8=255
1289system=system
1290update_data=false
1291warn_access=
1292pio=system.iobus.master[24]
1293
1294[system.realview.gic]
1295type=Pl390
|
1233clock=1000
| 1296clk_domain=system.clk_domain
|
1234cpu_addr=520093952
1235cpu_pio_delay=10000
1236dist_addr=520097792
1237dist_pio_delay=10000
1238int_latency=10000
1239it_lines=128
1240platform=system.realview
1241system=system
| 1297cpu_addr=520093952
1298cpu_pio_delay=10000
1299dist_addr=520097792
1300dist_pio_delay=10000
1301int_latency=10000
1302it_lines=128
1303platform=system.realview
1304system=system
|
1242pio=system.membus.master[3]
| 1305pio=system.membus.master[2]
|
1243
1244[system.realview.gpio0_fake]
1245type=AmbaFake
1246amba_id=0
| 1306
1307[system.realview.gpio0_fake]
1308type=AmbaFake
1309amba_id=0
|
1247clock=1000
| 1310clk_domain=system.clk_domain
|
1248ignore_access=false
1249pio_addr=268513280
1250pio_latency=100000
1251system=system
1252pio=system.iobus.master[16]
1253
1254[system.realview.gpio1_fake]
1255type=AmbaFake
1256amba_id=0
| 1311ignore_access=false
1312pio_addr=268513280
1313pio_latency=100000
1314system=system
1315pio=system.iobus.master[16]
1316
1317[system.realview.gpio1_fake]
1318type=AmbaFake
1319amba_id=0
|
1257clock=1000
| 1320clk_domain=system.clk_domain
|
1258ignore_access=false
1259pio_addr=268517376
1260pio_latency=100000
1261system=system
1262pio=system.iobus.master[17]
1263
1264[system.realview.gpio2_fake]
1265type=AmbaFake
1266amba_id=0
| 1321ignore_access=false
1322pio_addr=268517376
1323pio_latency=100000
1324system=system
1325pio=system.iobus.master[17]
1326
1327[system.realview.gpio2_fake]
1328type=AmbaFake
1329amba_id=0
|
1267clock=1000
| 1330clk_domain=system.clk_domain
|
1268ignore_access=false
1269pio_addr=268521472
1270pio_latency=100000
1271system=system
1272pio=system.iobus.master[18]
1273
1274[system.realview.kmi0]
1275type=Pl050
1276amba_id=1314896
| 1331ignore_access=false
1332pio_addr=268521472
1333pio_latency=100000
1334system=system
1335pio=system.iobus.master[18]
1336
1337[system.realview.kmi0]
1338type=Pl050
1339amba_id=1314896
|
1277clock=1000
| 1340clk_domain=system.clk_domain
|
1278gic=system.realview.gic
1279int_delay=1000000
1280int_num=52
1281is_mouse=false
1282pio_addr=268460032
1283pio_latency=100000
1284system=system
1285vnc=system.vncserver
1286pio=system.iobus.master[5]
1287
1288[system.realview.kmi1]
1289type=Pl050
1290amba_id=1314896
| 1341gic=system.realview.gic
1342int_delay=1000000
1343int_num=52
1344is_mouse=false
1345pio_addr=268460032
1346pio_latency=100000
1347system=system
1348vnc=system.vncserver
1349pio=system.iobus.master[5]
1350
1351[system.realview.kmi1]
1352type=Pl050
1353amba_id=1314896
|
1291clock=1000
| 1354clk_domain=system.clk_domain
|
1292gic=system.realview.gic
1293int_delay=1000000
1294int_num=53
1295is_mouse=true
1296pio_addr=268464128
1297pio_latency=100000
1298system=system
1299vnc=system.vncserver
1300pio=system.iobus.master[6]
1301
1302[system.realview.l2x0_fake]
1303type=IsaFake
| 1355gic=system.realview.gic
1356int_delay=1000000
1357int_num=53
1358is_mouse=true
1359pio_addr=268464128
1360pio_latency=100000
1361system=system
1362vnc=system.vncserver
1363pio=system.iobus.master[6]
1364
1365[system.realview.l2x0_fake]
1366type=IsaFake
|
1304clock=1000
| 1367clk_domain=system.clk_domain
|
1305fake_mem=false
1306pio_addr=520101888
1307pio_latency=100000
1308pio_size=4095
1309ret_bad_addr=false
1310ret_data16=65535
1311ret_data32=4294967295
1312ret_data64=18446744073709551615
1313ret_data8=255
1314system=system
1315update_data=false
1316warn_access=
| 1368fake_mem=false
1369pio_addr=520101888
1370pio_latency=100000
1371pio_size=4095
1372ret_bad_addr=false
1373ret_data16=65535
1374ret_data32=4294967295
1375ret_data64=18446744073709551615
1376ret_data8=255
1377system=system
1378update_data=false
1379warn_access=
|
1317pio=system.membus.master[4]
| 1380pio=system.membus.master[3]
|
1318
1319[system.realview.local_cpu_timer]
1320type=CpuLocalTimer
| 1381
1382[system.realview.local_cpu_timer]
1383type=CpuLocalTimer
|
1321clock=1000
| 1384clk_domain=system.clk_domain
|
1322gic=system.realview.gic
1323int_num_timer=29
1324int_num_watchdog=30
1325pio_addr=520095232
1326pio_latency=100000
1327system=system
| 1385gic=system.realview.gic
1386int_num_timer=29
1387int_num_watchdog=30
1388pio_addr=520095232
1389pio_latency=100000
1390system=system
|
1328pio=system.membus.master[6]
| 1391pio=system.membus.master[5]
|
1329
1330[system.realview.mmc_fake]
1331type=AmbaFake
1332amba_id=0
| 1392
1393[system.realview.mmc_fake]
1394type=AmbaFake
1395amba_id=0
|
1333clock=1000
| 1396clk_domain=system.clk_domain
|
1334ignore_access=false
1335pio_addr=268455936
1336pio_latency=100000
1337system=system
1338pio=system.iobus.master[22]
1339
1340[system.realview.nvmem]
1341type=SimpleMemory
1342bandwidth=73.000000
| 1397ignore_access=false
1398pio_addr=268455936
1399pio_latency=100000
1400system=system
1401pio=system.iobus.master[22]
1402
1403[system.realview.nvmem]
1404type=SimpleMemory
1405bandwidth=73.000000
|
1343clock=1000
| 1406clk_domain=system.clk_domain
|
1344conf_table_reported=false
1345in_addr_map=true
1346latency=30000
1347latency_var=0
1348null=false
1349range=2147483648:2214592511
| 1407conf_table_reported=false
1408in_addr_map=true
1409latency=30000
1410latency_var=0
1411null=false
1412range=2147483648:2214592511
|
1350zero=true
| |
1351port=system.membus.master[1]
1352
1353[system.realview.realview_io]
1354type=RealViewCtrl
| 1413port=system.membus.master[1]
1414
1415[system.realview.realview_io]
1416type=RealViewCtrl
|
1355clock=1000
| 1417clk_domain=system.clk_domain
|
1356idreg=0
1357pio_addr=268435456
1358pio_latency=100000
1359proc_id0=201326592
1360proc_id1=201327138
1361system=system
1362pio=system.iobus.master[1]
1363
1364[system.realview.rtc]
1365type=PL031
1366amba_id=3412017
| 1418idreg=0
1419pio_addr=268435456
1420pio_latency=100000
1421proc_id0=201326592
1422proc_id1=201327138
1423system=system
1424pio=system.iobus.master[1]
1425
1426[system.realview.rtc]
1427type=PL031
1428amba_id=3412017
|
1367clock=1000
| 1429clk_domain=system.clk_domain
|
1368gic=system.realview.gic
1369int_delay=100000
1370int_num=42
1371pio_addr=268529664
1372pio_latency=100000
1373system=system
1374time=Thu Jan 1 00:00:00 2009
1375pio=system.iobus.master[23]
1376
1377[system.realview.sci_fake]
1378type=AmbaFake
1379amba_id=0
| 1430gic=system.realview.gic
1431int_delay=100000
1432int_num=42
1433pio_addr=268529664
1434pio_latency=100000
1435system=system
1436time=Thu Jan 1 00:00:00 2009
1437pio=system.iobus.master[23]
1438
1439[system.realview.sci_fake]
1440type=AmbaFake
1441amba_id=0
|
1380clock=1000
| 1442clk_domain=system.clk_domain
|
1381ignore_access=false
1382pio_addr=268492800
1383pio_latency=100000
1384system=system
1385pio=system.iobus.master[20]
1386
1387[system.realview.smc_fake]
1388type=AmbaFake
1389amba_id=0
| 1443ignore_access=false
1444pio_addr=268492800
1445pio_latency=100000
1446system=system
1447pio=system.iobus.master[20]
1448
1449[system.realview.smc_fake]
1450type=AmbaFake
1451amba_id=0
|
1390clock=1000
| 1452clk_domain=system.clk_domain
|
1391ignore_access=false
1392pio_addr=269357056
1393pio_latency=100000
1394system=system
1395pio=system.iobus.master[13]
1396
1397[system.realview.sp810_fake]
1398type=AmbaFake
1399amba_id=0
| 1453ignore_access=false
1454pio_addr=269357056
1455pio_latency=100000
1456system=system
1457pio=system.iobus.master[13]
1458
1459[system.realview.sp810_fake]
1460type=AmbaFake
1461amba_id=0
|
1400clock=1000
| 1462clk_domain=system.clk_domain
|
1401ignore_access=true
1402pio_addr=268439552
1403pio_latency=100000
1404system=system
1405pio=system.iobus.master[14]
1406
1407[system.realview.ssp_fake]
1408type=AmbaFake
1409amba_id=0
| 1463ignore_access=true
1464pio_addr=268439552
1465pio_latency=100000
1466system=system
1467pio=system.iobus.master[14]
1468
1469[system.realview.ssp_fake]
1470type=AmbaFake
1471amba_id=0
|
1410clock=1000
| 1472clk_domain=system.clk_domain
|
1411ignore_access=false
1412pio_addr=268488704
1413pio_latency=100000
1414system=system
1415pio=system.iobus.master[19]
1416
1417[system.realview.timer0]
1418type=Sp804
1419amba_id=1316868
| 1473ignore_access=false
1474pio_addr=268488704
1475pio_latency=100000
1476system=system
1477pio=system.iobus.master[19]
1478
1479[system.realview.timer0]
1480type=Sp804
1481amba_id=1316868
|
1420clock=1000
| 1482clk_domain=system.clk_domain
|
1421clock0=1000000
1422clock1=1000000
1423gic=system.realview.gic
1424int_num0=36
1425int_num1=36
1426pio_addr=268505088
1427pio_latency=100000
1428system=system
1429pio=system.iobus.master[2]
1430
1431[system.realview.timer1]
1432type=Sp804
1433amba_id=1316868
| 1483clock0=1000000
1484clock1=1000000
1485gic=system.realview.gic
1486int_num0=36
1487int_num1=36
1488pio_addr=268505088
1489pio_latency=100000
1490system=system
1491pio=system.iobus.master[2]
1492
1493[system.realview.timer1]
1494type=Sp804
1495amba_id=1316868
|
1434clock=1000
| 1496clk_domain=system.clk_domain
|
1435clock0=1000000
1436clock1=1000000
1437gic=system.realview.gic
1438int_num0=37
1439int_num1=37
1440pio_addr=268509184
1441pio_latency=100000
1442system=system
1443pio=system.iobus.master[3]
1444
1445[system.realview.uart]
1446type=Pl011
| 1497clock0=1000000
1498clock1=1000000
1499gic=system.realview.gic
1500int_num0=37
1501int_num1=37
1502pio_addr=268509184
1503pio_latency=100000
1504system=system
1505pio=system.iobus.master[3]
1506
1507[system.realview.uart]
1508type=Pl011
|
1447clock=1000
| 1509clk_domain=system.clk_domain
|
1448end_on_eot=false
1449gic=system.realview.gic
1450int_delay=100000
1451int_num=44
1452pio_addr=268472320
1453pio_latency=100000
1454platform=system.realview
1455system=system
1456terminal=system.terminal
1457pio=system.iobus.master[0]
1458
1459[system.realview.uart1_fake]
1460type=AmbaFake
1461amba_id=0
| 1510end_on_eot=false
1511gic=system.realview.gic
1512int_delay=100000
1513int_num=44
1514pio_addr=268472320
1515pio_latency=100000
1516platform=system.realview
1517system=system
1518terminal=system.terminal
1519pio=system.iobus.master[0]
1520
1521[system.realview.uart1_fake]
1522type=AmbaFake
1523amba_id=0
|
1462clock=1000
| 1524clk_domain=system.clk_domain
|
1463ignore_access=false
1464pio_addr=268476416
1465pio_latency=100000
1466system=system
1467pio=system.iobus.master[10]
1468
1469[system.realview.uart2_fake]
1470type=AmbaFake
1471amba_id=0
| 1525ignore_access=false
1526pio_addr=268476416
1527pio_latency=100000
1528system=system
1529pio=system.iobus.master[10]
1530
1531[system.realview.uart2_fake]
1532type=AmbaFake
1533amba_id=0
|
1472clock=1000
| 1534clk_domain=system.clk_domain
|
1473ignore_access=false
1474pio_addr=268480512
1475pio_latency=100000
1476system=system
1477pio=system.iobus.master[11]
1478
1479[system.realview.uart3_fake]
1480type=AmbaFake
1481amba_id=0
| 1535ignore_access=false
1536pio_addr=268480512
1537pio_latency=100000
1538system=system
1539pio=system.iobus.master[11]
1540
1541[system.realview.uart3_fake]
1542type=AmbaFake
1543amba_id=0
|
1482clock=1000
| 1544clk_domain=system.clk_domain
|
1483ignore_access=false
1484pio_addr=268484608
1485pio_latency=100000
1486system=system
1487pio=system.iobus.master[12]
1488
1489[system.realview.watchdog_fake]
1490type=AmbaFake
1491amba_id=0
| 1545ignore_access=false
1546pio_addr=268484608
1547pio_latency=100000
1548system=system
1549pio=system.iobus.master[12]
1550
1551[system.realview.watchdog_fake]
1552type=AmbaFake
1553amba_id=0
|
1492clock=1000
| 1554clk_domain=system.clk_domain
|
1493ignore_access=false
1494pio_addr=268500992
1495pio_latency=100000
1496system=system
1497pio=system.iobus.master[15]
1498
1499[system.terminal]
1500type=Terminal
1501intr_control=system.intrctrl
1502number=0
1503output=true
1504port=3456
1505
1506[system.toL2Bus]
1507type=CoherentBus
| 1555ignore_access=false
1556pio_addr=268500992
1557pio_latency=100000
1558system=system
1559pio=system.iobus.master[15]
1560
1561[system.terminal]
1562type=Terminal
1563intr_control=system.intrctrl
1564number=0
1565output=true
1566port=3456
1567
1568[system.toL2Bus]
1569type=CoherentBus
|
1508block_size=64
1509clock=500
| 1570clk_domain=system.cpu_clk_domain
|
1510header_cycles=1
1511system=system
1512use_default_range=false
1513width=8
1514master=system.l2c.cpu_side
1515slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
1516
1517[system.vncserver]
1518type=VncServer
1519frame_capture=false
1520number=0
1521port=5900
1522
| 1571header_cycles=1
1572system=system
1573use_default_range=false
1574width=8
1575master=system.l2c.cpu_side
1576slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
1577
1578[system.vncserver]
1579type=VncServer
1580frame_capture=false
1581number=0
1582port=5900
1583
|
| 1584[system.voltage_domain]
1585type=VoltageDomain
1586voltage=1.000000
1587
|
| |