1[root]
2type=Root
3children=system
4full_system=true
5time_sync_enable=false
6time_sync_period=100000000000
7time_sync_spin_threshold=100000000
8
9[system]
10type=LinuxArmSystem
11children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
12atags_addr=256
13boot_loader=/projects/pd/randd/dist/binaries/boot.arm
14boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
| 1[root]
2type=Root
3children=system
4full_system=true
5time_sync_enable=false
6time_sync_period=100000000000
7time_sync_spin_threshold=100000000
8
9[system]
10type=LinuxArmSystem
11children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
12atags_addr=256
13boot_loader=/projects/pd/randd/dist/binaries/boot.arm
14boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
15clock=1
| 15clock=1000
|
16dtb_filename=
17early_kernel_symbols=false
| 16dtb_filename=
17early_kernel_symbols=false
|
| 18enable_context_switch_stats_dump=false
|
18flags_addr=268435504
19gic_cpu_addr=520093952
20init_param=0
21kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
22load_addr_mask=268435455
23machine_type=RealView_PBX
24mem_mode=timing
25memories=system.physmem system.realview.nvmem
| 19flags_addr=268435504
20gic_cpu_addr=520093952
21init_param=0
22kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
23load_addr_mask=268435455
24machine_type=RealView_PBX
25mem_mode=timing
26memories=system.physmem system.realview.nvmem
|
26midr_regval=890224640
| |
27multi_proc=true
28num_work_ids=16
29readfile=tests/halt.sh
30symbolfile=
31work_begin_ckpt_count=0
32work_begin_cpu_id_exit=-1
33work_begin_exit_count=0
34work_cpus_ckpt_count=0
35work_end_ckpt_count=0
36work_end_exit_count=0
37work_item_id=-1
38system_port=system.membus.slave[0]
39
40[system.bridge]
41type=Bridge
| 27multi_proc=true
28num_work_ids=16
29readfile=tests/halt.sh
30symbolfile=
31work_begin_ckpt_count=0
32work_begin_cpu_id_exit=-1
33work_begin_exit_count=0
34work_cpus_ckpt_count=0
35work_end_ckpt_count=0
36work_end_exit_count=0
37work_item_id=-1
38system_port=system.membus.slave[0]
39
40[system.bridge]
41type=Bridge
|
42clock=1
| 42clock=1000
|
43delay=50000
44ranges=268435456:520093695 1073741824:1610612735
45req_size=16
46resp_size=16
47master=system.iobus.slave[0]
48slave=system.membus.master[0]
49
50[system.cf0]
51type=IdeDisk
52children=image
53delay=1000000
54driveID=master
55image=system.cf0.image
56
57[system.cf0.image]
58type=CowDiskImage
59children=child
60child=system.cf0.image.child
61image_file=
62read_only=false
63table_size=65536
64
65[system.cf0.image.child]
66type=RawDiskImage
67image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
68read_only=true
69
70[system.cpu0]
71type=DerivO3CPU
| 43delay=50000
44ranges=268435456:520093695 1073741824:1610612735
45req_size=16
46resp_size=16
47master=system.iobus.slave[0]
48slave=system.membus.master[0]
49
50[system.cf0]
51type=IdeDisk
52children=image
53delay=1000000
54driveID=master
55image=system.cf0.image
56
57[system.cf0.image]
58type=CowDiskImage
59children=child
60child=system.cf0.image.child
61image_file=
62read_only=false
63table_size=65536
64
65[system.cf0.image.child]
66type=RawDiskImage
67image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
68read_only=true
69
70[system.cpu0]
71type=DerivO3CPU
|
72children=dcache dtb fuPool icache interrupts itb tracer
| 72children=dcache dtb fuPool icache interrupts isa itb tracer
|
73BTBEntries=4096
74BTBTagSize=16
75LFSTSize=1024
76LQEntries=32
77LSQCheckLoads=true
78LSQDepCheckShift=4
79RASSize=16
80SQEntries=32
81SSITSize=1024
82activity=0
83backComSize=5
84cachePorts=200
85checker=Null
86choiceCtrBits=2
87choicePredictorSize=8192
88clock=500
89commitToDecodeDelay=1
90commitToFetchDelay=1
91commitToIEWDelay=1
92commitToRenameDelay=1
93commitWidth=8
94cpu_id=0
95decodeToFetchDelay=1
96decodeToRenameDelay=1
97decodeWidth=8
98defer_registration=false
99dispatchWidth=8
100do_checkpoint_insts=true
101do_quiesce=true
102do_statistics_insts=true
103dtb=system.cpu0.dtb
104fetchToDecodeDelay=1
105fetchTrapLatency=1
106fetchWidth=8
107forwardComSize=5
108fuPool=system.cpu0.fuPool
109function_trace=false
110function_trace_start=0
111globalCtrBits=2
112globalHistoryBits=13
113globalPredictorSize=8192
114iewToCommitDelay=1
115iewToDecodeDelay=1
116iewToFetchDelay=1
117iewToRenameDelay=1
118instShiftAmt=2
119interrupts=system.cpu0.interrupts
| 73BTBEntries=4096
74BTBTagSize=16
75LFSTSize=1024
76LQEntries=32
77LSQCheckLoads=true
78LSQDepCheckShift=4
79RASSize=16
80SQEntries=32
81SSITSize=1024
82activity=0
83backComSize=5
84cachePorts=200
85checker=Null
86choiceCtrBits=2
87choicePredictorSize=8192
88clock=500
89commitToDecodeDelay=1
90commitToFetchDelay=1
91commitToIEWDelay=1
92commitToRenameDelay=1
93commitWidth=8
94cpu_id=0
95decodeToFetchDelay=1
96decodeToRenameDelay=1
97decodeWidth=8
98defer_registration=false
99dispatchWidth=8
100do_checkpoint_insts=true
101do_quiesce=true
102do_statistics_insts=true
103dtb=system.cpu0.dtb
104fetchToDecodeDelay=1
105fetchTrapLatency=1
106fetchWidth=8
107forwardComSize=5
108fuPool=system.cpu0.fuPool
109function_trace=false
110function_trace_start=0
111globalCtrBits=2
112globalHistoryBits=13
113globalPredictorSize=8192
114iewToCommitDelay=1
115iewToDecodeDelay=1
116iewToFetchDelay=1
117iewToRenameDelay=1
118instShiftAmt=2
119interrupts=system.cpu0.interrupts
|
| 120isa=system.cpu0.isa
|
120issueToExecuteDelay=1
121issueWidth=8
122itb=system.cpu0.itb
123localCtrBits=2
124localHistoryBits=11
125localHistoryTableSize=2048
126localPredictorSize=2048
127max_insts_all_threads=0
128max_insts_any_thread=0
129max_loads_all_threads=0
130max_loads_any_thread=0
131needsTSO=false
132numIQEntries=64
133numPhysFloatRegs=256
134numPhysIntRegs=256
135numROBEntries=192
136numRobs=1
137numThreads=1
138predType=tournament
139profile=0
140progress_interval=0
141renameToDecodeDelay=1
142renameToFetchDelay=1
143renameToIEWDelay=2
144renameToROBDelay=1
145renameWidth=8
146smtCommitPolicy=RoundRobin
147smtFetchPolicy=SingleThread
148smtIQPolicy=Partitioned
149smtIQThreshold=100
150smtLSQPolicy=Partitioned
151smtLSQThreshold=100
152smtNumFetchingThreads=1
153smtROBPolicy=Partitioned
154smtROBThreshold=100
155squashWidth=8
156store_set_clear_period=250000
157system=system
158tracer=system.cpu0.tracer
159trapLatency=13
160wbDepth=1
161wbWidth=8
162workload=
163dcache_port=system.cpu0.dcache.cpu_side
164icache_port=system.cpu0.icache.cpu_side
165
166[system.cpu0.dcache]
167type=BaseCache
168addr_ranges=0:18446744073709551615
169assoc=4
170block_size=64
| 121issueToExecuteDelay=1
122issueWidth=8
123itb=system.cpu0.itb
124localCtrBits=2
125localHistoryBits=11
126localHistoryTableSize=2048
127localPredictorSize=2048
128max_insts_all_threads=0
129max_insts_any_thread=0
130max_loads_all_threads=0
131max_loads_any_thread=0
132needsTSO=false
133numIQEntries=64
134numPhysFloatRegs=256
135numPhysIntRegs=256
136numROBEntries=192
137numRobs=1
138numThreads=1
139predType=tournament
140profile=0
141progress_interval=0
142renameToDecodeDelay=1
143renameToFetchDelay=1
144renameToIEWDelay=2
145renameToROBDelay=1
146renameWidth=8
147smtCommitPolicy=RoundRobin
148smtFetchPolicy=SingleThread
149smtIQPolicy=Partitioned
150smtIQThreshold=100
151smtLSQPolicy=Partitioned
152smtLSQThreshold=100
153smtNumFetchingThreads=1
154smtROBPolicy=Partitioned
155smtROBThreshold=100
156squashWidth=8
157store_set_clear_period=250000
158system=system
159tracer=system.cpu0.tracer
160trapLatency=13
161wbDepth=1
162wbWidth=8
163workload=
164dcache_port=system.cpu0.dcache.cpu_side
165icache_port=system.cpu0.icache.cpu_side
166
167[system.cpu0.dcache]
168type=BaseCache
169addr_ranges=0:18446744073709551615
170assoc=4
171block_size=64
|
171clock=1
| 172clock=500
|
172forward_snoops=true
173hash_delay=1
| 173forward_snoops=true
174hash_delay=1
|
174hit_latency=1000
| 175hit_latency=2
|
175is_top_level=true
176max_miss_count=0
177mshrs=4
178prefetch_on_access=false
179prefetcher=Null
180prioritizeRequests=false
181repl=Null
| 176is_top_level=true
177max_miss_count=0
178mshrs=4
179prefetch_on_access=false
180prefetcher=Null
181prioritizeRequests=false
182repl=Null
|
182response_latency=1000
| 183response_latency=2
|
183size=32768
184subblock_size=0
185system=system
186tgts_per_mshr=20
187trace_addr=0
188two_queue=false
189write_buffers=8
190cpu_side=system.cpu0.dcache_port
191mem_side=system.toL2Bus.slave[1]
192
193[system.cpu0.dtb]
194type=ArmTLB
195children=walker
196size=64
197walker=system.cpu0.dtb.walker
198
199[system.cpu0.dtb.walker]
200type=ArmTableWalker
| 184size=32768
185subblock_size=0
186system=system
187tgts_per_mshr=20
188trace_addr=0
189two_queue=false
190write_buffers=8
191cpu_side=system.cpu0.dcache_port
192mem_side=system.toL2Bus.slave[1]
193
194[system.cpu0.dtb]
195type=ArmTLB
196children=walker
197size=64
198walker=system.cpu0.dtb.walker
199
200[system.cpu0.dtb.walker]
201type=ArmTableWalker
|
201clock=1
| 202clock=500
|
202num_squash_per_cycle=2
203sys=system
204port=system.toL2Bus.slave[3]
205
206[system.cpu0.fuPool]
207type=FUPool
208children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
209FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
210
211[system.cpu0.fuPool.FUList0]
212type=FUDesc
213children=opList
214count=6
215opList=system.cpu0.fuPool.FUList0.opList
216
217[system.cpu0.fuPool.FUList0.opList]
218type=OpDesc
219issueLat=1
220opClass=IntAlu
221opLat=1
222
223[system.cpu0.fuPool.FUList1]
224type=FUDesc
225children=opList0 opList1
226count=2
227opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
228
229[system.cpu0.fuPool.FUList1.opList0]
230type=OpDesc
231issueLat=1
232opClass=IntMult
233opLat=3
234
235[system.cpu0.fuPool.FUList1.opList1]
236type=OpDesc
237issueLat=19
238opClass=IntDiv
239opLat=20
240
241[system.cpu0.fuPool.FUList2]
242type=FUDesc
243children=opList0 opList1 opList2
244count=4
245opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
246
247[system.cpu0.fuPool.FUList2.opList0]
248type=OpDesc
249issueLat=1
250opClass=FloatAdd
251opLat=2
252
253[system.cpu0.fuPool.FUList2.opList1]
254type=OpDesc
255issueLat=1
256opClass=FloatCmp
257opLat=2
258
259[system.cpu0.fuPool.FUList2.opList2]
260type=OpDesc
261issueLat=1
262opClass=FloatCvt
263opLat=2
264
265[system.cpu0.fuPool.FUList3]
266type=FUDesc
267children=opList0 opList1 opList2
268count=2
269opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
270
271[system.cpu0.fuPool.FUList3.opList0]
272type=OpDesc
273issueLat=1
274opClass=FloatMult
275opLat=4
276
277[system.cpu0.fuPool.FUList3.opList1]
278type=OpDesc
279issueLat=12
280opClass=FloatDiv
281opLat=12
282
283[system.cpu0.fuPool.FUList3.opList2]
284type=OpDesc
285issueLat=24
286opClass=FloatSqrt
287opLat=24
288
289[system.cpu0.fuPool.FUList4]
290type=FUDesc
291children=opList
292count=0
293opList=system.cpu0.fuPool.FUList4.opList
294
295[system.cpu0.fuPool.FUList4.opList]
296type=OpDesc
297issueLat=1
298opClass=MemRead
299opLat=1
300
301[system.cpu0.fuPool.FUList5]
302type=FUDesc
303children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
304count=4
305opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
306
307[system.cpu0.fuPool.FUList5.opList00]
308type=OpDesc
309issueLat=1
310opClass=SimdAdd
311opLat=1
312
313[system.cpu0.fuPool.FUList5.opList01]
314type=OpDesc
315issueLat=1
316opClass=SimdAddAcc
317opLat=1
318
319[system.cpu0.fuPool.FUList5.opList02]
320type=OpDesc
321issueLat=1
322opClass=SimdAlu
323opLat=1
324
325[system.cpu0.fuPool.FUList5.opList03]
326type=OpDesc
327issueLat=1
328opClass=SimdCmp
329opLat=1
330
331[system.cpu0.fuPool.FUList5.opList04]
332type=OpDesc
333issueLat=1
334opClass=SimdCvt
335opLat=1
336
337[system.cpu0.fuPool.FUList5.opList05]
338type=OpDesc
339issueLat=1
340opClass=SimdMisc
341opLat=1
342
343[system.cpu0.fuPool.FUList5.opList06]
344type=OpDesc
345issueLat=1
346opClass=SimdMult
347opLat=1
348
349[system.cpu0.fuPool.FUList5.opList07]
350type=OpDesc
351issueLat=1
352opClass=SimdMultAcc
353opLat=1
354
355[system.cpu0.fuPool.FUList5.opList08]
356type=OpDesc
357issueLat=1
358opClass=SimdShift
359opLat=1
360
361[system.cpu0.fuPool.FUList5.opList09]
362type=OpDesc
363issueLat=1
364opClass=SimdShiftAcc
365opLat=1
366
367[system.cpu0.fuPool.FUList5.opList10]
368type=OpDesc
369issueLat=1
370opClass=SimdSqrt
371opLat=1
372
373[system.cpu0.fuPool.FUList5.opList11]
374type=OpDesc
375issueLat=1
376opClass=SimdFloatAdd
377opLat=1
378
379[system.cpu0.fuPool.FUList5.opList12]
380type=OpDesc
381issueLat=1
382opClass=SimdFloatAlu
383opLat=1
384
385[system.cpu0.fuPool.FUList5.opList13]
386type=OpDesc
387issueLat=1
388opClass=SimdFloatCmp
389opLat=1
390
391[system.cpu0.fuPool.FUList5.opList14]
392type=OpDesc
393issueLat=1
394opClass=SimdFloatCvt
395opLat=1
396
397[system.cpu0.fuPool.FUList5.opList15]
398type=OpDesc
399issueLat=1
400opClass=SimdFloatDiv
401opLat=1
402
403[system.cpu0.fuPool.FUList5.opList16]
404type=OpDesc
405issueLat=1
406opClass=SimdFloatMisc
407opLat=1
408
409[system.cpu0.fuPool.FUList5.opList17]
410type=OpDesc
411issueLat=1
412opClass=SimdFloatMult
413opLat=1
414
415[system.cpu0.fuPool.FUList5.opList18]
416type=OpDesc
417issueLat=1
418opClass=SimdFloatMultAcc
419opLat=1
420
421[system.cpu0.fuPool.FUList5.opList19]
422type=OpDesc
423issueLat=1
424opClass=SimdFloatSqrt
425opLat=1
426
427[system.cpu0.fuPool.FUList6]
428type=FUDesc
429children=opList
430count=0
431opList=system.cpu0.fuPool.FUList6.opList
432
433[system.cpu0.fuPool.FUList6.opList]
434type=OpDesc
435issueLat=1
436opClass=MemWrite
437opLat=1
438
439[system.cpu0.fuPool.FUList7]
440type=FUDesc
441children=opList0 opList1
442count=4
443opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
444
445[system.cpu0.fuPool.FUList7.opList0]
446type=OpDesc
447issueLat=1
448opClass=MemRead
449opLat=1
450
451[system.cpu0.fuPool.FUList7.opList1]
452type=OpDesc
453issueLat=1
454opClass=MemWrite
455opLat=1
456
457[system.cpu0.fuPool.FUList8]
458type=FUDesc
459children=opList
460count=1
461opList=system.cpu0.fuPool.FUList8.opList
462
463[system.cpu0.fuPool.FUList8.opList]
464type=OpDesc
465issueLat=3
466opClass=IprAccess
467opLat=3
468
469[system.cpu0.icache]
470type=BaseCache
471addr_ranges=0:18446744073709551615
472assoc=1
473block_size=64
| 203num_squash_per_cycle=2
204sys=system
205port=system.toL2Bus.slave[3]
206
207[system.cpu0.fuPool]
208type=FUPool
209children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
210FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
211
212[system.cpu0.fuPool.FUList0]
213type=FUDesc
214children=opList
215count=6
216opList=system.cpu0.fuPool.FUList0.opList
217
218[system.cpu0.fuPool.FUList0.opList]
219type=OpDesc
220issueLat=1
221opClass=IntAlu
222opLat=1
223
224[system.cpu0.fuPool.FUList1]
225type=FUDesc
226children=opList0 opList1
227count=2
228opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
229
230[system.cpu0.fuPool.FUList1.opList0]
231type=OpDesc
232issueLat=1
233opClass=IntMult
234opLat=3
235
236[system.cpu0.fuPool.FUList1.opList1]
237type=OpDesc
238issueLat=19
239opClass=IntDiv
240opLat=20
241
242[system.cpu0.fuPool.FUList2]
243type=FUDesc
244children=opList0 opList1 opList2
245count=4
246opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
247
248[system.cpu0.fuPool.FUList2.opList0]
249type=OpDesc
250issueLat=1
251opClass=FloatAdd
252opLat=2
253
254[system.cpu0.fuPool.FUList2.opList1]
255type=OpDesc
256issueLat=1
257opClass=FloatCmp
258opLat=2
259
260[system.cpu0.fuPool.FUList2.opList2]
261type=OpDesc
262issueLat=1
263opClass=FloatCvt
264opLat=2
265
266[system.cpu0.fuPool.FUList3]
267type=FUDesc
268children=opList0 opList1 opList2
269count=2
270opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
271
272[system.cpu0.fuPool.FUList3.opList0]
273type=OpDesc
274issueLat=1
275opClass=FloatMult
276opLat=4
277
278[system.cpu0.fuPool.FUList3.opList1]
279type=OpDesc
280issueLat=12
281opClass=FloatDiv
282opLat=12
283
284[system.cpu0.fuPool.FUList3.opList2]
285type=OpDesc
286issueLat=24
287opClass=FloatSqrt
288opLat=24
289
290[system.cpu0.fuPool.FUList4]
291type=FUDesc
292children=opList
293count=0
294opList=system.cpu0.fuPool.FUList4.opList
295
296[system.cpu0.fuPool.FUList4.opList]
297type=OpDesc
298issueLat=1
299opClass=MemRead
300opLat=1
301
302[system.cpu0.fuPool.FUList5]
303type=FUDesc
304children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
305count=4
306opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
307
308[system.cpu0.fuPool.FUList5.opList00]
309type=OpDesc
310issueLat=1
311opClass=SimdAdd
312opLat=1
313
314[system.cpu0.fuPool.FUList5.opList01]
315type=OpDesc
316issueLat=1
317opClass=SimdAddAcc
318opLat=1
319
320[system.cpu0.fuPool.FUList5.opList02]
321type=OpDesc
322issueLat=1
323opClass=SimdAlu
324opLat=1
325
326[system.cpu0.fuPool.FUList5.opList03]
327type=OpDesc
328issueLat=1
329opClass=SimdCmp
330opLat=1
331
332[system.cpu0.fuPool.FUList5.opList04]
333type=OpDesc
334issueLat=1
335opClass=SimdCvt
336opLat=1
337
338[system.cpu0.fuPool.FUList5.opList05]
339type=OpDesc
340issueLat=1
341opClass=SimdMisc
342opLat=1
343
344[system.cpu0.fuPool.FUList5.opList06]
345type=OpDesc
346issueLat=1
347opClass=SimdMult
348opLat=1
349
350[system.cpu0.fuPool.FUList5.opList07]
351type=OpDesc
352issueLat=1
353opClass=SimdMultAcc
354opLat=1
355
356[system.cpu0.fuPool.FUList5.opList08]
357type=OpDesc
358issueLat=1
359opClass=SimdShift
360opLat=1
361
362[system.cpu0.fuPool.FUList5.opList09]
363type=OpDesc
364issueLat=1
365opClass=SimdShiftAcc
366opLat=1
367
368[system.cpu0.fuPool.FUList5.opList10]
369type=OpDesc
370issueLat=1
371opClass=SimdSqrt
372opLat=1
373
374[system.cpu0.fuPool.FUList5.opList11]
375type=OpDesc
376issueLat=1
377opClass=SimdFloatAdd
378opLat=1
379
380[system.cpu0.fuPool.FUList5.opList12]
381type=OpDesc
382issueLat=1
383opClass=SimdFloatAlu
384opLat=1
385
386[system.cpu0.fuPool.FUList5.opList13]
387type=OpDesc
388issueLat=1
389opClass=SimdFloatCmp
390opLat=1
391
392[system.cpu0.fuPool.FUList5.opList14]
393type=OpDesc
394issueLat=1
395opClass=SimdFloatCvt
396opLat=1
397
398[system.cpu0.fuPool.FUList5.opList15]
399type=OpDesc
400issueLat=1
401opClass=SimdFloatDiv
402opLat=1
403
404[system.cpu0.fuPool.FUList5.opList16]
405type=OpDesc
406issueLat=1
407opClass=SimdFloatMisc
408opLat=1
409
410[system.cpu0.fuPool.FUList5.opList17]
411type=OpDesc
412issueLat=1
413opClass=SimdFloatMult
414opLat=1
415
416[system.cpu0.fuPool.FUList5.opList18]
417type=OpDesc
418issueLat=1
419opClass=SimdFloatMultAcc
420opLat=1
421
422[system.cpu0.fuPool.FUList5.opList19]
423type=OpDesc
424issueLat=1
425opClass=SimdFloatSqrt
426opLat=1
427
428[system.cpu0.fuPool.FUList6]
429type=FUDesc
430children=opList
431count=0
432opList=system.cpu0.fuPool.FUList6.opList
433
434[system.cpu0.fuPool.FUList6.opList]
435type=OpDesc
436issueLat=1
437opClass=MemWrite
438opLat=1
439
440[system.cpu0.fuPool.FUList7]
441type=FUDesc
442children=opList0 opList1
443count=4
444opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
445
446[system.cpu0.fuPool.FUList7.opList0]
447type=OpDesc
448issueLat=1
449opClass=MemRead
450opLat=1
451
452[system.cpu0.fuPool.FUList7.opList1]
453type=OpDesc
454issueLat=1
455opClass=MemWrite
456opLat=1
457
458[system.cpu0.fuPool.FUList8]
459type=FUDesc
460children=opList
461count=1
462opList=system.cpu0.fuPool.FUList8.opList
463
464[system.cpu0.fuPool.FUList8.opList]
465type=OpDesc
466issueLat=3
467opClass=IprAccess
468opLat=3
469
470[system.cpu0.icache]
471type=BaseCache
472addr_ranges=0:18446744073709551615
473assoc=1
474block_size=64
|
474clock=1
| 475clock=500
|
475forward_snoops=true
476hash_delay=1
| 476forward_snoops=true
477hash_delay=1
|
477hit_latency=1000
| 478hit_latency=2
|
478is_top_level=true
479max_miss_count=0
480mshrs=4
481prefetch_on_access=false
482prefetcher=Null
483prioritizeRequests=false
484repl=Null
| 479is_top_level=true
480max_miss_count=0
481mshrs=4
482prefetch_on_access=false
483prefetcher=Null
484prioritizeRequests=false
485repl=Null
|
485response_latency=1000
| 486response_latency=2
|
486size=32768
487subblock_size=0
488system=system
489tgts_per_mshr=20
490trace_addr=0
491two_queue=false
492write_buffers=8
493cpu_side=system.cpu0.icache_port
494mem_side=system.toL2Bus.slave[0]
495
496[system.cpu0.interrupts]
497type=ArmInterrupts
498
| 487size=32768
488subblock_size=0
489system=system
490tgts_per_mshr=20
491trace_addr=0
492two_queue=false
493write_buffers=8
494cpu_side=system.cpu0.icache_port
495mem_side=system.toL2Bus.slave[0]
496
497[system.cpu0.interrupts]
498type=ArmInterrupts
499
|
| 500[system.cpu0.isa]
501type=ArmISA
502fpsid=1090793632
503id_isar0=34607377
504id_isar1=34677009
505id_isar2=555950401
506id_isar3=17899825
507id_isar4=268501314
508id_isar5=0
509id_mmfr0=3
510id_mmfr1=0
511id_mmfr2=19070976
512id_mmfr3=4027589137
513id_pfr0=49
514id_pfr1=1
515midr=890224640
516
|
499[system.cpu0.itb]
500type=ArmTLB
501children=walker
502size=64
503walker=system.cpu0.itb.walker
504
505[system.cpu0.itb.walker]
506type=ArmTableWalker
| 517[system.cpu0.itb]
518type=ArmTLB
519children=walker
520size=64
521walker=system.cpu0.itb.walker
522
523[system.cpu0.itb.walker]
524type=ArmTableWalker
|
507clock=1
| 525clock=500
|
508num_squash_per_cycle=2
509sys=system
510port=system.toL2Bus.slave[2]
511
512[system.cpu0.tracer]
513type=ExeTracer
514
515[system.cpu1]
516type=DerivO3CPU
| 526num_squash_per_cycle=2
527sys=system
528port=system.toL2Bus.slave[2]
529
530[system.cpu0.tracer]
531type=ExeTracer
532
533[system.cpu1]
534type=DerivO3CPU
|
517children=dcache dtb fuPool icache interrupts itb tracer
| 535children=dcache dtb fuPool icache interrupts isa itb tracer
|
518BTBEntries=4096
519BTBTagSize=16
520LFSTSize=1024
521LQEntries=32
522LSQCheckLoads=true
523LSQDepCheckShift=4
524RASSize=16
525SQEntries=32
526SSITSize=1024
527activity=0
528backComSize=5
529cachePorts=200
530checker=Null
531choiceCtrBits=2
532choicePredictorSize=8192
533clock=500
534commitToDecodeDelay=1
535commitToFetchDelay=1
536commitToIEWDelay=1
537commitToRenameDelay=1
538commitWidth=8
539cpu_id=1
540decodeToFetchDelay=1
541decodeToRenameDelay=1
542decodeWidth=8
543defer_registration=false
544dispatchWidth=8
545do_checkpoint_insts=true
546do_quiesce=true
547do_statistics_insts=true
548dtb=system.cpu1.dtb
549fetchToDecodeDelay=1
550fetchTrapLatency=1
551fetchWidth=8
552forwardComSize=5
553fuPool=system.cpu1.fuPool
554function_trace=false
555function_trace_start=0
556globalCtrBits=2
557globalHistoryBits=13
558globalPredictorSize=8192
559iewToCommitDelay=1
560iewToDecodeDelay=1
561iewToFetchDelay=1
562iewToRenameDelay=1
563instShiftAmt=2
564interrupts=system.cpu1.interrupts
| 536BTBEntries=4096
537BTBTagSize=16
538LFSTSize=1024
539LQEntries=32
540LSQCheckLoads=true
541LSQDepCheckShift=4
542RASSize=16
543SQEntries=32
544SSITSize=1024
545activity=0
546backComSize=5
547cachePorts=200
548checker=Null
549choiceCtrBits=2
550choicePredictorSize=8192
551clock=500
552commitToDecodeDelay=1
553commitToFetchDelay=1
554commitToIEWDelay=1
555commitToRenameDelay=1
556commitWidth=8
557cpu_id=1
558decodeToFetchDelay=1
559decodeToRenameDelay=1
560decodeWidth=8
561defer_registration=false
562dispatchWidth=8
563do_checkpoint_insts=true
564do_quiesce=true
565do_statistics_insts=true
566dtb=system.cpu1.dtb
567fetchToDecodeDelay=1
568fetchTrapLatency=1
569fetchWidth=8
570forwardComSize=5
571fuPool=system.cpu1.fuPool
572function_trace=false
573function_trace_start=0
574globalCtrBits=2
575globalHistoryBits=13
576globalPredictorSize=8192
577iewToCommitDelay=1
578iewToDecodeDelay=1
579iewToFetchDelay=1
580iewToRenameDelay=1
581instShiftAmt=2
582interrupts=system.cpu1.interrupts
|
| 583isa=system.cpu1.isa
|
565issueToExecuteDelay=1
566issueWidth=8
567itb=system.cpu1.itb
568localCtrBits=2
569localHistoryBits=11
570localHistoryTableSize=2048
571localPredictorSize=2048
572max_insts_all_threads=0
573max_insts_any_thread=0
574max_loads_all_threads=0
575max_loads_any_thread=0
576needsTSO=false
577numIQEntries=64
578numPhysFloatRegs=256
579numPhysIntRegs=256
580numROBEntries=192
581numRobs=1
582numThreads=1
583predType=tournament
584profile=0
585progress_interval=0
586renameToDecodeDelay=1
587renameToFetchDelay=1
588renameToIEWDelay=2
589renameToROBDelay=1
590renameWidth=8
591smtCommitPolicy=RoundRobin
592smtFetchPolicy=SingleThread
593smtIQPolicy=Partitioned
594smtIQThreshold=100
595smtLSQPolicy=Partitioned
596smtLSQThreshold=100
597smtNumFetchingThreads=1
598smtROBPolicy=Partitioned
599smtROBThreshold=100
600squashWidth=8
601store_set_clear_period=250000
602system=system
603tracer=system.cpu1.tracer
604trapLatency=13
605wbDepth=1
606wbWidth=8
607workload=
608dcache_port=system.cpu1.dcache.cpu_side
609icache_port=system.cpu1.icache.cpu_side
610
611[system.cpu1.dcache]
612type=BaseCache
613addr_ranges=0:18446744073709551615
614assoc=4
615block_size=64
| 584issueToExecuteDelay=1
585issueWidth=8
586itb=system.cpu1.itb
587localCtrBits=2
588localHistoryBits=11
589localHistoryTableSize=2048
590localPredictorSize=2048
591max_insts_all_threads=0
592max_insts_any_thread=0
593max_loads_all_threads=0
594max_loads_any_thread=0
595needsTSO=false
596numIQEntries=64
597numPhysFloatRegs=256
598numPhysIntRegs=256
599numROBEntries=192
600numRobs=1
601numThreads=1
602predType=tournament
603profile=0
604progress_interval=0
605renameToDecodeDelay=1
606renameToFetchDelay=1
607renameToIEWDelay=2
608renameToROBDelay=1
609renameWidth=8
610smtCommitPolicy=RoundRobin
611smtFetchPolicy=SingleThread
612smtIQPolicy=Partitioned
613smtIQThreshold=100
614smtLSQPolicy=Partitioned
615smtLSQThreshold=100
616smtNumFetchingThreads=1
617smtROBPolicy=Partitioned
618smtROBThreshold=100
619squashWidth=8
620store_set_clear_period=250000
621system=system
622tracer=system.cpu1.tracer
623trapLatency=13
624wbDepth=1
625wbWidth=8
626workload=
627dcache_port=system.cpu1.dcache.cpu_side
628icache_port=system.cpu1.icache.cpu_side
629
630[system.cpu1.dcache]
631type=BaseCache
632addr_ranges=0:18446744073709551615
633assoc=4
634block_size=64
|
616clock=1
| 635clock=500
|
617forward_snoops=true
618hash_delay=1
| 636forward_snoops=true
637hash_delay=1
|
619hit_latency=1000
| 638hit_latency=2
|
620is_top_level=true
621max_miss_count=0
622mshrs=4
623prefetch_on_access=false
624prefetcher=Null
625prioritizeRequests=false
626repl=Null
| 639is_top_level=true
640max_miss_count=0
641mshrs=4
642prefetch_on_access=false
643prefetcher=Null
644prioritizeRequests=false
645repl=Null
|
627response_latency=1000
| 646response_latency=2
|
628size=32768
629subblock_size=0
630system=system
631tgts_per_mshr=20
632trace_addr=0
633two_queue=false
634write_buffers=8
635cpu_side=system.cpu1.dcache_port
636mem_side=system.toL2Bus.slave[5]
637
638[system.cpu1.dtb]
639type=ArmTLB
640children=walker
641size=64
642walker=system.cpu1.dtb.walker
643
644[system.cpu1.dtb.walker]
645type=ArmTableWalker
| 647size=32768
648subblock_size=0
649system=system
650tgts_per_mshr=20
651trace_addr=0
652two_queue=false
653write_buffers=8
654cpu_side=system.cpu1.dcache_port
655mem_side=system.toL2Bus.slave[5]
656
657[system.cpu1.dtb]
658type=ArmTLB
659children=walker
660size=64
661walker=system.cpu1.dtb.walker
662
663[system.cpu1.dtb.walker]
664type=ArmTableWalker
|
646clock=1
| 665clock=500
|
647num_squash_per_cycle=2
648sys=system
649port=system.toL2Bus.slave[7]
650
651[system.cpu1.fuPool]
652type=FUPool
653children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
654FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8
655
656[system.cpu1.fuPool.FUList0]
657type=FUDesc
658children=opList
659count=6
660opList=system.cpu1.fuPool.FUList0.opList
661
662[system.cpu1.fuPool.FUList0.opList]
663type=OpDesc
664issueLat=1
665opClass=IntAlu
666opLat=1
667
668[system.cpu1.fuPool.FUList1]
669type=FUDesc
670children=opList0 opList1
671count=2
672opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
673
674[system.cpu1.fuPool.FUList1.opList0]
675type=OpDesc
676issueLat=1
677opClass=IntMult
678opLat=3
679
680[system.cpu1.fuPool.FUList1.opList1]
681type=OpDesc
682issueLat=19
683opClass=IntDiv
684opLat=20
685
686[system.cpu1.fuPool.FUList2]
687type=FUDesc
688children=opList0 opList1 opList2
689count=4
690opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2
691
692[system.cpu1.fuPool.FUList2.opList0]
693type=OpDesc
694issueLat=1
695opClass=FloatAdd
696opLat=2
697
698[system.cpu1.fuPool.FUList2.opList1]
699type=OpDesc
700issueLat=1
701opClass=FloatCmp
702opLat=2
703
704[system.cpu1.fuPool.FUList2.opList2]
705type=OpDesc
706issueLat=1
707opClass=FloatCvt
708opLat=2
709
710[system.cpu1.fuPool.FUList3]
711type=FUDesc
712children=opList0 opList1 opList2
713count=2
714opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
715
716[system.cpu1.fuPool.FUList3.opList0]
717type=OpDesc
718issueLat=1
719opClass=FloatMult
720opLat=4
721
722[system.cpu1.fuPool.FUList3.opList1]
723type=OpDesc
724issueLat=12
725opClass=FloatDiv
726opLat=12
727
728[system.cpu1.fuPool.FUList3.opList2]
729type=OpDesc
730issueLat=24
731opClass=FloatSqrt
732opLat=24
733
734[system.cpu1.fuPool.FUList4]
735type=FUDesc
736children=opList
737count=0
738opList=system.cpu1.fuPool.FUList4.opList
739
740[system.cpu1.fuPool.FUList4.opList]
741type=OpDesc
742issueLat=1
743opClass=MemRead
744opLat=1
745
746[system.cpu1.fuPool.FUList5]
747type=FUDesc
748children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
749count=4
750opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
751
752[system.cpu1.fuPool.FUList5.opList00]
753type=OpDesc
754issueLat=1
755opClass=SimdAdd
756opLat=1
757
758[system.cpu1.fuPool.FUList5.opList01]
759type=OpDesc
760issueLat=1
761opClass=SimdAddAcc
762opLat=1
763
764[system.cpu1.fuPool.FUList5.opList02]
765type=OpDesc
766issueLat=1
767opClass=SimdAlu
768opLat=1
769
770[system.cpu1.fuPool.FUList5.opList03]
771type=OpDesc
772issueLat=1
773opClass=SimdCmp
774opLat=1
775
776[system.cpu1.fuPool.FUList5.opList04]
777type=OpDesc
778issueLat=1
779opClass=SimdCvt
780opLat=1
781
782[system.cpu1.fuPool.FUList5.opList05]
783type=OpDesc
784issueLat=1
785opClass=SimdMisc
786opLat=1
787
788[system.cpu1.fuPool.FUList5.opList06]
789type=OpDesc
790issueLat=1
791opClass=SimdMult
792opLat=1
793
794[system.cpu1.fuPool.FUList5.opList07]
795type=OpDesc
796issueLat=1
797opClass=SimdMultAcc
798opLat=1
799
800[system.cpu1.fuPool.FUList5.opList08]
801type=OpDesc
802issueLat=1
803opClass=SimdShift
804opLat=1
805
806[system.cpu1.fuPool.FUList5.opList09]
807type=OpDesc
808issueLat=1
809opClass=SimdShiftAcc
810opLat=1
811
812[system.cpu1.fuPool.FUList5.opList10]
813type=OpDesc
814issueLat=1
815opClass=SimdSqrt
816opLat=1
817
818[system.cpu1.fuPool.FUList5.opList11]
819type=OpDesc
820issueLat=1
821opClass=SimdFloatAdd
822opLat=1
823
824[system.cpu1.fuPool.FUList5.opList12]
825type=OpDesc
826issueLat=1
827opClass=SimdFloatAlu
828opLat=1
829
830[system.cpu1.fuPool.FUList5.opList13]
831type=OpDesc
832issueLat=1
833opClass=SimdFloatCmp
834opLat=1
835
836[system.cpu1.fuPool.FUList5.opList14]
837type=OpDesc
838issueLat=1
839opClass=SimdFloatCvt
840opLat=1
841
842[system.cpu1.fuPool.FUList5.opList15]
843type=OpDesc
844issueLat=1
845opClass=SimdFloatDiv
846opLat=1
847
848[system.cpu1.fuPool.FUList5.opList16]
849type=OpDesc
850issueLat=1
851opClass=SimdFloatMisc
852opLat=1
853
854[system.cpu1.fuPool.FUList5.opList17]
855type=OpDesc
856issueLat=1
857opClass=SimdFloatMult
858opLat=1
859
860[system.cpu1.fuPool.FUList5.opList18]
861type=OpDesc
862issueLat=1
863opClass=SimdFloatMultAcc
864opLat=1
865
866[system.cpu1.fuPool.FUList5.opList19]
867type=OpDesc
868issueLat=1
869opClass=SimdFloatSqrt
870opLat=1
871
872[system.cpu1.fuPool.FUList6]
873type=FUDesc
874children=opList
875count=0
876opList=system.cpu1.fuPool.FUList6.opList
877
878[system.cpu1.fuPool.FUList6.opList]
879type=OpDesc
880issueLat=1
881opClass=MemWrite
882opLat=1
883
884[system.cpu1.fuPool.FUList7]
885type=FUDesc
886children=opList0 opList1
887count=4
888opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
889
890[system.cpu1.fuPool.FUList7.opList0]
891type=OpDesc
892issueLat=1
893opClass=MemRead
894opLat=1
895
896[system.cpu1.fuPool.FUList7.opList1]
897type=OpDesc
898issueLat=1
899opClass=MemWrite
900opLat=1
901
902[system.cpu1.fuPool.FUList8]
903type=FUDesc
904children=opList
905count=1
906opList=system.cpu1.fuPool.FUList8.opList
907
908[system.cpu1.fuPool.FUList8.opList]
909type=OpDesc
910issueLat=3
911opClass=IprAccess
912opLat=3
913
914[system.cpu1.icache]
915type=BaseCache
916addr_ranges=0:18446744073709551615
917assoc=1
918block_size=64
| 666num_squash_per_cycle=2
667sys=system
668port=system.toL2Bus.slave[7]
669
670[system.cpu1.fuPool]
671type=FUPool
672children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
673FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8
674
675[system.cpu1.fuPool.FUList0]
676type=FUDesc
677children=opList
678count=6
679opList=system.cpu1.fuPool.FUList0.opList
680
681[system.cpu1.fuPool.FUList0.opList]
682type=OpDesc
683issueLat=1
684opClass=IntAlu
685opLat=1
686
687[system.cpu1.fuPool.FUList1]
688type=FUDesc
689children=opList0 opList1
690count=2
691opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
692
693[system.cpu1.fuPool.FUList1.opList0]
694type=OpDesc
695issueLat=1
696opClass=IntMult
697opLat=3
698
699[system.cpu1.fuPool.FUList1.opList1]
700type=OpDesc
701issueLat=19
702opClass=IntDiv
703opLat=20
704
705[system.cpu1.fuPool.FUList2]
706type=FUDesc
707children=opList0 opList1 opList2
708count=4
709opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2
710
711[system.cpu1.fuPool.FUList2.opList0]
712type=OpDesc
713issueLat=1
714opClass=FloatAdd
715opLat=2
716
717[system.cpu1.fuPool.FUList2.opList1]
718type=OpDesc
719issueLat=1
720opClass=FloatCmp
721opLat=2
722
723[system.cpu1.fuPool.FUList2.opList2]
724type=OpDesc
725issueLat=1
726opClass=FloatCvt
727opLat=2
728
729[system.cpu1.fuPool.FUList3]
730type=FUDesc
731children=opList0 opList1 opList2
732count=2
733opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
734
735[system.cpu1.fuPool.FUList3.opList0]
736type=OpDesc
737issueLat=1
738opClass=FloatMult
739opLat=4
740
741[system.cpu1.fuPool.FUList3.opList1]
742type=OpDesc
743issueLat=12
744opClass=FloatDiv
745opLat=12
746
747[system.cpu1.fuPool.FUList3.opList2]
748type=OpDesc
749issueLat=24
750opClass=FloatSqrt
751opLat=24
752
753[system.cpu1.fuPool.FUList4]
754type=FUDesc
755children=opList
756count=0
757opList=system.cpu1.fuPool.FUList4.opList
758
759[system.cpu1.fuPool.FUList4.opList]
760type=OpDesc
761issueLat=1
762opClass=MemRead
763opLat=1
764
765[system.cpu1.fuPool.FUList5]
766type=FUDesc
767children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
768count=4
769opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
770
771[system.cpu1.fuPool.FUList5.opList00]
772type=OpDesc
773issueLat=1
774opClass=SimdAdd
775opLat=1
776
777[system.cpu1.fuPool.FUList5.opList01]
778type=OpDesc
779issueLat=1
780opClass=SimdAddAcc
781opLat=1
782
783[system.cpu1.fuPool.FUList5.opList02]
784type=OpDesc
785issueLat=1
786opClass=SimdAlu
787opLat=1
788
789[system.cpu1.fuPool.FUList5.opList03]
790type=OpDesc
791issueLat=1
792opClass=SimdCmp
793opLat=1
794
795[system.cpu1.fuPool.FUList5.opList04]
796type=OpDesc
797issueLat=1
798opClass=SimdCvt
799opLat=1
800
801[system.cpu1.fuPool.FUList5.opList05]
802type=OpDesc
803issueLat=1
804opClass=SimdMisc
805opLat=1
806
807[system.cpu1.fuPool.FUList5.opList06]
808type=OpDesc
809issueLat=1
810opClass=SimdMult
811opLat=1
812
813[system.cpu1.fuPool.FUList5.opList07]
814type=OpDesc
815issueLat=1
816opClass=SimdMultAcc
817opLat=1
818
819[system.cpu1.fuPool.FUList5.opList08]
820type=OpDesc
821issueLat=1
822opClass=SimdShift
823opLat=1
824
825[system.cpu1.fuPool.FUList5.opList09]
826type=OpDesc
827issueLat=1
828opClass=SimdShiftAcc
829opLat=1
830
831[system.cpu1.fuPool.FUList5.opList10]
832type=OpDesc
833issueLat=1
834opClass=SimdSqrt
835opLat=1
836
837[system.cpu1.fuPool.FUList5.opList11]
838type=OpDesc
839issueLat=1
840opClass=SimdFloatAdd
841opLat=1
842
843[system.cpu1.fuPool.FUList5.opList12]
844type=OpDesc
845issueLat=1
846opClass=SimdFloatAlu
847opLat=1
848
849[system.cpu1.fuPool.FUList5.opList13]
850type=OpDesc
851issueLat=1
852opClass=SimdFloatCmp
853opLat=1
854
855[system.cpu1.fuPool.FUList5.opList14]
856type=OpDesc
857issueLat=1
858opClass=SimdFloatCvt
859opLat=1
860
861[system.cpu1.fuPool.FUList5.opList15]
862type=OpDesc
863issueLat=1
864opClass=SimdFloatDiv
865opLat=1
866
867[system.cpu1.fuPool.FUList5.opList16]
868type=OpDesc
869issueLat=1
870opClass=SimdFloatMisc
871opLat=1
872
873[system.cpu1.fuPool.FUList5.opList17]
874type=OpDesc
875issueLat=1
876opClass=SimdFloatMult
877opLat=1
878
879[system.cpu1.fuPool.FUList5.opList18]
880type=OpDesc
881issueLat=1
882opClass=SimdFloatMultAcc
883opLat=1
884
885[system.cpu1.fuPool.FUList5.opList19]
886type=OpDesc
887issueLat=1
888opClass=SimdFloatSqrt
889opLat=1
890
891[system.cpu1.fuPool.FUList6]
892type=FUDesc
893children=opList
894count=0
895opList=system.cpu1.fuPool.FUList6.opList
896
897[system.cpu1.fuPool.FUList6.opList]
898type=OpDesc
899issueLat=1
900opClass=MemWrite
901opLat=1
902
903[system.cpu1.fuPool.FUList7]
904type=FUDesc
905children=opList0 opList1
906count=4
907opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
908
909[system.cpu1.fuPool.FUList7.opList0]
910type=OpDesc
911issueLat=1
912opClass=MemRead
913opLat=1
914
915[system.cpu1.fuPool.FUList7.opList1]
916type=OpDesc
917issueLat=1
918opClass=MemWrite
919opLat=1
920
921[system.cpu1.fuPool.FUList8]
922type=FUDesc
923children=opList
924count=1
925opList=system.cpu1.fuPool.FUList8.opList
926
927[system.cpu1.fuPool.FUList8.opList]
928type=OpDesc
929issueLat=3
930opClass=IprAccess
931opLat=3
932
933[system.cpu1.icache]
934type=BaseCache
935addr_ranges=0:18446744073709551615
936assoc=1
937block_size=64
|
919clock=1
| 938clock=500
|
920forward_snoops=true
921hash_delay=1
| 939forward_snoops=true
940hash_delay=1
|
922hit_latency=1000
| 941hit_latency=2
|
923is_top_level=true
924max_miss_count=0
925mshrs=4
926prefetch_on_access=false
927prefetcher=Null
928prioritizeRequests=false
929repl=Null
| 942is_top_level=true
943max_miss_count=0
944mshrs=4
945prefetch_on_access=false
946prefetcher=Null
947prioritizeRequests=false
948repl=Null
|
930response_latency=1000
| 949response_latency=2
|
931size=32768
932subblock_size=0
933system=system
934tgts_per_mshr=20
935trace_addr=0
936two_queue=false
937write_buffers=8
938cpu_side=system.cpu1.icache_port
939mem_side=system.toL2Bus.slave[4]
940
941[system.cpu1.interrupts]
942type=ArmInterrupts
943
| 950size=32768
951subblock_size=0
952system=system
953tgts_per_mshr=20
954trace_addr=0
955two_queue=false
956write_buffers=8
957cpu_side=system.cpu1.icache_port
958mem_side=system.toL2Bus.slave[4]
959
960[system.cpu1.interrupts]
961type=ArmInterrupts
962
|
| 963[system.cpu1.isa]
964type=ArmISA
965fpsid=1090793632
966id_isar0=34607377
967id_isar1=34677009
968id_isar2=555950401
969id_isar3=17899825
970id_isar4=268501314
971id_isar5=0
972id_mmfr0=3
973id_mmfr1=0
974id_mmfr2=19070976
975id_mmfr3=4027589137
976id_pfr0=49
977id_pfr1=1
978midr=890224640
979
|
944[system.cpu1.itb]
945type=ArmTLB
946children=walker
947size=64
948walker=system.cpu1.itb.walker
949
950[system.cpu1.itb.walker]
951type=ArmTableWalker
| 980[system.cpu1.itb]
981type=ArmTLB
982children=walker
983size=64
984walker=system.cpu1.itb.walker
985
986[system.cpu1.itb.walker]
987type=ArmTableWalker
|
952clock=1
| 988clock=500
|
953num_squash_per_cycle=2
954sys=system
955port=system.toL2Bus.slave[6]
956
957[system.cpu1.tracer]
958type=ExeTracer
959
960[system.intrctrl]
961type=IntrControl
962sys=system
963
964[system.iobus]
965type=NoncoherentBus
966block_size=64
967clock=1000
968header_cycles=1
969use_default_range=false
970width=8
971master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
972slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
973
974[system.iocache]
975type=BaseCache
976addr_ranges=0:268435455
977assoc=8
978block_size=64
| 989num_squash_per_cycle=2
990sys=system
991port=system.toL2Bus.slave[6]
992
993[system.cpu1.tracer]
994type=ExeTracer
995
996[system.intrctrl]
997type=IntrControl
998sys=system
999
1000[system.iobus]
1001type=NoncoherentBus
1002block_size=64
1003clock=1000
1004header_cycles=1
1005use_default_range=false
1006width=8
1007master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
1008slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
1009
1010[system.iocache]
1011type=BaseCache
1012addr_ranges=0:268435455
1013assoc=8
1014block_size=64
|
979clock=1
| 1015clock=1000
|
980forward_snoops=false
981hash_delay=1
| 1016forward_snoops=false
1017hash_delay=1
|
982hit_latency=50000
983is_top_level=false
| 1018hit_latency=50
1019is_top_level=true
|
984max_miss_count=0
985mshrs=20
986prefetch_on_access=false
987prefetcher=Null
988prioritizeRequests=false
989repl=Null
| 1020max_miss_count=0
1021mshrs=20
1022prefetch_on_access=false
1023prefetcher=Null
1024prioritizeRequests=false
1025repl=Null
|
990response_latency=50000
| 1026response_latency=50
|
991size=1024
992subblock_size=0
993system=system
994tgts_per_mshr=12
995trace_addr=0
996two_queue=false
997write_buffers=8
998cpu_side=system.iobus.master[25]
999mem_side=system.membus.slave[1]
1000
1001[system.l2c]
1002type=BaseCache
1003addr_ranges=0:18446744073709551615
1004assoc=8
1005block_size=64
| 1027size=1024
1028subblock_size=0
1029system=system
1030tgts_per_mshr=12
1031trace_addr=0
1032two_queue=false
1033write_buffers=8
1034cpu_side=system.iobus.master[25]
1035mem_side=system.membus.slave[1]
1036
1037[system.l2c]
1038type=BaseCache
1039addr_ranges=0:18446744073709551615
1040assoc=8
1041block_size=64
|
1006clock=1
| 1042clock=500
|
1007forward_snoops=true
1008hash_delay=1
| 1043forward_snoops=true
1044hash_delay=1
|
1009hit_latency=10000
| 1045hit_latency=20
|
1010is_top_level=false
1011max_miss_count=0
| 1046is_top_level=false
1047max_miss_count=0
|
1012mshrs=92
| 1048mshrs=20
|
1013prefetch_on_access=false
1014prefetcher=Null
1015prioritizeRequests=false
1016repl=Null
| 1049prefetch_on_access=false
1050prefetcher=Null
1051prioritizeRequests=false
1052repl=Null
|
1017response_latency=10000
| 1053response_latency=20
|
1018size=4194304
1019subblock_size=0
1020system=system
| 1054size=4194304
1055subblock_size=0
1056system=system
|
1021tgts_per_mshr=16
| 1057tgts_per_mshr=12
|
1022trace_addr=0
1023two_queue=false
1024write_buffers=8
1025cpu_side=system.toL2Bus.master[0]
1026mem_side=system.membus.slave[2]
1027
1028[system.membus]
1029type=CoherentBus
1030children=badaddr_responder
1031block_size=64
1032clock=1000
1033header_cycles=1
1034use_default_range=false
1035width=8
1036default=system.membus.badaddr_responder.pio
1037master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
1038slave=system.system_port system.iocache.mem_side system.l2c.mem_side
1039
1040[system.membus.badaddr_responder]
1041type=IsaFake
| 1058trace_addr=0
1059two_queue=false
1060write_buffers=8
1061cpu_side=system.toL2Bus.master[0]
1062mem_side=system.membus.slave[2]
1063
1064[system.membus]
1065type=CoherentBus
1066children=badaddr_responder
1067block_size=64
1068clock=1000
1069header_cycles=1
1070use_default_range=false
1071width=8
1072default=system.membus.badaddr_responder.pio
1073master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
1074slave=system.system_port system.iocache.mem_side system.l2c.mem_side
1075
1076[system.membus.badaddr_responder]
1077type=IsaFake
|
1042clock=1
| 1078clock=1000
|
1043fake_mem=false
1044pio_addr=0
1045pio_latency=100000
1046pio_size=8
1047ret_bad_addr=true
1048ret_data16=65535
1049ret_data32=4294967295
1050ret_data64=18446744073709551615
1051ret_data8=255
1052system=system
1053update_data=false
1054warn_access=warn
1055pio=system.membus.default
1056
1057[system.physmem]
| 1079fake_mem=false
1080pio_addr=0
1081pio_latency=100000
1082pio_size=8
1083ret_bad_addr=true
1084ret_data16=65535
1085ret_data32=4294967295
1086ret_data64=18446744073709551615
1087ret_data8=255
1088system=system
1089update_data=false
1090warn_access=warn
1091pio=system.membus.default
1092
1093[system.physmem]
|
1058type=SimpleMemory
1059bandwidth=73.000000
1060clock=1
| 1094type=SimpleDRAM
1095addr_mapping=openmap
1096banks_per_rank=8
1097clock=1000
|
1061conf_table_reported=true
1062in_addr_map=true
| 1098conf_table_reported=true
1099in_addr_map=true
|
1063latency=30000
1064latency_var=0
| 1100lines_per_rowbuffer=64
1101mem_sched_policy=fcfs
|
1065null=false
| 1102null=false
|
| 1103page_policy=open
|
1066range=0:134217727
| 1104range=0:134217727
|
| 1105ranks_per_channel=2
1106read_buffer_size=32
1107tBURST=4000
1108tCL=14000
1109tRCD=14000
1110tREFI=7800000
1111tRFC=300000
1112tRP=14000
1113tWTR=1000
1114write_buffer_size=32
1115write_thresh_perc=70
|
1067zero=false
1068port=system.membus.master[2]
1069
1070[system.realview]
1071type=RealView
1072children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
1073intrctrl=system.intrctrl
1074max_mem_size=268435456
1075mem_start_addr=0
1076pci_cfg_base=0
1077system=system
1078
1079[system.realview.a9scu]
1080type=A9SCU
| 1116zero=false
1117port=system.membus.master[2]
1118
1119[system.realview]
1120type=RealView
1121children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
1122intrctrl=system.intrctrl
1123max_mem_size=268435456
1124mem_start_addr=0
1125pci_cfg_base=0
1126system=system
1127
1128[system.realview.a9scu]
1129type=A9SCU
|
1081clock=1
| 1130clock=1000
|
1082pio_addr=520093696
1083pio_latency=100000
1084system=system
1085pio=system.membus.master[5]
1086
1087[system.realview.aaci_fake]
1088type=AmbaFake
1089amba_id=0
| 1131pio_addr=520093696
1132pio_latency=100000
1133system=system
1134pio=system.membus.master[5]
1135
1136[system.realview.aaci_fake]
1137type=AmbaFake
1138amba_id=0
|
1090clock=1
| 1139clock=1000
|
1091ignore_access=false
1092pio_addr=268451840
1093pio_latency=100000
1094system=system
1095pio=system.iobus.master[21]
1096
1097[system.realview.cf_ctrl]
1098type=IdeController
1099BAR0=402653184
1100BAR0LegacyIO=true
1101BAR0Size=16
1102BAR1=402653440
1103BAR1LegacyIO=true
1104BAR1Size=1
1105BAR2=1
1106BAR2LegacyIO=false
1107BAR2Size=8
1108BAR3=1
1109BAR3LegacyIO=false
1110BAR3Size=4
1111BAR4=1
1112BAR4LegacyIO=false
1113BAR4Size=16
1114BAR5=1
1115BAR5LegacyIO=false
1116BAR5Size=0
1117BIST=0
1118CacheLineSize=0
1119CardbusCIS=0
1120ClassCode=1
1121Command=1
1122DeviceID=28945
1123ExpansionROM=0
1124HeaderType=0
1125InterruptLine=31
1126InterruptPin=1
1127LatencyTimer=0
1128MaximumLatency=0
1129MinimumGrant=0
1130ProgIF=133
1131Revision=0
1132Status=640
1133SubClassCode=1
1134SubsystemID=0
1135SubsystemVendorID=0
1136VendorID=32902
| 1140ignore_access=false
1141pio_addr=268451840
1142pio_latency=100000
1143system=system
1144pio=system.iobus.master[21]
1145
1146[system.realview.cf_ctrl]
1147type=IdeController
1148BAR0=402653184
1149BAR0LegacyIO=true
1150BAR0Size=16
1151BAR1=402653440
1152BAR1LegacyIO=true
1153BAR1Size=1
1154BAR2=1
1155BAR2LegacyIO=false
1156BAR2Size=8
1157BAR3=1
1158BAR3LegacyIO=false
1159BAR3Size=4
1160BAR4=1
1161BAR4LegacyIO=false
1162BAR4Size=16
1163BAR5=1
1164BAR5LegacyIO=false
1165BAR5Size=0
1166BIST=0
1167CacheLineSize=0
1168CardbusCIS=0
1169ClassCode=1
1170Command=1
1171DeviceID=28945
1172ExpansionROM=0
1173HeaderType=0
1174InterruptLine=31
1175InterruptPin=1
1176LatencyTimer=0
1177MaximumLatency=0
1178MinimumGrant=0
1179ProgIF=133
1180Revision=0
1181Status=640
1182SubClassCode=1
1183SubsystemID=0
1184SubsystemVendorID=0
1185VendorID=32902
|
1137clock=1
| 1186clock=1000
|
1138config_latency=20000
1139ctrl_offset=2
1140disks=system.cf0
1141io_shift=1
1142pci_bus=2
1143pci_dev=7
1144pci_func=0
1145pio_latency=30000
1146platform=system.realview
1147system=system
1148config=system.iobus.master[8]
1149dma=system.iobus.slave[2]
1150pio=system.iobus.master[7]
1151
1152[system.realview.clcd]
1153type=Pl111
1154amba_id=1315089
1155clock=41667
1156gic=system.realview.gic
1157int_num=55
1158pio_addr=268566528
1159pio_latency=10000
1160system=system
1161vnc=system.vncserver
1162dma=system.iobus.slave[1]
1163pio=system.iobus.master[4]
1164
1165[system.realview.dmac_fake]
1166type=AmbaFake
1167amba_id=0
| 1187config_latency=20000
1188ctrl_offset=2
1189disks=system.cf0
1190io_shift=1
1191pci_bus=2
1192pci_dev=7
1193pci_func=0
1194pio_latency=30000
1195platform=system.realview
1196system=system
1197config=system.iobus.master[8]
1198dma=system.iobus.slave[2]
1199pio=system.iobus.master[7]
1200
1201[system.realview.clcd]
1202type=Pl111
1203amba_id=1315089
1204clock=41667
1205gic=system.realview.gic
1206int_num=55
1207pio_addr=268566528
1208pio_latency=10000
1209system=system
1210vnc=system.vncserver
1211dma=system.iobus.slave[1]
1212pio=system.iobus.master[4]
1213
1214[system.realview.dmac_fake]
1215type=AmbaFake
1216amba_id=0
|
1168clock=1
| 1217clock=1000
|
1169ignore_access=false
1170pio_addr=268632064
1171pio_latency=100000
1172system=system
1173pio=system.iobus.master[9]
1174
1175[system.realview.flash_fake]
1176type=IsaFake
| 1218ignore_access=false
1219pio_addr=268632064
1220pio_latency=100000
1221system=system
1222pio=system.iobus.master[9]
1223
1224[system.realview.flash_fake]
1225type=IsaFake
|
1177clock=1
| 1226clock=1000
|
1178fake_mem=true
1179pio_addr=1073741824
1180pio_latency=100000
1181pio_size=536870912
1182ret_bad_addr=false
1183ret_data16=65535
1184ret_data32=4294967295
1185ret_data64=18446744073709551615
1186ret_data8=255
1187system=system
1188update_data=false
1189warn_access=
1190pio=system.iobus.master[24]
1191
1192[system.realview.gic]
1193type=Gic
| 1227fake_mem=true
1228pio_addr=1073741824
1229pio_latency=100000
1230pio_size=536870912
1231ret_bad_addr=false
1232ret_data16=65535
1233ret_data32=4294967295
1234ret_data64=18446744073709551615
1235ret_data8=255
1236system=system
1237update_data=false
1238warn_access=
1239pio=system.iobus.master[24]
1240
1241[system.realview.gic]
1242type=Gic
|
1194clock=1
| 1243clock=1000
|
1195cpu_addr=520093952
1196cpu_pio_delay=10000
1197dist_addr=520097792
1198dist_pio_delay=10000
1199int_latency=10000
1200it_lines=128
1201platform=system.realview
1202system=system
1203pio=system.membus.master[3]
1204
1205[system.realview.gpio0_fake]
1206type=AmbaFake
1207amba_id=0
| 1244cpu_addr=520093952
1245cpu_pio_delay=10000
1246dist_addr=520097792
1247dist_pio_delay=10000
1248int_latency=10000
1249it_lines=128
1250platform=system.realview
1251system=system
1252pio=system.membus.master[3]
1253
1254[system.realview.gpio0_fake]
1255type=AmbaFake
1256amba_id=0
|
1208clock=1
| 1257clock=1000
|
1209ignore_access=false
1210pio_addr=268513280
1211pio_latency=100000
1212system=system
1213pio=system.iobus.master[16]
1214
1215[system.realview.gpio1_fake]
1216type=AmbaFake
1217amba_id=0
| 1258ignore_access=false
1259pio_addr=268513280
1260pio_latency=100000
1261system=system
1262pio=system.iobus.master[16]
1263
1264[system.realview.gpio1_fake]
1265type=AmbaFake
1266amba_id=0
|
1218clock=1
| 1267clock=1000
|
1219ignore_access=false
1220pio_addr=268517376
1221pio_latency=100000
1222system=system
1223pio=system.iobus.master[17]
1224
1225[system.realview.gpio2_fake]
1226type=AmbaFake
1227amba_id=0
| 1268ignore_access=false
1269pio_addr=268517376
1270pio_latency=100000
1271system=system
1272pio=system.iobus.master[17]
1273
1274[system.realview.gpio2_fake]
1275type=AmbaFake
1276amba_id=0
|
1228clock=1
| 1277clock=1000
|
1229ignore_access=false
1230pio_addr=268521472
1231pio_latency=100000
1232system=system
1233pio=system.iobus.master[18]
1234
1235[system.realview.kmi0]
1236type=Pl050
1237amba_id=1314896
| 1278ignore_access=false
1279pio_addr=268521472
1280pio_latency=100000
1281system=system
1282pio=system.iobus.master[18]
1283
1284[system.realview.kmi0]
1285type=Pl050
1286amba_id=1314896
|
1238clock=1
| 1287clock=1000
|
1239gic=system.realview.gic
1240int_delay=1000000
1241int_num=52
1242is_mouse=false
1243pio_addr=268460032
1244pio_latency=100000
1245system=system
1246vnc=system.vncserver
1247pio=system.iobus.master[5]
1248
1249[system.realview.kmi1]
1250type=Pl050
1251amba_id=1314896
| 1288gic=system.realview.gic
1289int_delay=1000000
1290int_num=52
1291is_mouse=false
1292pio_addr=268460032
1293pio_latency=100000
1294system=system
1295vnc=system.vncserver
1296pio=system.iobus.master[5]
1297
1298[system.realview.kmi1]
1299type=Pl050
1300amba_id=1314896
|
1252clock=1
| 1301clock=1000
|
1253gic=system.realview.gic
1254int_delay=1000000
1255int_num=53
1256is_mouse=true
1257pio_addr=268464128
1258pio_latency=100000
1259system=system
1260vnc=system.vncserver
1261pio=system.iobus.master[6]
1262
1263[system.realview.l2x0_fake]
1264type=IsaFake
| 1302gic=system.realview.gic
1303int_delay=1000000
1304int_num=53
1305is_mouse=true
1306pio_addr=268464128
1307pio_latency=100000
1308system=system
1309vnc=system.vncserver
1310pio=system.iobus.master[6]
1311
1312[system.realview.l2x0_fake]
1313type=IsaFake
|
1265clock=1
| 1314clock=1000
|
1266fake_mem=false
1267pio_addr=520101888
1268pio_latency=100000
1269pio_size=4095
1270ret_bad_addr=false
1271ret_data16=65535
1272ret_data32=4294967295
1273ret_data64=18446744073709551615
1274ret_data8=255
1275system=system
1276update_data=false
1277warn_access=
1278pio=system.membus.master[4]
1279
1280[system.realview.local_cpu_timer]
1281type=CpuLocalTimer
1282clock=1000
1283gic=system.realview.gic
1284int_num_timer=29
1285int_num_watchdog=30
1286pio_addr=520095232
1287pio_latency=100000
1288system=system
1289pio=system.membus.master[6]
1290
1291[system.realview.mmc_fake]
1292type=AmbaFake
1293amba_id=0
| 1315fake_mem=false
1316pio_addr=520101888
1317pio_latency=100000
1318pio_size=4095
1319ret_bad_addr=false
1320ret_data16=65535
1321ret_data32=4294967295
1322ret_data64=18446744073709551615
1323ret_data8=255
1324system=system
1325update_data=false
1326warn_access=
1327pio=system.membus.master[4]
1328
1329[system.realview.local_cpu_timer]
1330type=CpuLocalTimer
1331clock=1000
1332gic=system.realview.gic
1333int_num_timer=29
1334int_num_watchdog=30
1335pio_addr=520095232
1336pio_latency=100000
1337system=system
1338pio=system.membus.master[6]
1339
1340[system.realview.mmc_fake]
1341type=AmbaFake
1342amba_id=0
|
1294clock=1
| 1343clock=1000
|
1295ignore_access=false
1296pio_addr=268455936
1297pio_latency=100000
1298system=system
1299pio=system.iobus.master[22]
1300
1301[system.realview.nvmem]
1302type=SimpleMemory
1303bandwidth=73.000000
| 1344ignore_access=false
1345pio_addr=268455936
1346pio_latency=100000
1347system=system
1348pio=system.iobus.master[22]
1349
1350[system.realview.nvmem]
1351type=SimpleMemory
1352bandwidth=73.000000
|
1304clock=1
| 1353clock=1000
|
1305conf_table_reported=false
1306in_addr_map=true
1307latency=30000
1308latency_var=0
1309null=false
1310range=2147483648:2214592511
1311zero=true
1312port=system.membus.master[1]
1313
1314[system.realview.realview_io]
1315type=RealViewCtrl
| 1354conf_table_reported=false
1355in_addr_map=true
1356latency=30000
1357latency_var=0
1358null=false
1359range=2147483648:2214592511
1360zero=true
1361port=system.membus.master[1]
1362
1363[system.realview.realview_io]
1364type=RealViewCtrl
|
1316clock=1
| 1365clock=1000
|
1317idreg=0
1318pio_addr=268435456
1319pio_latency=100000
1320proc_id0=201326592
1321proc_id1=201327138
1322system=system
1323pio=system.iobus.master[1]
1324
1325[system.realview.rtc]
1326type=PL031
1327amba_id=3412017
| 1366idreg=0
1367pio_addr=268435456
1368pio_latency=100000
1369proc_id0=201326592
1370proc_id1=201327138
1371system=system
1372pio=system.iobus.master[1]
1373
1374[system.realview.rtc]
1375type=PL031
1376amba_id=3412017
|
1328clock=1
| 1377clock=1000
|
1329gic=system.realview.gic
1330int_delay=100000
1331int_num=42
1332pio_addr=268529664
1333pio_latency=100000
1334system=system
1335time=Thu Jan 1 00:00:00 2009
1336pio=system.iobus.master[23]
1337
1338[system.realview.sci_fake]
1339type=AmbaFake
1340amba_id=0
| 1378gic=system.realview.gic
1379int_delay=100000
1380int_num=42
1381pio_addr=268529664
1382pio_latency=100000
1383system=system
1384time=Thu Jan 1 00:00:00 2009
1385pio=system.iobus.master[23]
1386
1387[system.realview.sci_fake]
1388type=AmbaFake
1389amba_id=0
|
1341clock=1
| 1390clock=1000
|
1342ignore_access=false
1343pio_addr=268492800
1344pio_latency=100000
1345system=system
1346pio=system.iobus.master[20]
1347
1348[system.realview.smc_fake]
1349type=AmbaFake
1350amba_id=0
| 1391ignore_access=false
1392pio_addr=268492800
1393pio_latency=100000
1394system=system
1395pio=system.iobus.master[20]
1396
1397[system.realview.smc_fake]
1398type=AmbaFake
1399amba_id=0
|
1351clock=1
| 1400clock=1000
|
1352ignore_access=false
1353pio_addr=269357056
1354pio_latency=100000
1355system=system
1356pio=system.iobus.master[13]
1357
1358[system.realview.sp810_fake]
1359type=AmbaFake
1360amba_id=0
| 1401ignore_access=false
1402pio_addr=269357056
1403pio_latency=100000
1404system=system
1405pio=system.iobus.master[13]
1406
1407[system.realview.sp810_fake]
1408type=AmbaFake
1409amba_id=0
|
1361clock=1
| 1410clock=1000
|
1362ignore_access=true
1363pio_addr=268439552
1364pio_latency=100000
1365system=system
1366pio=system.iobus.master[14]
1367
1368[system.realview.ssp_fake]
1369type=AmbaFake
1370amba_id=0
| 1411ignore_access=true
1412pio_addr=268439552
1413pio_latency=100000
1414system=system
1415pio=system.iobus.master[14]
1416
1417[system.realview.ssp_fake]
1418type=AmbaFake
1419amba_id=0
|
1371clock=1
| 1420clock=1000
|
1372ignore_access=false
1373pio_addr=268488704
1374pio_latency=100000
1375system=system
1376pio=system.iobus.master[19]
1377
1378[system.realview.timer0]
1379type=Sp804
1380amba_id=1316868
| 1421ignore_access=false
1422pio_addr=268488704
1423pio_latency=100000
1424system=system
1425pio=system.iobus.master[19]
1426
1427[system.realview.timer0]
1428type=Sp804
1429amba_id=1316868
|
1381clock=1
| 1430clock=1000
|
1382clock0=1000000
1383clock1=1000000
1384gic=system.realview.gic
1385int_num0=36
1386int_num1=36
1387pio_addr=268505088
1388pio_latency=100000
1389system=system
1390pio=system.iobus.master[2]
1391
1392[system.realview.timer1]
1393type=Sp804
1394amba_id=1316868
| 1431clock0=1000000
1432clock1=1000000
1433gic=system.realview.gic
1434int_num0=36
1435int_num1=36
1436pio_addr=268505088
1437pio_latency=100000
1438system=system
1439pio=system.iobus.master[2]
1440
1441[system.realview.timer1]
1442type=Sp804
1443amba_id=1316868
|
1395clock=1
| 1444clock=1000
|
1396clock0=1000000
1397clock1=1000000
1398gic=system.realview.gic
1399int_num0=37
1400int_num1=37
1401pio_addr=268509184
1402pio_latency=100000
1403system=system
1404pio=system.iobus.master[3]
1405
1406[system.realview.uart]
1407type=Pl011
| 1445clock0=1000000
1446clock1=1000000
1447gic=system.realview.gic
1448int_num0=37
1449int_num1=37
1450pio_addr=268509184
1451pio_latency=100000
1452system=system
1453pio=system.iobus.master[3]
1454
1455[system.realview.uart]
1456type=Pl011
|
1408clock=1
| 1457clock=1000
|
1409end_on_eot=false
1410gic=system.realview.gic
1411int_delay=100000
1412int_num=44
1413pio_addr=268472320
1414pio_latency=100000
1415platform=system.realview
1416system=system
1417terminal=system.terminal
1418pio=system.iobus.master[0]
1419
1420[system.realview.uart1_fake]
1421type=AmbaFake
1422amba_id=0
| 1458end_on_eot=false
1459gic=system.realview.gic
1460int_delay=100000
1461int_num=44
1462pio_addr=268472320
1463pio_latency=100000
1464platform=system.realview
1465system=system
1466terminal=system.terminal
1467pio=system.iobus.master[0]
1468
1469[system.realview.uart1_fake]
1470type=AmbaFake
1471amba_id=0
|
1423clock=1
| 1472clock=1000
|
1424ignore_access=false
1425pio_addr=268476416
1426pio_latency=100000
1427system=system
1428pio=system.iobus.master[10]
1429
1430[system.realview.uart2_fake]
1431type=AmbaFake
1432amba_id=0
| 1473ignore_access=false
1474pio_addr=268476416
1475pio_latency=100000
1476system=system
1477pio=system.iobus.master[10]
1478
1479[system.realview.uart2_fake]
1480type=AmbaFake
1481amba_id=0
|
1433clock=1
| 1482clock=1000
|
1434ignore_access=false
1435pio_addr=268480512
1436pio_latency=100000
1437system=system
1438pio=system.iobus.master[11]
1439
1440[system.realview.uart3_fake]
1441type=AmbaFake
1442amba_id=0
| 1483ignore_access=false
1484pio_addr=268480512
1485pio_latency=100000
1486system=system
1487pio=system.iobus.master[11]
1488
1489[system.realview.uart3_fake]
1490type=AmbaFake
1491amba_id=0
|
1443clock=1
| 1492clock=1000
|
1444ignore_access=false
1445pio_addr=268484608
1446pio_latency=100000
1447system=system
1448pio=system.iobus.master[12]
1449
1450[system.realview.watchdog_fake]
1451type=AmbaFake
1452amba_id=0
| 1493ignore_access=false
1494pio_addr=268484608
1495pio_latency=100000
1496system=system
1497pio=system.iobus.master[12]
1498
1499[system.realview.watchdog_fake]
1500type=AmbaFake
1501amba_id=0
|
1453clock=1
| 1502clock=1000
|
1454ignore_access=false
1455pio_addr=268500992
1456pio_latency=100000
1457system=system
1458pio=system.iobus.master[15]
1459
1460[system.terminal]
1461type=Terminal
1462intr_control=system.intrctrl
1463number=0
1464output=true
1465port=3456
1466
1467[system.toL2Bus]
1468type=CoherentBus
1469block_size=64
| 1503ignore_access=false
1504pio_addr=268500992
1505pio_latency=100000
1506system=system
1507pio=system.iobus.master[15]
1508
1509[system.terminal]
1510type=Terminal
1511intr_control=system.intrctrl
1512number=0
1513output=true
1514port=3456
1515
1516[system.toL2Bus]
1517type=CoherentBus
1518block_size=64
|
1470clock=1000
| 1519clock=500
|
1471header_cycles=1
1472use_default_range=false
1473width=8
1474master=system.l2c.cpu_side
1475slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
1476
1477[system.vncserver]
1478type=VncServer
1479frame_capture=false
1480number=0
1481port=5900
1482
| 1520header_cycles=1
1521use_default_range=false
1522width=8
1523master=system.l2c.cpu_side
1524slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
1525
1526[system.vncserver]
1527type=VncServer
1528frame_capture=false
1529number=0
1530port=5900
1531
|