1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxArmSystem 13children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxArmSystem 13children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
|
14atags_addr=256 15boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm 16boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
| 14atags_addr=134217728 15boot_loader=/dist/binaries/boot_emm.arm 16boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
17boot_release_addr=65528 18cache_line_size=64 19clk_domain=system.clk_domain
| 17boot_release_addr=65528 18cache_line_size=64 19clk_domain=system.clk_domain
|
20dtb_filename=
| 20dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
|
21early_kernel_symbols=false 22enable_context_switch_stats_dump=false 23eventq_index=0
| 21early_kernel_symbols=false 22enable_context_switch_stats_dump=false 23eventq_index=0
|
24flags_addr=268435504 25gic_cpu_addr=520093952
| 24flags_addr=469827632 25gic_cpu_addr=738205696
|
26have_generic_timer=false 27have_large_asid_64=false 28have_lpae=false 29have_security=false 30have_virtualization=false 31highest_el_is_64=false 32init_param=0
| 26have_generic_timer=false 27have_large_asid_64=false 28have_lpae=false 29have_security=false 30have_virtualization=false 31highest_el_is_64=false 32init_param=0
|
33kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
| 33kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
34kernel_addr_check=true 35load_addr_mask=268435455
| 34kernel_addr_check=true 35load_addr_mask=268435455
|
36load_offset=0 37machine_type=RealView_PBX
| 36load_offset=2147483648 37machine_type=VExpress_EMM
|
38mem_mode=timing
| 38mem_mode=timing
|
39mem_ranges=0:134217727 40memories=system.physmem system.realview.nvmem
| 39mem_ranges=2147483648:2415919103 40memories=system.realview.nvmem system.physmem system.realview.vram
|
41multi_proc=true 42num_work_ids=16 43panic_on_oops=true 44panic_on_panic=true 45phys_addr_range_64=40
| 41multi_proc=true 42num_work_ids=16 43panic_on_oops=true 44panic_on_panic=true 45phys_addr_range_64=40
|
46readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
| 46readfile=/work/gem5.latest/tests/halt.sh
|
47reset_addr_64=0 48symbolfile= 49work_begin_ckpt_count=0 50work_begin_cpu_id_exit=-1 51work_begin_exit_count=0 52work_cpus_ckpt_count=0 53work_end_ckpt_count=0 54work_end_exit_count=0 55work_item_id=-1
| 47reset_addr_64=0 48symbolfile= 49work_begin_ckpt_count=0 50work_begin_cpu_id_exit=-1 51work_begin_exit_count=0 52work_cpus_ckpt_count=0 53work_end_ckpt_count=0 54work_end_exit_count=0 55work_item_id=-1
|
56system_port=system.membus.slave[0]
| 56system_port=system.membus.slave[1]
|
57 58[system.bridge] 59type=Bridge 60clk_domain=system.clk_domain 61delay=50000 62eventq_index=0
| 57 58[system.bridge] 59type=Bridge 60clk_domain=system.clk_domain 61delay=50000 62eventq_index=0
|
63ranges=268435456:520093695 1073741824:1610612735
| 63ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
|
64req_size=16 65resp_size=16 66master=system.iobus.slave[0] 67slave=system.membus.master[0] 68 69[system.cf0] 70type=IdeDisk 71children=image 72delay=1000000 73driveID=master 74eventq_index=0 75image=system.cf0.image 76 77[system.cf0.image] 78type=CowDiskImage 79children=child 80child=system.cf0.image.child 81eventq_index=0 82image_file= 83read_only=false 84table_size=65536 85 86[system.cf0.image.child] 87type=RawDiskImage 88eventq_index=0
| 64req_size=16 65resp_size=16 66master=system.iobus.slave[0] 67slave=system.membus.master[0] 68 69[system.cf0] 70type=IdeDisk 71children=image 72delay=1000000 73driveID=master 74eventq_index=0 75image=system.cf0.image 76 77[system.cf0.image] 78type=CowDiskImage 79children=child 80child=system.cf0.image.child 81eventq_index=0 82image_file= 83read_only=false 84table_size=65536 85 86[system.cf0.image.child] 87type=RawDiskImage 88eventq_index=0
|
89image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
| 89image_file=/dist/disks/linux-aarch32-ael.img
|
90read_only=true 91 92[system.clk_domain] 93type=SrcClockDomain 94clock=1000 95domain_id=-1 96eventq_index=0 97init_perf_level=0 98voltage_domain=system.voltage_domain 99 100[system.cpu0] 101type=DerivO3CPU 102children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer 103LFSTSize=1024 104LQEntries=16 105LSQCheckLoads=true 106LSQDepCheckShift=0 107SQEntries=16 108SSITSize=1024 109activity=0 110backComSize=5 111branchPred=system.cpu0.branchPred 112cachePorts=200 113checker=Null 114clk_domain=system.cpu_clk_domain 115commitToDecodeDelay=1 116commitToFetchDelay=1 117commitToIEWDelay=1 118commitToRenameDelay=1 119commitWidth=8 120cpu_id=0 121decodeToFetchDelay=1 122decodeToRenameDelay=2 123decodeWidth=3 124dispatchWidth=6 125do_checkpoint_insts=true 126do_quiesce=true 127do_statistics_insts=true 128dstage2_mmu=system.cpu0.dstage2_mmu 129dtb=system.cpu0.dtb 130eventq_index=0 131fetchBufferSize=16 132fetchQueueSize=32 133fetchToDecodeDelay=3 134fetchTrapLatency=1 135fetchWidth=3 136forwardComSize=5 137fuPool=system.cpu0.fuPool 138function_trace=false 139function_trace_start=0 140iewToCommitDelay=1 141iewToDecodeDelay=1 142iewToFetchDelay=1 143iewToRenameDelay=1 144interrupts=system.cpu0.interrupts 145isa=system.cpu0.isa 146issueToExecuteDelay=1 147issueWidth=8 148istage2_mmu=system.cpu0.istage2_mmu 149itb=system.cpu0.itb 150max_insts_all_threads=0 151max_insts_any_thread=0 152max_loads_all_threads=0 153max_loads_any_thread=0 154needsTSO=false 155numIQEntries=32 156numPhysCCRegs=640 157numPhysFloatRegs=192 158numPhysIntRegs=128 159numROBEntries=40 160numRobs=1 161numThreads=1 162profile=0 163progress_interval=0 164renameToDecodeDelay=1 165renameToFetchDelay=1 166renameToIEWDelay=1 167renameToROBDelay=1 168renameWidth=3 169simpoint_start_insts= 170smtCommitPolicy=RoundRobin 171smtFetchPolicy=SingleThread 172smtIQPolicy=Partitioned 173smtIQThreshold=100 174smtLSQPolicy=Partitioned 175smtLSQThreshold=100 176smtNumFetchingThreads=1 177smtROBPolicy=Partitioned 178smtROBThreshold=100 179socket_id=0 180squashWidth=8 181store_set_clear_period=250000 182switched_out=false 183system=system 184tracer=system.cpu0.tracer 185trapLatency=13 186wbWidth=8 187workload= 188dcache_port=system.cpu0.dcache.cpu_side 189icache_port=system.cpu0.icache.cpu_side 190 191[system.cpu0.branchPred] 192type=BranchPredictor 193BTBEntries=2048 194BTBTagSize=18 195RASSize=16 196choiceCtrBits=2 197choicePredictorSize=8192 198eventq_index=0 199globalCtrBits=2 200globalPredictorSize=8192 201instShiftAmt=2 202localCtrBits=2 203localHistoryTableSize=2048 204localPredictorSize=2048 205numThreads=1 206predType=bi-mode 207 208[system.cpu0.dcache] 209type=BaseCache 210children=tags 211addr_ranges=0:18446744073709551615 212assoc=2 213clk_domain=system.cpu_clk_domain 214eventq_index=0 215forward_snoops=true 216hit_latency=2 217is_top_level=true 218max_miss_count=0 219mshrs=6 220prefetch_on_access=false 221prefetcher=Null 222response_latency=2 223sequential_access=false 224size=32768 225system=system 226tags=system.cpu0.dcache.tags 227tgts_per_mshr=8 228two_queue=false 229write_buffers=16 230cpu_side=system.cpu0.dcache_port 231mem_side=system.cpu0.toL2Bus.slave[1] 232 233[system.cpu0.dcache.tags] 234type=LRU 235assoc=2 236block_size=64 237clk_domain=system.cpu_clk_domain 238eventq_index=0 239hit_latency=2 240sequential_access=false 241size=32768 242 243[system.cpu0.dstage2_mmu] 244type=ArmStage2MMU 245children=stage2_tlb 246eventq_index=0 247stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb 248tlb=system.cpu0.dtb 249 250[system.cpu0.dstage2_mmu.stage2_tlb] 251type=ArmTLB 252children=walker 253eventq_index=0 254is_stage2=true 255size=32 256walker=system.cpu0.dstage2_mmu.stage2_tlb.walker 257 258[system.cpu0.dstage2_mmu.stage2_tlb.walker] 259type=ArmTableWalker 260clk_domain=system.cpu_clk_domain 261eventq_index=0 262is_stage2=true 263num_squash_per_cycle=2 264sys=system 265port=system.cpu0.toL2Bus.slave[5] 266 267[system.cpu0.dtb] 268type=ArmTLB 269children=walker 270eventq_index=0 271is_stage2=false 272size=64 273walker=system.cpu0.dtb.walker 274 275[system.cpu0.dtb.walker] 276type=ArmTableWalker 277clk_domain=system.cpu_clk_domain 278eventq_index=0 279is_stage2=false 280num_squash_per_cycle=2 281sys=system 282port=system.cpu0.toL2Bus.slave[3] 283 284[system.cpu0.fuPool] 285type=FUPool 286children=FUList0 FUList1 FUList2 FUList3 FUList4 287FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 288eventq_index=0 289 290[system.cpu0.fuPool.FUList0] 291type=FUDesc 292children=opList 293count=2 294eventq_index=0 295opList=system.cpu0.fuPool.FUList0.opList 296 297[system.cpu0.fuPool.FUList0.opList] 298type=OpDesc 299eventq_index=0 300issueLat=1 301opClass=IntAlu 302opLat=1 303 304[system.cpu0.fuPool.FUList1] 305type=FUDesc 306children=opList0 opList1 opList2 307count=1 308eventq_index=0 309opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 system.cpu0.fuPool.FUList1.opList2 310 311[system.cpu0.fuPool.FUList1.opList0] 312type=OpDesc 313eventq_index=0 314issueLat=1 315opClass=IntMult 316opLat=3 317 318[system.cpu0.fuPool.FUList1.opList1] 319type=OpDesc 320eventq_index=0 321issueLat=12 322opClass=IntDiv 323opLat=12 324 325[system.cpu0.fuPool.FUList1.opList2] 326type=OpDesc 327eventq_index=0 328issueLat=1 329opClass=IprAccess 330opLat=3 331 332[system.cpu0.fuPool.FUList2] 333type=FUDesc 334children=opList 335count=1 336eventq_index=0 337opList=system.cpu0.fuPool.FUList2.opList 338 339[system.cpu0.fuPool.FUList2.opList] 340type=OpDesc 341eventq_index=0 342issueLat=1 343opClass=MemRead 344opLat=2 345 346[system.cpu0.fuPool.FUList3] 347type=FUDesc 348children=opList 349count=1 350eventq_index=0 351opList=system.cpu0.fuPool.FUList3.opList 352 353[system.cpu0.fuPool.FUList3.opList] 354type=OpDesc 355eventq_index=0 356issueLat=1 357opClass=MemWrite 358opLat=2 359 360[system.cpu0.fuPool.FUList4] 361type=FUDesc 362children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 363count=2 364eventq_index=0 365opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 system.cpu0.fuPool.FUList4.opList02 system.cpu0.fuPool.FUList4.opList03 system.cpu0.fuPool.FUList4.opList04 system.cpu0.fuPool.FUList4.opList05 system.cpu0.fuPool.FUList4.opList06 system.cpu0.fuPool.FUList4.opList07 system.cpu0.fuPool.FUList4.opList08 system.cpu0.fuPool.FUList4.opList09 system.cpu0.fuPool.FUList4.opList10 system.cpu0.fuPool.FUList4.opList11 system.cpu0.fuPool.FUList4.opList12 system.cpu0.fuPool.FUList4.opList13 system.cpu0.fuPool.FUList4.opList14 system.cpu0.fuPool.FUList4.opList15 system.cpu0.fuPool.FUList4.opList16 system.cpu0.fuPool.FUList4.opList17 system.cpu0.fuPool.FUList4.opList18 system.cpu0.fuPool.FUList4.opList19 system.cpu0.fuPool.FUList4.opList20 system.cpu0.fuPool.FUList4.opList21 system.cpu0.fuPool.FUList4.opList22 system.cpu0.fuPool.FUList4.opList23 system.cpu0.fuPool.FUList4.opList24 system.cpu0.fuPool.FUList4.opList25 366 367[system.cpu0.fuPool.FUList4.opList00] 368type=OpDesc 369eventq_index=0 370issueLat=1 371opClass=SimdAdd 372opLat=4 373 374[system.cpu0.fuPool.FUList4.opList01] 375type=OpDesc 376eventq_index=0 377issueLat=1 378opClass=SimdAddAcc 379opLat=4 380 381[system.cpu0.fuPool.FUList4.opList02] 382type=OpDesc 383eventq_index=0 384issueLat=1 385opClass=SimdAlu 386opLat=4 387 388[system.cpu0.fuPool.FUList4.opList03] 389type=OpDesc 390eventq_index=0 391issueLat=1 392opClass=SimdCmp 393opLat=4 394 395[system.cpu0.fuPool.FUList4.opList04] 396type=OpDesc 397eventq_index=0 398issueLat=1 399opClass=SimdCvt 400opLat=3 401 402[system.cpu0.fuPool.FUList4.opList05] 403type=OpDesc 404eventq_index=0 405issueLat=1 406opClass=SimdMisc 407opLat=3 408 409[system.cpu0.fuPool.FUList4.opList06] 410type=OpDesc 411eventq_index=0 412issueLat=1 413opClass=SimdMult 414opLat=5 415 416[system.cpu0.fuPool.FUList4.opList07] 417type=OpDesc 418eventq_index=0 419issueLat=1 420opClass=SimdMultAcc 421opLat=5 422 423[system.cpu0.fuPool.FUList4.opList08] 424type=OpDesc 425eventq_index=0 426issueLat=1 427opClass=SimdShift 428opLat=3 429 430[system.cpu0.fuPool.FUList4.opList09] 431type=OpDesc 432eventq_index=0 433issueLat=1 434opClass=SimdShiftAcc 435opLat=3 436 437[system.cpu0.fuPool.FUList4.opList10] 438type=OpDesc 439eventq_index=0 440issueLat=1 441opClass=SimdSqrt 442opLat=9 443 444[system.cpu0.fuPool.FUList4.opList11] 445type=OpDesc 446eventq_index=0 447issueLat=1 448opClass=SimdFloatAdd 449opLat=5 450 451[system.cpu0.fuPool.FUList4.opList12] 452type=OpDesc 453eventq_index=0 454issueLat=1 455opClass=SimdFloatAlu 456opLat=5 457 458[system.cpu0.fuPool.FUList4.opList13] 459type=OpDesc 460eventq_index=0 461issueLat=1 462opClass=SimdFloatCmp 463opLat=3 464 465[system.cpu0.fuPool.FUList4.opList14] 466type=OpDesc 467eventq_index=0 468issueLat=1 469opClass=SimdFloatCvt 470opLat=3 471 472[system.cpu0.fuPool.FUList4.opList15] 473type=OpDesc 474eventq_index=0 475issueLat=1 476opClass=SimdFloatDiv 477opLat=3 478 479[system.cpu0.fuPool.FUList4.opList16] 480type=OpDesc 481eventq_index=0 482issueLat=1 483opClass=SimdFloatMisc 484opLat=3 485 486[system.cpu0.fuPool.FUList4.opList17] 487type=OpDesc 488eventq_index=0 489issueLat=1 490opClass=SimdFloatMult 491opLat=3 492 493[system.cpu0.fuPool.FUList4.opList18] 494type=OpDesc 495eventq_index=0 496issueLat=1 497opClass=SimdFloatMultAcc 498opLat=1 499 500[system.cpu0.fuPool.FUList4.opList19] 501type=OpDesc 502eventq_index=0 503issueLat=1 504opClass=SimdFloatSqrt 505opLat=9 506 507[system.cpu0.fuPool.FUList4.opList20] 508type=OpDesc 509eventq_index=0 510issueLat=1 511opClass=FloatAdd 512opLat=5 513 514[system.cpu0.fuPool.FUList4.opList21] 515type=OpDesc 516eventq_index=0 517issueLat=1 518opClass=FloatCmp 519opLat=5 520 521[system.cpu0.fuPool.FUList4.opList22] 522type=OpDesc 523eventq_index=0 524issueLat=1 525opClass=FloatCvt 526opLat=5 527 528[system.cpu0.fuPool.FUList4.opList23] 529type=OpDesc 530eventq_index=0 531issueLat=9 532opClass=FloatDiv 533opLat=9 534 535[system.cpu0.fuPool.FUList4.opList24] 536type=OpDesc 537eventq_index=0 538issueLat=33 539opClass=FloatSqrt 540opLat=33 541 542[system.cpu0.fuPool.FUList4.opList25] 543type=OpDesc 544eventq_index=0 545issueLat=1 546opClass=FloatMult 547opLat=4 548 549[system.cpu0.icache] 550type=BaseCache 551children=tags 552addr_ranges=0:18446744073709551615 553assoc=2 554clk_domain=system.cpu_clk_domain 555eventq_index=0 556forward_snoops=true 557hit_latency=1 558is_top_level=true 559max_miss_count=0 560mshrs=2 561prefetch_on_access=false 562prefetcher=Null 563response_latency=1 564sequential_access=false 565size=32768 566system=system 567tags=system.cpu0.icache.tags 568tgts_per_mshr=8 569two_queue=false 570write_buffers=8 571cpu_side=system.cpu0.icache_port 572mem_side=system.cpu0.toL2Bus.slave[0] 573 574[system.cpu0.icache.tags] 575type=LRU 576assoc=2 577block_size=64 578clk_domain=system.cpu_clk_domain 579eventq_index=0 580hit_latency=1 581sequential_access=false 582size=32768 583 584[system.cpu0.interrupts] 585type=ArmInterrupts 586eventq_index=0 587 588[system.cpu0.isa] 589type=ArmISA 590eventq_index=0 591fpsid=1090793632 592id_aa64afr0_el1=0 593id_aa64afr1_el1=0 594id_aa64dfr0_el1=1052678 595id_aa64dfr1_el1=0 596id_aa64isar0_el1=0 597id_aa64isar1_el1=0 598id_aa64mmfr0_el1=15728642 599id_aa64mmfr1_el1=0 600id_aa64pfr0_el1=17 601id_aa64pfr1_el1=0 602id_isar0=34607377 603id_isar1=34677009 604id_isar2=555950401 605id_isar3=17899825 606id_isar4=268501314 607id_isar5=0 608id_mmfr0=270536963 609id_mmfr1=0 610id_mmfr2=19070976 611id_mmfr3=34611729 612id_pfr0=49 613id_pfr1=4113 614midr=1091551472
| 90read_only=true 91 92[system.clk_domain] 93type=SrcClockDomain 94clock=1000 95domain_id=-1 96eventq_index=0 97init_perf_level=0 98voltage_domain=system.voltage_domain 99 100[system.cpu0] 101type=DerivO3CPU 102children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer 103LFSTSize=1024 104LQEntries=16 105LSQCheckLoads=true 106LSQDepCheckShift=0 107SQEntries=16 108SSITSize=1024 109activity=0 110backComSize=5 111branchPred=system.cpu0.branchPred 112cachePorts=200 113checker=Null 114clk_domain=system.cpu_clk_domain 115commitToDecodeDelay=1 116commitToFetchDelay=1 117commitToIEWDelay=1 118commitToRenameDelay=1 119commitWidth=8 120cpu_id=0 121decodeToFetchDelay=1 122decodeToRenameDelay=2 123decodeWidth=3 124dispatchWidth=6 125do_checkpoint_insts=true 126do_quiesce=true 127do_statistics_insts=true 128dstage2_mmu=system.cpu0.dstage2_mmu 129dtb=system.cpu0.dtb 130eventq_index=0 131fetchBufferSize=16 132fetchQueueSize=32 133fetchToDecodeDelay=3 134fetchTrapLatency=1 135fetchWidth=3 136forwardComSize=5 137fuPool=system.cpu0.fuPool 138function_trace=false 139function_trace_start=0 140iewToCommitDelay=1 141iewToDecodeDelay=1 142iewToFetchDelay=1 143iewToRenameDelay=1 144interrupts=system.cpu0.interrupts 145isa=system.cpu0.isa 146issueToExecuteDelay=1 147issueWidth=8 148istage2_mmu=system.cpu0.istage2_mmu 149itb=system.cpu0.itb 150max_insts_all_threads=0 151max_insts_any_thread=0 152max_loads_all_threads=0 153max_loads_any_thread=0 154needsTSO=false 155numIQEntries=32 156numPhysCCRegs=640 157numPhysFloatRegs=192 158numPhysIntRegs=128 159numROBEntries=40 160numRobs=1 161numThreads=1 162profile=0 163progress_interval=0 164renameToDecodeDelay=1 165renameToFetchDelay=1 166renameToIEWDelay=1 167renameToROBDelay=1 168renameWidth=3 169simpoint_start_insts= 170smtCommitPolicy=RoundRobin 171smtFetchPolicy=SingleThread 172smtIQPolicy=Partitioned 173smtIQThreshold=100 174smtLSQPolicy=Partitioned 175smtLSQThreshold=100 176smtNumFetchingThreads=1 177smtROBPolicy=Partitioned 178smtROBThreshold=100 179socket_id=0 180squashWidth=8 181store_set_clear_period=250000 182switched_out=false 183system=system 184tracer=system.cpu0.tracer 185trapLatency=13 186wbWidth=8 187workload= 188dcache_port=system.cpu0.dcache.cpu_side 189icache_port=system.cpu0.icache.cpu_side 190 191[system.cpu0.branchPred] 192type=BranchPredictor 193BTBEntries=2048 194BTBTagSize=18 195RASSize=16 196choiceCtrBits=2 197choicePredictorSize=8192 198eventq_index=0 199globalCtrBits=2 200globalPredictorSize=8192 201instShiftAmt=2 202localCtrBits=2 203localHistoryTableSize=2048 204localPredictorSize=2048 205numThreads=1 206predType=bi-mode 207 208[system.cpu0.dcache] 209type=BaseCache 210children=tags 211addr_ranges=0:18446744073709551615 212assoc=2 213clk_domain=system.cpu_clk_domain 214eventq_index=0 215forward_snoops=true 216hit_latency=2 217is_top_level=true 218max_miss_count=0 219mshrs=6 220prefetch_on_access=false 221prefetcher=Null 222response_latency=2 223sequential_access=false 224size=32768 225system=system 226tags=system.cpu0.dcache.tags 227tgts_per_mshr=8 228two_queue=false 229write_buffers=16 230cpu_side=system.cpu0.dcache_port 231mem_side=system.cpu0.toL2Bus.slave[1] 232 233[system.cpu0.dcache.tags] 234type=LRU 235assoc=2 236block_size=64 237clk_domain=system.cpu_clk_domain 238eventq_index=0 239hit_latency=2 240sequential_access=false 241size=32768 242 243[system.cpu0.dstage2_mmu] 244type=ArmStage2MMU 245children=stage2_tlb 246eventq_index=0 247stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb 248tlb=system.cpu0.dtb 249 250[system.cpu0.dstage2_mmu.stage2_tlb] 251type=ArmTLB 252children=walker 253eventq_index=0 254is_stage2=true 255size=32 256walker=system.cpu0.dstage2_mmu.stage2_tlb.walker 257 258[system.cpu0.dstage2_mmu.stage2_tlb.walker] 259type=ArmTableWalker 260clk_domain=system.cpu_clk_domain 261eventq_index=0 262is_stage2=true 263num_squash_per_cycle=2 264sys=system 265port=system.cpu0.toL2Bus.slave[5] 266 267[system.cpu0.dtb] 268type=ArmTLB 269children=walker 270eventq_index=0 271is_stage2=false 272size=64 273walker=system.cpu0.dtb.walker 274 275[system.cpu0.dtb.walker] 276type=ArmTableWalker 277clk_domain=system.cpu_clk_domain 278eventq_index=0 279is_stage2=false 280num_squash_per_cycle=2 281sys=system 282port=system.cpu0.toL2Bus.slave[3] 283 284[system.cpu0.fuPool] 285type=FUPool 286children=FUList0 FUList1 FUList2 FUList3 FUList4 287FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 288eventq_index=0 289 290[system.cpu0.fuPool.FUList0] 291type=FUDesc 292children=opList 293count=2 294eventq_index=0 295opList=system.cpu0.fuPool.FUList0.opList 296 297[system.cpu0.fuPool.FUList0.opList] 298type=OpDesc 299eventq_index=0 300issueLat=1 301opClass=IntAlu 302opLat=1 303 304[system.cpu0.fuPool.FUList1] 305type=FUDesc 306children=opList0 opList1 opList2 307count=1 308eventq_index=0 309opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 system.cpu0.fuPool.FUList1.opList2 310 311[system.cpu0.fuPool.FUList1.opList0] 312type=OpDesc 313eventq_index=0 314issueLat=1 315opClass=IntMult 316opLat=3 317 318[system.cpu0.fuPool.FUList1.opList1] 319type=OpDesc 320eventq_index=0 321issueLat=12 322opClass=IntDiv 323opLat=12 324 325[system.cpu0.fuPool.FUList1.opList2] 326type=OpDesc 327eventq_index=0 328issueLat=1 329opClass=IprAccess 330opLat=3 331 332[system.cpu0.fuPool.FUList2] 333type=FUDesc 334children=opList 335count=1 336eventq_index=0 337opList=system.cpu0.fuPool.FUList2.opList 338 339[system.cpu0.fuPool.FUList2.opList] 340type=OpDesc 341eventq_index=0 342issueLat=1 343opClass=MemRead 344opLat=2 345 346[system.cpu0.fuPool.FUList3] 347type=FUDesc 348children=opList 349count=1 350eventq_index=0 351opList=system.cpu0.fuPool.FUList3.opList 352 353[system.cpu0.fuPool.FUList3.opList] 354type=OpDesc 355eventq_index=0 356issueLat=1 357opClass=MemWrite 358opLat=2 359 360[system.cpu0.fuPool.FUList4] 361type=FUDesc 362children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 363count=2 364eventq_index=0 365opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 system.cpu0.fuPool.FUList4.opList02 system.cpu0.fuPool.FUList4.opList03 system.cpu0.fuPool.FUList4.opList04 system.cpu0.fuPool.FUList4.opList05 system.cpu0.fuPool.FUList4.opList06 system.cpu0.fuPool.FUList4.opList07 system.cpu0.fuPool.FUList4.opList08 system.cpu0.fuPool.FUList4.opList09 system.cpu0.fuPool.FUList4.opList10 system.cpu0.fuPool.FUList4.opList11 system.cpu0.fuPool.FUList4.opList12 system.cpu0.fuPool.FUList4.opList13 system.cpu0.fuPool.FUList4.opList14 system.cpu0.fuPool.FUList4.opList15 system.cpu0.fuPool.FUList4.opList16 system.cpu0.fuPool.FUList4.opList17 system.cpu0.fuPool.FUList4.opList18 system.cpu0.fuPool.FUList4.opList19 system.cpu0.fuPool.FUList4.opList20 system.cpu0.fuPool.FUList4.opList21 system.cpu0.fuPool.FUList4.opList22 system.cpu0.fuPool.FUList4.opList23 system.cpu0.fuPool.FUList4.opList24 system.cpu0.fuPool.FUList4.opList25 366 367[system.cpu0.fuPool.FUList4.opList00] 368type=OpDesc 369eventq_index=0 370issueLat=1 371opClass=SimdAdd 372opLat=4 373 374[system.cpu0.fuPool.FUList4.opList01] 375type=OpDesc 376eventq_index=0 377issueLat=1 378opClass=SimdAddAcc 379opLat=4 380 381[system.cpu0.fuPool.FUList4.opList02] 382type=OpDesc 383eventq_index=0 384issueLat=1 385opClass=SimdAlu 386opLat=4 387 388[system.cpu0.fuPool.FUList4.opList03] 389type=OpDesc 390eventq_index=0 391issueLat=1 392opClass=SimdCmp 393opLat=4 394 395[system.cpu0.fuPool.FUList4.opList04] 396type=OpDesc 397eventq_index=0 398issueLat=1 399opClass=SimdCvt 400opLat=3 401 402[system.cpu0.fuPool.FUList4.opList05] 403type=OpDesc 404eventq_index=0 405issueLat=1 406opClass=SimdMisc 407opLat=3 408 409[system.cpu0.fuPool.FUList4.opList06] 410type=OpDesc 411eventq_index=0 412issueLat=1 413opClass=SimdMult 414opLat=5 415 416[system.cpu0.fuPool.FUList4.opList07] 417type=OpDesc 418eventq_index=0 419issueLat=1 420opClass=SimdMultAcc 421opLat=5 422 423[system.cpu0.fuPool.FUList4.opList08] 424type=OpDesc 425eventq_index=0 426issueLat=1 427opClass=SimdShift 428opLat=3 429 430[system.cpu0.fuPool.FUList4.opList09] 431type=OpDesc 432eventq_index=0 433issueLat=1 434opClass=SimdShiftAcc 435opLat=3 436 437[system.cpu0.fuPool.FUList4.opList10] 438type=OpDesc 439eventq_index=0 440issueLat=1 441opClass=SimdSqrt 442opLat=9 443 444[system.cpu0.fuPool.FUList4.opList11] 445type=OpDesc 446eventq_index=0 447issueLat=1 448opClass=SimdFloatAdd 449opLat=5 450 451[system.cpu0.fuPool.FUList4.opList12] 452type=OpDesc 453eventq_index=0 454issueLat=1 455opClass=SimdFloatAlu 456opLat=5 457 458[system.cpu0.fuPool.FUList4.opList13] 459type=OpDesc 460eventq_index=0 461issueLat=1 462opClass=SimdFloatCmp 463opLat=3 464 465[system.cpu0.fuPool.FUList4.opList14] 466type=OpDesc 467eventq_index=0 468issueLat=1 469opClass=SimdFloatCvt 470opLat=3 471 472[system.cpu0.fuPool.FUList4.opList15] 473type=OpDesc 474eventq_index=0 475issueLat=1 476opClass=SimdFloatDiv 477opLat=3 478 479[system.cpu0.fuPool.FUList4.opList16] 480type=OpDesc 481eventq_index=0 482issueLat=1 483opClass=SimdFloatMisc 484opLat=3 485 486[system.cpu0.fuPool.FUList4.opList17] 487type=OpDesc 488eventq_index=0 489issueLat=1 490opClass=SimdFloatMult 491opLat=3 492 493[system.cpu0.fuPool.FUList4.opList18] 494type=OpDesc 495eventq_index=0 496issueLat=1 497opClass=SimdFloatMultAcc 498opLat=1 499 500[system.cpu0.fuPool.FUList4.opList19] 501type=OpDesc 502eventq_index=0 503issueLat=1 504opClass=SimdFloatSqrt 505opLat=9 506 507[system.cpu0.fuPool.FUList4.opList20] 508type=OpDesc 509eventq_index=0 510issueLat=1 511opClass=FloatAdd 512opLat=5 513 514[system.cpu0.fuPool.FUList4.opList21] 515type=OpDesc 516eventq_index=0 517issueLat=1 518opClass=FloatCmp 519opLat=5 520 521[system.cpu0.fuPool.FUList4.opList22] 522type=OpDesc 523eventq_index=0 524issueLat=1 525opClass=FloatCvt 526opLat=5 527 528[system.cpu0.fuPool.FUList4.opList23] 529type=OpDesc 530eventq_index=0 531issueLat=9 532opClass=FloatDiv 533opLat=9 534 535[system.cpu0.fuPool.FUList4.opList24] 536type=OpDesc 537eventq_index=0 538issueLat=33 539opClass=FloatSqrt 540opLat=33 541 542[system.cpu0.fuPool.FUList4.opList25] 543type=OpDesc 544eventq_index=0 545issueLat=1 546opClass=FloatMult 547opLat=4 548 549[system.cpu0.icache] 550type=BaseCache 551children=tags 552addr_ranges=0:18446744073709551615 553assoc=2 554clk_domain=system.cpu_clk_domain 555eventq_index=0 556forward_snoops=true 557hit_latency=1 558is_top_level=true 559max_miss_count=0 560mshrs=2 561prefetch_on_access=false 562prefetcher=Null 563response_latency=1 564sequential_access=false 565size=32768 566system=system 567tags=system.cpu0.icache.tags 568tgts_per_mshr=8 569two_queue=false 570write_buffers=8 571cpu_side=system.cpu0.icache_port 572mem_side=system.cpu0.toL2Bus.slave[0] 573 574[system.cpu0.icache.tags] 575type=LRU 576assoc=2 577block_size=64 578clk_domain=system.cpu_clk_domain 579eventq_index=0 580hit_latency=1 581sequential_access=false 582size=32768 583 584[system.cpu0.interrupts] 585type=ArmInterrupts 586eventq_index=0 587 588[system.cpu0.isa] 589type=ArmISA 590eventq_index=0 591fpsid=1090793632 592id_aa64afr0_el1=0 593id_aa64afr1_el1=0 594id_aa64dfr0_el1=1052678 595id_aa64dfr1_el1=0 596id_aa64isar0_el1=0 597id_aa64isar1_el1=0 598id_aa64mmfr0_el1=15728642 599id_aa64mmfr1_el1=0 600id_aa64pfr0_el1=17 601id_aa64pfr1_el1=0 602id_isar0=34607377 603id_isar1=34677009 604id_isar2=555950401 605id_isar3=17899825 606id_isar4=268501314 607id_isar5=0 608id_mmfr0=270536963 609id_mmfr1=0 610id_mmfr2=19070976 611id_mmfr3=34611729 612id_pfr0=49 613id_pfr1=4113 614midr=1091551472
|
| 615pmu=Null
|
615system=system 616 617[system.cpu0.istage2_mmu] 618type=ArmStage2MMU 619children=stage2_tlb 620eventq_index=0 621stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb 622tlb=system.cpu0.itb 623 624[system.cpu0.istage2_mmu.stage2_tlb] 625type=ArmTLB 626children=walker 627eventq_index=0 628is_stage2=true 629size=32 630walker=system.cpu0.istage2_mmu.stage2_tlb.walker 631 632[system.cpu0.istage2_mmu.stage2_tlb.walker] 633type=ArmTableWalker 634clk_domain=system.cpu_clk_domain 635eventq_index=0 636is_stage2=true 637num_squash_per_cycle=2 638sys=system 639port=system.cpu0.toL2Bus.slave[4] 640 641[system.cpu0.itb] 642type=ArmTLB 643children=walker 644eventq_index=0 645is_stage2=false 646size=64 647walker=system.cpu0.itb.walker 648 649[system.cpu0.itb.walker] 650type=ArmTableWalker 651clk_domain=system.cpu_clk_domain 652eventq_index=0 653is_stage2=false 654num_squash_per_cycle=2 655sys=system 656port=system.cpu0.toL2Bus.slave[2] 657 658[system.cpu0.l2cache] 659type=BaseCache 660children=prefetcher tags 661addr_ranges=0:18446744073709551615 662assoc=16 663clk_domain=system.cpu_clk_domain 664eventq_index=0 665forward_snoops=true 666hit_latency=12 667is_top_level=false 668max_miss_count=0 669mshrs=16 670prefetch_on_access=true 671prefetcher=system.cpu0.l2cache.prefetcher 672response_latency=12 673sequential_access=false 674size=1048576 675system=system 676tags=system.cpu0.l2cache.tags 677tgts_per_mshr=8 678two_queue=false 679write_buffers=8 680cpu_side=system.cpu0.toL2Bus.master[0] 681mem_side=system.toL2Bus.slave[0] 682 683[system.cpu0.l2cache.prefetcher] 684type=StridePrefetcher 685clk_domain=system.cpu_clk_domain 686cross_pages=false 687data_accesses_only=false 688degree=8 689eventq_index=0 690inst_tagged=true 691latency=1 692on_miss_only=false 693on_prefetch=true 694on_read_only=false 695serial_squash=false 696size=100 697sys=system 698use_master_id=true 699 700[system.cpu0.l2cache.tags] 701type=RandomRepl 702assoc=16 703block_size=64 704clk_domain=system.cpu_clk_domain 705eventq_index=0 706hit_latency=12 707sequential_access=false 708size=1048576 709 710[system.cpu0.toL2Bus] 711type=CoherentXBar 712clk_domain=system.cpu_clk_domain 713eventq_index=0 714header_cycles=1 715snoop_filter=Null 716system=system 717use_default_range=false 718width=32 719master=system.cpu0.l2cache.cpu_side 720slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port 721 722[system.cpu0.tracer] 723type=ExeTracer 724eventq_index=0 725 726[system.cpu1] 727type=DerivO3CPU 728children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer 729LFSTSize=1024 730LQEntries=16 731LSQCheckLoads=true 732LSQDepCheckShift=0 733SQEntries=16 734SSITSize=1024 735activity=0 736backComSize=5 737branchPred=system.cpu1.branchPred 738cachePorts=200 739checker=Null 740clk_domain=system.cpu_clk_domain 741commitToDecodeDelay=1 742commitToFetchDelay=1 743commitToIEWDelay=1 744commitToRenameDelay=1 745commitWidth=8 746cpu_id=1 747decodeToFetchDelay=1 748decodeToRenameDelay=2 749decodeWidth=3 750dispatchWidth=6 751do_checkpoint_insts=true 752do_quiesce=true 753do_statistics_insts=true 754dstage2_mmu=system.cpu1.dstage2_mmu 755dtb=system.cpu1.dtb 756eventq_index=0 757fetchBufferSize=16 758fetchQueueSize=32 759fetchToDecodeDelay=3 760fetchTrapLatency=1 761fetchWidth=3 762forwardComSize=5 763fuPool=system.cpu1.fuPool 764function_trace=false 765function_trace_start=0 766iewToCommitDelay=1 767iewToDecodeDelay=1 768iewToFetchDelay=1 769iewToRenameDelay=1 770interrupts=system.cpu1.interrupts 771isa=system.cpu1.isa 772issueToExecuteDelay=1 773issueWidth=8 774istage2_mmu=system.cpu1.istage2_mmu 775itb=system.cpu1.itb 776max_insts_all_threads=0 777max_insts_any_thread=0 778max_loads_all_threads=0 779max_loads_any_thread=0 780needsTSO=false 781numIQEntries=32 782numPhysCCRegs=640 783numPhysFloatRegs=192 784numPhysIntRegs=128 785numROBEntries=40 786numRobs=1 787numThreads=1 788profile=0 789progress_interval=0 790renameToDecodeDelay=1 791renameToFetchDelay=1 792renameToIEWDelay=1 793renameToROBDelay=1 794renameWidth=3 795simpoint_start_insts= 796smtCommitPolicy=RoundRobin 797smtFetchPolicy=SingleThread 798smtIQPolicy=Partitioned 799smtIQThreshold=100 800smtLSQPolicy=Partitioned 801smtLSQThreshold=100 802smtNumFetchingThreads=1 803smtROBPolicy=Partitioned 804smtROBThreshold=100 805socket_id=0 806squashWidth=8 807store_set_clear_period=250000 808switched_out=false 809system=system 810tracer=system.cpu1.tracer 811trapLatency=13 812wbWidth=8 813workload= 814dcache_port=system.cpu1.dcache.cpu_side 815icache_port=system.cpu1.icache.cpu_side 816 817[system.cpu1.branchPred] 818type=BranchPredictor 819BTBEntries=2048 820BTBTagSize=18 821RASSize=16 822choiceCtrBits=2 823choicePredictorSize=8192 824eventq_index=0 825globalCtrBits=2 826globalPredictorSize=8192 827instShiftAmt=2 828localCtrBits=2 829localHistoryTableSize=2048 830localPredictorSize=2048 831numThreads=1 832predType=bi-mode 833 834[system.cpu1.dcache] 835type=BaseCache 836children=tags 837addr_ranges=0:18446744073709551615 838assoc=2 839clk_domain=system.cpu_clk_domain 840eventq_index=0 841forward_snoops=true 842hit_latency=2 843is_top_level=true 844max_miss_count=0 845mshrs=6 846prefetch_on_access=false 847prefetcher=Null 848response_latency=2 849sequential_access=false 850size=32768 851system=system 852tags=system.cpu1.dcache.tags 853tgts_per_mshr=8 854two_queue=false 855write_buffers=16 856cpu_side=system.cpu1.dcache_port 857mem_side=system.cpu1.toL2Bus.slave[1] 858 859[system.cpu1.dcache.tags] 860type=LRU 861assoc=2 862block_size=64 863clk_domain=system.cpu_clk_domain 864eventq_index=0 865hit_latency=2 866sequential_access=false 867size=32768 868 869[system.cpu1.dstage2_mmu] 870type=ArmStage2MMU 871children=stage2_tlb 872eventq_index=0 873stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb 874tlb=system.cpu1.dtb 875 876[system.cpu1.dstage2_mmu.stage2_tlb] 877type=ArmTLB 878children=walker 879eventq_index=0 880is_stage2=true 881size=32 882walker=system.cpu1.dstage2_mmu.stage2_tlb.walker 883 884[system.cpu1.dstage2_mmu.stage2_tlb.walker] 885type=ArmTableWalker 886clk_domain=system.cpu_clk_domain 887eventq_index=0 888is_stage2=true 889num_squash_per_cycle=2 890sys=system 891port=system.cpu1.toL2Bus.slave[5] 892 893[system.cpu1.dtb] 894type=ArmTLB 895children=walker 896eventq_index=0 897is_stage2=false 898size=64 899walker=system.cpu1.dtb.walker 900 901[system.cpu1.dtb.walker] 902type=ArmTableWalker 903clk_domain=system.cpu_clk_domain 904eventq_index=0 905is_stage2=false 906num_squash_per_cycle=2 907sys=system 908port=system.cpu1.toL2Bus.slave[3] 909 910[system.cpu1.fuPool] 911type=FUPool 912children=FUList0 FUList1 FUList2 FUList3 FUList4 913FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 914eventq_index=0 915 916[system.cpu1.fuPool.FUList0] 917type=FUDesc 918children=opList 919count=2 920eventq_index=0 921opList=system.cpu1.fuPool.FUList0.opList 922 923[system.cpu1.fuPool.FUList0.opList] 924type=OpDesc 925eventq_index=0 926issueLat=1 927opClass=IntAlu 928opLat=1 929 930[system.cpu1.fuPool.FUList1] 931type=FUDesc 932children=opList0 opList1 opList2 933count=1 934eventq_index=0 935opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 system.cpu1.fuPool.FUList1.opList2 936 937[system.cpu1.fuPool.FUList1.opList0] 938type=OpDesc 939eventq_index=0 940issueLat=1 941opClass=IntMult 942opLat=3 943 944[system.cpu1.fuPool.FUList1.opList1] 945type=OpDesc 946eventq_index=0 947issueLat=12 948opClass=IntDiv 949opLat=12 950 951[system.cpu1.fuPool.FUList1.opList2] 952type=OpDesc 953eventq_index=0 954issueLat=1 955opClass=IprAccess 956opLat=3 957 958[system.cpu1.fuPool.FUList2] 959type=FUDesc 960children=opList 961count=1 962eventq_index=0 963opList=system.cpu1.fuPool.FUList2.opList 964 965[system.cpu1.fuPool.FUList2.opList] 966type=OpDesc 967eventq_index=0 968issueLat=1 969opClass=MemRead 970opLat=2 971 972[system.cpu1.fuPool.FUList3] 973type=FUDesc 974children=opList 975count=1 976eventq_index=0 977opList=system.cpu1.fuPool.FUList3.opList 978 979[system.cpu1.fuPool.FUList3.opList] 980type=OpDesc 981eventq_index=0 982issueLat=1 983opClass=MemWrite 984opLat=2 985 986[system.cpu1.fuPool.FUList4] 987type=FUDesc 988children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 989count=2 990eventq_index=0 991opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 system.cpu1.fuPool.FUList4.opList02 system.cpu1.fuPool.FUList4.opList03 system.cpu1.fuPool.FUList4.opList04 system.cpu1.fuPool.FUList4.opList05 system.cpu1.fuPool.FUList4.opList06 system.cpu1.fuPool.FUList4.opList07 system.cpu1.fuPool.FUList4.opList08 system.cpu1.fuPool.FUList4.opList09 system.cpu1.fuPool.FUList4.opList10 system.cpu1.fuPool.FUList4.opList11 system.cpu1.fuPool.FUList4.opList12 system.cpu1.fuPool.FUList4.opList13 system.cpu1.fuPool.FUList4.opList14 system.cpu1.fuPool.FUList4.opList15 system.cpu1.fuPool.FUList4.opList16 system.cpu1.fuPool.FUList4.opList17 system.cpu1.fuPool.FUList4.opList18 system.cpu1.fuPool.FUList4.opList19 system.cpu1.fuPool.FUList4.opList20 system.cpu1.fuPool.FUList4.opList21 system.cpu1.fuPool.FUList4.opList22 system.cpu1.fuPool.FUList4.opList23 system.cpu1.fuPool.FUList4.opList24 system.cpu1.fuPool.FUList4.opList25 992 993[system.cpu1.fuPool.FUList4.opList00] 994type=OpDesc 995eventq_index=0 996issueLat=1 997opClass=SimdAdd 998opLat=4 999 1000[system.cpu1.fuPool.FUList4.opList01] 1001type=OpDesc 1002eventq_index=0 1003issueLat=1 1004opClass=SimdAddAcc 1005opLat=4 1006 1007[system.cpu1.fuPool.FUList4.opList02] 1008type=OpDesc 1009eventq_index=0 1010issueLat=1 1011opClass=SimdAlu 1012opLat=4 1013 1014[system.cpu1.fuPool.FUList4.opList03] 1015type=OpDesc 1016eventq_index=0 1017issueLat=1 1018opClass=SimdCmp 1019opLat=4 1020 1021[system.cpu1.fuPool.FUList4.opList04] 1022type=OpDesc 1023eventq_index=0 1024issueLat=1 1025opClass=SimdCvt 1026opLat=3 1027 1028[system.cpu1.fuPool.FUList4.opList05] 1029type=OpDesc 1030eventq_index=0 1031issueLat=1 1032opClass=SimdMisc 1033opLat=3 1034 1035[system.cpu1.fuPool.FUList4.opList06] 1036type=OpDesc 1037eventq_index=0 1038issueLat=1 1039opClass=SimdMult 1040opLat=5 1041 1042[system.cpu1.fuPool.FUList4.opList07] 1043type=OpDesc 1044eventq_index=0 1045issueLat=1 1046opClass=SimdMultAcc 1047opLat=5 1048 1049[system.cpu1.fuPool.FUList4.opList08] 1050type=OpDesc 1051eventq_index=0 1052issueLat=1 1053opClass=SimdShift 1054opLat=3 1055 1056[system.cpu1.fuPool.FUList4.opList09] 1057type=OpDesc 1058eventq_index=0 1059issueLat=1 1060opClass=SimdShiftAcc 1061opLat=3 1062 1063[system.cpu1.fuPool.FUList4.opList10] 1064type=OpDesc 1065eventq_index=0 1066issueLat=1 1067opClass=SimdSqrt 1068opLat=9 1069 1070[system.cpu1.fuPool.FUList4.opList11] 1071type=OpDesc 1072eventq_index=0 1073issueLat=1 1074opClass=SimdFloatAdd 1075opLat=5 1076 1077[system.cpu1.fuPool.FUList4.opList12] 1078type=OpDesc 1079eventq_index=0 1080issueLat=1 1081opClass=SimdFloatAlu 1082opLat=5 1083 1084[system.cpu1.fuPool.FUList4.opList13] 1085type=OpDesc 1086eventq_index=0 1087issueLat=1 1088opClass=SimdFloatCmp 1089opLat=3 1090 1091[system.cpu1.fuPool.FUList4.opList14] 1092type=OpDesc 1093eventq_index=0 1094issueLat=1 1095opClass=SimdFloatCvt 1096opLat=3 1097 1098[system.cpu1.fuPool.FUList4.opList15] 1099type=OpDesc 1100eventq_index=0 1101issueLat=1 1102opClass=SimdFloatDiv 1103opLat=3 1104 1105[system.cpu1.fuPool.FUList4.opList16] 1106type=OpDesc 1107eventq_index=0 1108issueLat=1 1109opClass=SimdFloatMisc 1110opLat=3 1111 1112[system.cpu1.fuPool.FUList4.opList17] 1113type=OpDesc 1114eventq_index=0 1115issueLat=1 1116opClass=SimdFloatMult 1117opLat=3 1118 1119[system.cpu1.fuPool.FUList4.opList18] 1120type=OpDesc 1121eventq_index=0 1122issueLat=1 1123opClass=SimdFloatMultAcc 1124opLat=1 1125 1126[system.cpu1.fuPool.FUList4.opList19] 1127type=OpDesc 1128eventq_index=0 1129issueLat=1 1130opClass=SimdFloatSqrt 1131opLat=9 1132 1133[system.cpu1.fuPool.FUList4.opList20] 1134type=OpDesc 1135eventq_index=0 1136issueLat=1 1137opClass=FloatAdd 1138opLat=5 1139 1140[system.cpu1.fuPool.FUList4.opList21] 1141type=OpDesc 1142eventq_index=0 1143issueLat=1 1144opClass=FloatCmp 1145opLat=5 1146 1147[system.cpu1.fuPool.FUList4.opList22] 1148type=OpDesc 1149eventq_index=0 1150issueLat=1 1151opClass=FloatCvt 1152opLat=5 1153 1154[system.cpu1.fuPool.FUList4.opList23] 1155type=OpDesc 1156eventq_index=0 1157issueLat=9 1158opClass=FloatDiv 1159opLat=9 1160 1161[system.cpu1.fuPool.FUList4.opList24] 1162type=OpDesc 1163eventq_index=0 1164issueLat=33 1165opClass=FloatSqrt 1166opLat=33 1167 1168[system.cpu1.fuPool.FUList4.opList25] 1169type=OpDesc 1170eventq_index=0 1171issueLat=1 1172opClass=FloatMult 1173opLat=4 1174 1175[system.cpu1.icache] 1176type=BaseCache 1177children=tags 1178addr_ranges=0:18446744073709551615 1179assoc=2 1180clk_domain=system.cpu_clk_domain 1181eventq_index=0 1182forward_snoops=true 1183hit_latency=1 1184is_top_level=true 1185max_miss_count=0 1186mshrs=2 1187prefetch_on_access=false 1188prefetcher=Null 1189response_latency=1 1190sequential_access=false 1191size=32768 1192system=system 1193tags=system.cpu1.icache.tags 1194tgts_per_mshr=8 1195two_queue=false 1196write_buffers=8 1197cpu_side=system.cpu1.icache_port 1198mem_side=system.cpu1.toL2Bus.slave[0] 1199 1200[system.cpu1.icache.tags] 1201type=LRU 1202assoc=2 1203block_size=64 1204clk_domain=system.cpu_clk_domain 1205eventq_index=0 1206hit_latency=1 1207sequential_access=false 1208size=32768 1209 1210[system.cpu1.interrupts] 1211type=ArmInterrupts 1212eventq_index=0 1213 1214[system.cpu1.isa] 1215type=ArmISA 1216eventq_index=0 1217fpsid=1090793632 1218id_aa64afr0_el1=0 1219id_aa64afr1_el1=0 1220id_aa64dfr0_el1=1052678 1221id_aa64dfr1_el1=0 1222id_aa64isar0_el1=0 1223id_aa64isar1_el1=0 1224id_aa64mmfr0_el1=15728642 1225id_aa64mmfr1_el1=0 1226id_aa64pfr0_el1=17 1227id_aa64pfr1_el1=0 1228id_isar0=34607377 1229id_isar1=34677009 1230id_isar2=555950401 1231id_isar3=17899825 1232id_isar4=268501314 1233id_isar5=0 1234id_mmfr0=270536963 1235id_mmfr1=0 1236id_mmfr2=19070976 1237id_mmfr3=34611729 1238id_pfr0=49 1239id_pfr1=4113 1240midr=1091551472
| 616system=system 617 618[system.cpu0.istage2_mmu] 619type=ArmStage2MMU 620children=stage2_tlb 621eventq_index=0 622stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb 623tlb=system.cpu0.itb 624 625[system.cpu0.istage2_mmu.stage2_tlb] 626type=ArmTLB 627children=walker 628eventq_index=0 629is_stage2=true 630size=32 631walker=system.cpu0.istage2_mmu.stage2_tlb.walker 632 633[system.cpu0.istage2_mmu.stage2_tlb.walker] 634type=ArmTableWalker 635clk_domain=system.cpu_clk_domain 636eventq_index=0 637is_stage2=true 638num_squash_per_cycle=2 639sys=system 640port=system.cpu0.toL2Bus.slave[4] 641 642[system.cpu0.itb] 643type=ArmTLB 644children=walker 645eventq_index=0 646is_stage2=false 647size=64 648walker=system.cpu0.itb.walker 649 650[system.cpu0.itb.walker] 651type=ArmTableWalker 652clk_domain=system.cpu_clk_domain 653eventq_index=0 654is_stage2=false 655num_squash_per_cycle=2 656sys=system 657port=system.cpu0.toL2Bus.slave[2] 658 659[system.cpu0.l2cache] 660type=BaseCache 661children=prefetcher tags 662addr_ranges=0:18446744073709551615 663assoc=16 664clk_domain=system.cpu_clk_domain 665eventq_index=0 666forward_snoops=true 667hit_latency=12 668is_top_level=false 669max_miss_count=0 670mshrs=16 671prefetch_on_access=true 672prefetcher=system.cpu0.l2cache.prefetcher 673response_latency=12 674sequential_access=false 675size=1048576 676system=system 677tags=system.cpu0.l2cache.tags 678tgts_per_mshr=8 679two_queue=false 680write_buffers=8 681cpu_side=system.cpu0.toL2Bus.master[0] 682mem_side=system.toL2Bus.slave[0] 683 684[system.cpu0.l2cache.prefetcher] 685type=StridePrefetcher 686clk_domain=system.cpu_clk_domain 687cross_pages=false 688data_accesses_only=false 689degree=8 690eventq_index=0 691inst_tagged=true 692latency=1 693on_miss_only=false 694on_prefetch=true 695on_read_only=false 696serial_squash=false 697size=100 698sys=system 699use_master_id=true 700 701[system.cpu0.l2cache.tags] 702type=RandomRepl 703assoc=16 704block_size=64 705clk_domain=system.cpu_clk_domain 706eventq_index=0 707hit_latency=12 708sequential_access=false 709size=1048576 710 711[system.cpu0.toL2Bus] 712type=CoherentXBar 713clk_domain=system.cpu_clk_domain 714eventq_index=0 715header_cycles=1 716snoop_filter=Null 717system=system 718use_default_range=false 719width=32 720master=system.cpu0.l2cache.cpu_side 721slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port 722 723[system.cpu0.tracer] 724type=ExeTracer 725eventq_index=0 726 727[system.cpu1] 728type=DerivO3CPU 729children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer 730LFSTSize=1024 731LQEntries=16 732LSQCheckLoads=true 733LSQDepCheckShift=0 734SQEntries=16 735SSITSize=1024 736activity=0 737backComSize=5 738branchPred=system.cpu1.branchPred 739cachePorts=200 740checker=Null 741clk_domain=system.cpu_clk_domain 742commitToDecodeDelay=1 743commitToFetchDelay=1 744commitToIEWDelay=1 745commitToRenameDelay=1 746commitWidth=8 747cpu_id=1 748decodeToFetchDelay=1 749decodeToRenameDelay=2 750decodeWidth=3 751dispatchWidth=6 752do_checkpoint_insts=true 753do_quiesce=true 754do_statistics_insts=true 755dstage2_mmu=system.cpu1.dstage2_mmu 756dtb=system.cpu1.dtb 757eventq_index=0 758fetchBufferSize=16 759fetchQueueSize=32 760fetchToDecodeDelay=3 761fetchTrapLatency=1 762fetchWidth=3 763forwardComSize=5 764fuPool=system.cpu1.fuPool 765function_trace=false 766function_trace_start=0 767iewToCommitDelay=1 768iewToDecodeDelay=1 769iewToFetchDelay=1 770iewToRenameDelay=1 771interrupts=system.cpu1.interrupts 772isa=system.cpu1.isa 773issueToExecuteDelay=1 774issueWidth=8 775istage2_mmu=system.cpu1.istage2_mmu 776itb=system.cpu1.itb 777max_insts_all_threads=0 778max_insts_any_thread=0 779max_loads_all_threads=0 780max_loads_any_thread=0 781needsTSO=false 782numIQEntries=32 783numPhysCCRegs=640 784numPhysFloatRegs=192 785numPhysIntRegs=128 786numROBEntries=40 787numRobs=1 788numThreads=1 789profile=0 790progress_interval=0 791renameToDecodeDelay=1 792renameToFetchDelay=1 793renameToIEWDelay=1 794renameToROBDelay=1 795renameWidth=3 796simpoint_start_insts= 797smtCommitPolicy=RoundRobin 798smtFetchPolicy=SingleThread 799smtIQPolicy=Partitioned 800smtIQThreshold=100 801smtLSQPolicy=Partitioned 802smtLSQThreshold=100 803smtNumFetchingThreads=1 804smtROBPolicy=Partitioned 805smtROBThreshold=100 806socket_id=0 807squashWidth=8 808store_set_clear_period=250000 809switched_out=false 810system=system 811tracer=system.cpu1.tracer 812trapLatency=13 813wbWidth=8 814workload= 815dcache_port=system.cpu1.dcache.cpu_side 816icache_port=system.cpu1.icache.cpu_side 817 818[system.cpu1.branchPred] 819type=BranchPredictor 820BTBEntries=2048 821BTBTagSize=18 822RASSize=16 823choiceCtrBits=2 824choicePredictorSize=8192 825eventq_index=0 826globalCtrBits=2 827globalPredictorSize=8192 828instShiftAmt=2 829localCtrBits=2 830localHistoryTableSize=2048 831localPredictorSize=2048 832numThreads=1 833predType=bi-mode 834 835[system.cpu1.dcache] 836type=BaseCache 837children=tags 838addr_ranges=0:18446744073709551615 839assoc=2 840clk_domain=system.cpu_clk_domain 841eventq_index=0 842forward_snoops=true 843hit_latency=2 844is_top_level=true 845max_miss_count=0 846mshrs=6 847prefetch_on_access=false 848prefetcher=Null 849response_latency=2 850sequential_access=false 851size=32768 852system=system 853tags=system.cpu1.dcache.tags 854tgts_per_mshr=8 855two_queue=false 856write_buffers=16 857cpu_side=system.cpu1.dcache_port 858mem_side=system.cpu1.toL2Bus.slave[1] 859 860[system.cpu1.dcache.tags] 861type=LRU 862assoc=2 863block_size=64 864clk_domain=system.cpu_clk_domain 865eventq_index=0 866hit_latency=2 867sequential_access=false 868size=32768 869 870[system.cpu1.dstage2_mmu] 871type=ArmStage2MMU 872children=stage2_tlb 873eventq_index=0 874stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb 875tlb=system.cpu1.dtb 876 877[system.cpu1.dstage2_mmu.stage2_tlb] 878type=ArmTLB 879children=walker 880eventq_index=0 881is_stage2=true 882size=32 883walker=system.cpu1.dstage2_mmu.stage2_tlb.walker 884 885[system.cpu1.dstage2_mmu.stage2_tlb.walker] 886type=ArmTableWalker 887clk_domain=system.cpu_clk_domain 888eventq_index=0 889is_stage2=true 890num_squash_per_cycle=2 891sys=system 892port=system.cpu1.toL2Bus.slave[5] 893 894[system.cpu1.dtb] 895type=ArmTLB 896children=walker 897eventq_index=0 898is_stage2=false 899size=64 900walker=system.cpu1.dtb.walker 901 902[system.cpu1.dtb.walker] 903type=ArmTableWalker 904clk_domain=system.cpu_clk_domain 905eventq_index=0 906is_stage2=false 907num_squash_per_cycle=2 908sys=system 909port=system.cpu1.toL2Bus.slave[3] 910 911[system.cpu1.fuPool] 912type=FUPool 913children=FUList0 FUList1 FUList2 FUList3 FUList4 914FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 915eventq_index=0 916 917[system.cpu1.fuPool.FUList0] 918type=FUDesc 919children=opList 920count=2 921eventq_index=0 922opList=system.cpu1.fuPool.FUList0.opList 923 924[system.cpu1.fuPool.FUList0.opList] 925type=OpDesc 926eventq_index=0 927issueLat=1 928opClass=IntAlu 929opLat=1 930 931[system.cpu1.fuPool.FUList1] 932type=FUDesc 933children=opList0 opList1 opList2 934count=1 935eventq_index=0 936opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 system.cpu1.fuPool.FUList1.opList2 937 938[system.cpu1.fuPool.FUList1.opList0] 939type=OpDesc 940eventq_index=0 941issueLat=1 942opClass=IntMult 943opLat=3 944 945[system.cpu1.fuPool.FUList1.opList1] 946type=OpDesc 947eventq_index=0 948issueLat=12 949opClass=IntDiv 950opLat=12 951 952[system.cpu1.fuPool.FUList1.opList2] 953type=OpDesc 954eventq_index=0 955issueLat=1 956opClass=IprAccess 957opLat=3 958 959[system.cpu1.fuPool.FUList2] 960type=FUDesc 961children=opList 962count=1 963eventq_index=0 964opList=system.cpu1.fuPool.FUList2.opList 965 966[system.cpu1.fuPool.FUList2.opList] 967type=OpDesc 968eventq_index=0 969issueLat=1 970opClass=MemRead 971opLat=2 972 973[system.cpu1.fuPool.FUList3] 974type=FUDesc 975children=opList 976count=1 977eventq_index=0 978opList=system.cpu1.fuPool.FUList3.opList 979 980[system.cpu1.fuPool.FUList3.opList] 981type=OpDesc 982eventq_index=0 983issueLat=1 984opClass=MemWrite 985opLat=2 986 987[system.cpu1.fuPool.FUList4] 988type=FUDesc 989children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 990count=2 991eventq_index=0 992opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 system.cpu1.fuPool.FUList4.opList02 system.cpu1.fuPool.FUList4.opList03 system.cpu1.fuPool.FUList4.opList04 system.cpu1.fuPool.FUList4.opList05 system.cpu1.fuPool.FUList4.opList06 system.cpu1.fuPool.FUList4.opList07 system.cpu1.fuPool.FUList4.opList08 system.cpu1.fuPool.FUList4.opList09 system.cpu1.fuPool.FUList4.opList10 system.cpu1.fuPool.FUList4.opList11 system.cpu1.fuPool.FUList4.opList12 system.cpu1.fuPool.FUList4.opList13 system.cpu1.fuPool.FUList4.opList14 system.cpu1.fuPool.FUList4.opList15 system.cpu1.fuPool.FUList4.opList16 system.cpu1.fuPool.FUList4.opList17 system.cpu1.fuPool.FUList4.opList18 system.cpu1.fuPool.FUList4.opList19 system.cpu1.fuPool.FUList4.opList20 system.cpu1.fuPool.FUList4.opList21 system.cpu1.fuPool.FUList4.opList22 system.cpu1.fuPool.FUList4.opList23 system.cpu1.fuPool.FUList4.opList24 system.cpu1.fuPool.FUList4.opList25 993 994[system.cpu1.fuPool.FUList4.opList00] 995type=OpDesc 996eventq_index=0 997issueLat=1 998opClass=SimdAdd 999opLat=4 1000 1001[system.cpu1.fuPool.FUList4.opList01] 1002type=OpDesc 1003eventq_index=0 1004issueLat=1 1005opClass=SimdAddAcc 1006opLat=4 1007 1008[system.cpu1.fuPool.FUList4.opList02] 1009type=OpDesc 1010eventq_index=0 1011issueLat=1 1012opClass=SimdAlu 1013opLat=4 1014 1015[system.cpu1.fuPool.FUList4.opList03] 1016type=OpDesc 1017eventq_index=0 1018issueLat=1 1019opClass=SimdCmp 1020opLat=4 1021 1022[system.cpu1.fuPool.FUList4.opList04] 1023type=OpDesc 1024eventq_index=0 1025issueLat=1 1026opClass=SimdCvt 1027opLat=3 1028 1029[system.cpu1.fuPool.FUList4.opList05] 1030type=OpDesc 1031eventq_index=0 1032issueLat=1 1033opClass=SimdMisc 1034opLat=3 1035 1036[system.cpu1.fuPool.FUList4.opList06] 1037type=OpDesc 1038eventq_index=0 1039issueLat=1 1040opClass=SimdMult 1041opLat=5 1042 1043[system.cpu1.fuPool.FUList4.opList07] 1044type=OpDesc 1045eventq_index=0 1046issueLat=1 1047opClass=SimdMultAcc 1048opLat=5 1049 1050[system.cpu1.fuPool.FUList4.opList08] 1051type=OpDesc 1052eventq_index=0 1053issueLat=1 1054opClass=SimdShift 1055opLat=3 1056 1057[system.cpu1.fuPool.FUList4.opList09] 1058type=OpDesc 1059eventq_index=0 1060issueLat=1 1061opClass=SimdShiftAcc 1062opLat=3 1063 1064[system.cpu1.fuPool.FUList4.opList10] 1065type=OpDesc 1066eventq_index=0 1067issueLat=1 1068opClass=SimdSqrt 1069opLat=9 1070 1071[system.cpu1.fuPool.FUList4.opList11] 1072type=OpDesc 1073eventq_index=0 1074issueLat=1 1075opClass=SimdFloatAdd 1076opLat=5 1077 1078[system.cpu1.fuPool.FUList4.opList12] 1079type=OpDesc 1080eventq_index=0 1081issueLat=1 1082opClass=SimdFloatAlu 1083opLat=5 1084 1085[system.cpu1.fuPool.FUList4.opList13] 1086type=OpDesc 1087eventq_index=0 1088issueLat=1 1089opClass=SimdFloatCmp 1090opLat=3 1091 1092[system.cpu1.fuPool.FUList4.opList14] 1093type=OpDesc 1094eventq_index=0 1095issueLat=1 1096opClass=SimdFloatCvt 1097opLat=3 1098 1099[system.cpu1.fuPool.FUList4.opList15] 1100type=OpDesc 1101eventq_index=0 1102issueLat=1 1103opClass=SimdFloatDiv 1104opLat=3 1105 1106[system.cpu1.fuPool.FUList4.opList16] 1107type=OpDesc 1108eventq_index=0 1109issueLat=1 1110opClass=SimdFloatMisc 1111opLat=3 1112 1113[system.cpu1.fuPool.FUList4.opList17] 1114type=OpDesc 1115eventq_index=0 1116issueLat=1 1117opClass=SimdFloatMult 1118opLat=3 1119 1120[system.cpu1.fuPool.FUList4.opList18] 1121type=OpDesc 1122eventq_index=0 1123issueLat=1 1124opClass=SimdFloatMultAcc 1125opLat=1 1126 1127[system.cpu1.fuPool.FUList4.opList19] 1128type=OpDesc 1129eventq_index=0 1130issueLat=1 1131opClass=SimdFloatSqrt 1132opLat=9 1133 1134[system.cpu1.fuPool.FUList4.opList20] 1135type=OpDesc 1136eventq_index=0 1137issueLat=1 1138opClass=FloatAdd 1139opLat=5 1140 1141[system.cpu1.fuPool.FUList4.opList21] 1142type=OpDesc 1143eventq_index=0 1144issueLat=1 1145opClass=FloatCmp 1146opLat=5 1147 1148[system.cpu1.fuPool.FUList4.opList22] 1149type=OpDesc 1150eventq_index=0 1151issueLat=1 1152opClass=FloatCvt 1153opLat=5 1154 1155[system.cpu1.fuPool.FUList4.opList23] 1156type=OpDesc 1157eventq_index=0 1158issueLat=9 1159opClass=FloatDiv 1160opLat=9 1161 1162[system.cpu1.fuPool.FUList4.opList24] 1163type=OpDesc 1164eventq_index=0 1165issueLat=33 1166opClass=FloatSqrt 1167opLat=33 1168 1169[system.cpu1.fuPool.FUList4.opList25] 1170type=OpDesc 1171eventq_index=0 1172issueLat=1 1173opClass=FloatMult 1174opLat=4 1175 1176[system.cpu1.icache] 1177type=BaseCache 1178children=tags 1179addr_ranges=0:18446744073709551615 1180assoc=2 1181clk_domain=system.cpu_clk_domain 1182eventq_index=0 1183forward_snoops=true 1184hit_latency=1 1185is_top_level=true 1186max_miss_count=0 1187mshrs=2 1188prefetch_on_access=false 1189prefetcher=Null 1190response_latency=1 1191sequential_access=false 1192size=32768 1193system=system 1194tags=system.cpu1.icache.tags 1195tgts_per_mshr=8 1196two_queue=false 1197write_buffers=8 1198cpu_side=system.cpu1.icache_port 1199mem_side=system.cpu1.toL2Bus.slave[0] 1200 1201[system.cpu1.icache.tags] 1202type=LRU 1203assoc=2 1204block_size=64 1205clk_domain=system.cpu_clk_domain 1206eventq_index=0 1207hit_latency=1 1208sequential_access=false 1209size=32768 1210 1211[system.cpu1.interrupts] 1212type=ArmInterrupts 1213eventq_index=0 1214 1215[system.cpu1.isa] 1216type=ArmISA 1217eventq_index=0 1218fpsid=1090793632 1219id_aa64afr0_el1=0 1220id_aa64afr1_el1=0 1221id_aa64dfr0_el1=1052678 1222id_aa64dfr1_el1=0 1223id_aa64isar0_el1=0 1224id_aa64isar1_el1=0 1225id_aa64mmfr0_el1=15728642 1226id_aa64mmfr1_el1=0 1227id_aa64pfr0_el1=17 1228id_aa64pfr1_el1=0 1229id_isar0=34607377 1230id_isar1=34677009 1231id_isar2=555950401 1232id_isar3=17899825 1233id_isar4=268501314 1234id_isar5=0 1235id_mmfr0=270536963 1236id_mmfr1=0 1237id_mmfr2=19070976 1238id_mmfr3=34611729 1239id_pfr0=49 1240id_pfr1=4113 1241midr=1091551472
|
| 1242pmu=Null
|
1241system=system 1242 1243[system.cpu1.istage2_mmu] 1244type=ArmStage2MMU 1245children=stage2_tlb 1246eventq_index=0 1247stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb 1248tlb=system.cpu1.itb 1249 1250[system.cpu1.istage2_mmu.stage2_tlb] 1251type=ArmTLB 1252children=walker 1253eventq_index=0 1254is_stage2=true 1255size=32 1256walker=system.cpu1.istage2_mmu.stage2_tlb.walker 1257 1258[system.cpu1.istage2_mmu.stage2_tlb.walker] 1259type=ArmTableWalker 1260clk_domain=system.cpu_clk_domain 1261eventq_index=0 1262is_stage2=true 1263num_squash_per_cycle=2 1264sys=system 1265port=system.cpu1.toL2Bus.slave[4] 1266 1267[system.cpu1.itb] 1268type=ArmTLB 1269children=walker 1270eventq_index=0 1271is_stage2=false 1272size=64 1273walker=system.cpu1.itb.walker 1274 1275[system.cpu1.itb.walker] 1276type=ArmTableWalker 1277clk_domain=system.cpu_clk_domain 1278eventq_index=0 1279is_stage2=false 1280num_squash_per_cycle=2 1281sys=system 1282port=system.cpu1.toL2Bus.slave[2] 1283 1284[system.cpu1.l2cache] 1285type=BaseCache 1286children=prefetcher tags 1287addr_ranges=0:18446744073709551615 1288assoc=16 1289clk_domain=system.cpu_clk_domain 1290eventq_index=0 1291forward_snoops=true 1292hit_latency=12 1293is_top_level=false 1294max_miss_count=0 1295mshrs=16 1296prefetch_on_access=true 1297prefetcher=system.cpu1.l2cache.prefetcher 1298response_latency=12 1299sequential_access=false 1300size=1048576 1301system=system 1302tags=system.cpu1.l2cache.tags 1303tgts_per_mshr=8 1304two_queue=false 1305write_buffers=8 1306cpu_side=system.cpu1.toL2Bus.master[0] 1307mem_side=system.toL2Bus.slave[1] 1308 1309[system.cpu1.l2cache.prefetcher] 1310type=StridePrefetcher 1311clk_domain=system.cpu_clk_domain 1312cross_pages=false 1313data_accesses_only=false 1314degree=8 1315eventq_index=0 1316inst_tagged=true 1317latency=1 1318on_miss_only=false 1319on_prefetch=true 1320on_read_only=false 1321serial_squash=false 1322size=100 1323sys=system 1324use_master_id=true 1325 1326[system.cpu1.l2cache.tags] 1327type=RandomRepl 1328assoc=16 1329block_size=64 1330clk_domain=system.cpu_clk_domain 1331eventq_index=0 1332hit_latency=12 1333sequential_access=false 1334size=1048576 1335 1336[system.cpu1.toL2Bus] 1337type=CoherentXBar 1338clk_domain=system.cpu_clk_domain 1339eventq_index=0 1340header_cycles=1 1341snoop_filter=Null 1342system=system 1343use_default_range=false 1344width=32 1345master=system.cpu1.l2cache.cpu_side 1346slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port 1347 1348[system.cpu1.tracer] 1349type=ExeTracer 1350eventq_index=0 1351 1352[system.cpu_clk_domain] 1353type=SrcClockDomain 1354clock=500 1355domain_id=-1 1356eventq_index=0 1357init_perf_level=0 1358voltage_domain=system.voltage_domain 1359 1360[system.dvfs_handler] 1361type=DVFSHandler 1362domains= 1363enable=false 1364eventq_index=0 1365sys_clk_domain=system.clk_domain 1366transition_latency=100000000 1367 1368[system.intrctrl] 1369type=IntrControl 1370eventq_index=0 1371sys=system 1372 1373[system.iobus] 1374type=NoncoherentXBar 1375clk_domain=system.clk_domain 1376eventq_index=0 1377header_cycles=1
| 1243system=system 1244 1245[system.cpu1.istage2_mmu] 1246type=ArmStage2MMU 1247children=stage2_tlb 1248eventq_index=0 1249stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb 1250tlb=system.cpu1.itb 1251 1252[system.cpu1.istage2_mmu.stage2_tlb] 1253type=ArmTLB 1254children=walker 1255eventq_index=0 1256is_stage2=true 1257size=32 1258walker=system.cpu1.istage2_mmu.stage2_tlb.walker 1259 1260[system.cpu1.istage2_mmu.stage2_tlb.walker] 1261type=ArmTableWalker 1262clk_domain=system.cpu_clk_domain 1263eventq_index=0 1264is_stage2=true 1265num_squash_per_cycle=2 1266sys=system 1267port=system.cpu1.toL2Bus.slave[4] 1268 1269[system.cpu1.itb] 1270type=ArmTLB 1271children=walker 1272eventq_index=0 1273is_stage2=false 1274size=64 1275walker=system.cpu1.itb.walker 1276 1277[system.cpu1.itb.walker] 1278type=ArmTableWalker 1279clk_domain=system.cpu_clk_domain 1280eventq_index=0 1281is_stage2=false 1282num_squash_per_cycle=2 1283sys=system 1284port=system.cpu1.toL2Bus.slave[2] 1285 1286[system.cpu1.l2cache] 1287type=BaseCache 1288children=prefetcher tags 1289addr_ranges=0:18446744073709551615 1290assoc=16 1291clk_domain=system.cpu_clk_domain 1292eventq_index=0 1293forward_snoops=true 1294hit_latency=12 1295is_top_level=false 1296max_miss_count=0 1297mshrs=16 1298prefetch_on_access=true 1299prefetcher=system.cpu1.l2cache.prefetcher 1300response_latency=12 1301sequential_access=false 1302size=1048576 1303system=system 1304tags=system.cpu1.l2cache.tags 1305tgts_per_mshr=8 1306two_queue=false 1307write_buffers=8 1308cpu_side=system.cpu1.toL2Bus.master[0] 1309mem_side=system.toL2Bus.slave[1] 1310 1311[system.cpu1.l2cache.prefetcher] 1312type=StridePrefetcher 1313clk_domain=system.cpu_clk_domain 1314cross_pages=false 1315data_accesses_only=false 1316degree=8 1317eventq_index=0 1318inst_tagged=true 1319latency=1 1320on_miss_only=false 1321on_prefetch=true 1322on_read_only=false 1323serial_squash=false 1324size=100 1325sys=system 1326use_master_id=true 1327 1328[system.cpu1.l2cache.tags] 1329type=RandomRepl 1330assoc=16 1331block_size=64 1332clk_domain=system.cpu_clk_domain 1333eventq_index=0 1334hit_latency=12 1335sequential_access=false 1336size=1048576 1337 1338[system.cpu1.toL2Bus] 1339type=CoherentXBar 1340clk_domain=system.cpu_clk_domain 1341eventq_index=0 1342header_cycles=1 1343snoop_filter=Null 1344system=system 1345use_default_range=false 1346width=32 1347master=system.cpu1.l2cache.cpu_side 1348slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port 1349 1350[system.cpu1.tracer] 1351type=ExeTracer 1352eventq_index=0 1353 1354[system.cpu_clk_domain] 1355type=SrcClockDomain 1356clock=500 1357domain_id=-1 1358eventq_index=0 1359init_perf_level=0 1360voltage_domain=system.voltage_domain 1361 1362[system.dvfs_handler] 1363type=DVFSHandler 1364domains= 1365enable=false 1366eventq_index=0 1367sys_clk_domain=system.clk_domain 1368transition_latency=100000000 1369 1370[system.intrctrl] 1371type=IntrControl 1372eventq_index=0 1373sys=system 1374 1375[system.iobus] 1376type=NoncoherentXBar 1377clk_domain=system.clk_domain 1378eventq_index=0 1379header_cycles=1
|
1378use_default_range=false
| 1380use_default_range=true
|
1379width=8
| 1381width=8
|
1380master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side 1381slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
| 1382default=system.realview.pciconfig.pio 1383master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side 1384slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
|
1382 1383[system.iocache] 1384type=BaseCache 1385children=tags
| 1385 1386[system.iocache] 1387type=BaseCache 1388children=tags
|
1386addr_ranges=0:134217727
| 1389addr_ranges=2147483648:2415919103
|
1387assoc=8 1388clk_domain=system.clk_domain 1389eventq_index=0 1390forward_snoops=false 1391hit_latency=50 1392is_top_level=true 1393max_miss_count=0 1394mshrs=20 1395prefetch_on_access=false 1396prefetcher=Null 1397response_latency=50 1398sequential_access=false 1399size=1024 1400system=system 1401tags=system.iocache.tags 1402tgts_per_mshr=12 1403two_queue=false 1404write_buffers=8
| 1390assoc=8 1391clk_domain=system.clk_domain 1392eventq_index=0 1393forward_snoops=false 1394hit_latency=50 1395is_top_level=true 1396max_miss_count=0 1397mshrs=20 1398prefetch_on_access=false 1399prefetcher=Null 1400response_latency=50 1401sequential_access=false 1402size=1024 1403system=system 1404tags=system.iocache.tags 1405tgts_per_mshr=12 1406two_queue=false 1407write_buffers=8
|
1405cpu_side=system.iobus.master[26] 1406mem_side=system.membus.slave[2]
| 1408cpu_side=system.iobus.master[27] 1409mem_side=system.membus.slave[3]
|
1407 1408[system.iocache.tags] 1409type=LRU 1410assoc=8 1411block_size=64 1412clk_domain=system.clk_domain 1413eventq_index=0 1414hit_latency=50 1415sequential_access=false 1416size=1024 1417 1418[system.l2c] 1419type=BaseCache 1420children=tags 1421addr_ranges=0:18446744073709551615 1422assoc=8 1423clk_domain=system.cpu_clk_domain 1424eventq_index=0 1425forward_snoops=true 1426hit_latency=20 1427is_top_level=false 1428max_miss_count=0 1429mshrs=20 1430prefetch_on_access=false 1431prefetcher=Null 1432response_latency=20 1433sequential_access=false 1434size=4194304 1435system=system 1436tags=system.l2c.tags 1437tgts_per_mshr=12 1438two_queue=false 1439write_buffers=8 1440cpu_side=system.toL2Bus.master[0]
| 1410 1411[system.iocache.tags] 1412type=LRU 1413assoc=8 1414block_size=64 1415clk_domain=system.clk_domain 1416eventq_index=0 1417hit_latency=50 1418sequential_access=false 1419size=1024 1420 1421[system.l2c] 1422type=BaseCache 1423children=tags 1424addr_ranges=0:18446744073709551615 1425assoc=8 1426clk_domain=system.cpu_clk_domain 1427eventq_index=0 1428forward_snoops=true 1429hit_latency=20 1430is_top_level=false 1431max_miss_count=0 1432mshrs=20 1433prefetch_on_access=false 1434prefetcher=Null 1435response_latency=20 1436sequential_access=false 1437size=4194304 1438system=system 1439tags=system.l2c.tags 1440tgts_per_mshr=12 1441two_queue=false 1442write_buffers=8 1443cpu_side=system.toL2Bus.master[0]
|
1441mem_side=system.membus.slave[1]
| 1444mem_side=system.membus.slave[2]
|
1442 1443[system.l2c.tags] 1444type=LRU 1445assoc=8 1446block_size=64 1447clk_domain=system.cpu_clk_domain 1448eventq_index=0 1449hit_latency=20 1450sequential_access=false 1451size=4194304 1452 1453[system.membus] 1454type=CoherentXBar 1455children=badaddr_responder 1456clk_domain=system.clk_domain 1457eventq_index=0 1458header_cycles=1 1459snoop_filter=Null 1460system=system 1461use_default_range=false 1462width=8 1463default=system.membus.badaddr_responder.pio
| 1445 1446[system.l2c.tags] 1447type=LRU 1448assoc=8 1449block_size=64 1450clk_domain=system.cpu_clk_domain 1451eventq_index=0 1452hit_latency=20 1453sequential_access=false 1454size=4194304 1455 1456[system.membus] 1457type=CoherentXBar 1458children=badaddr_responder 1459clk_domain=system.clk_domain 1460eventq_index=0 1461header_cycles=1 1462snoop_filter=Null 1463system=system 1464use_default_range=false 1465width=8 1466default=system.membus.badaddr_responder.pio
|
1464master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port 1465slave=system.system_port system.l2c.mem_side system.iocache.mem_side
| 1467master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port 1468slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
|
1466 1467[system.membus.badaddr_responder] 1468type=IsaFake 1469clk_domain=system.clk_domain 1470eventq_index=0 1471fake_mem=false 1472pio_addr=0 1473pio_latency=100000 1474pio_size=8 1475ret_bad_addr=true 1476ret_data16=65535 1477ret_data32=4294967295 1478ret_data64=18446744073709551615 1479ret_data8=255 1480system=system 1481update_data=false 1482warn_access=warn 1483pio=system.membus.default 1484 1485[system.physmem] 1486type=DRAMCtrl 1487IDD0=0.075000 1488IDD02=0.000000 1489IDD2N=0.050000 1490IDD2N2=0.000000 1491IDD2P0=0.000000 1492IDD2P02=0.000000 1493IDD2P1=0.000000 1494IDD2P12=0.000000 1495IDD3N=0.057000 1496IDD3N2=0.000000 1497IDD3P0=0.000000 1498IDD3P02=0.000000 1499IDD3P1=0.000000 1500IDD3P12=0.000000 1501IDD4R=0.187000 1502IDD4R2=0.000000 1503IDD4W=0.165000 1504IDD4W2=0.000000 1505IDD5=0.220000 1506IDD52=0.000000 1507IDD6=0.000000 1508IDD62=0.000000 1509VDD=1.500000 1510VDD2=0.000000 1511activation_limit=4 1512addr_mapping=RoRaBaChCo 1513bank_groups_per_rank=0 1514banks_per_rank=8 1515burst_length=8 1516channels=1 1517clk_domain=system.clk_domain 1518conf_table_reported=true 1519device_bus_width=8 1520device_rowbuffer_size=1024
| 1469 1470[system.membus.badaddr_responder] 1471type=IsaFake 1472clk_domain=system.clk_domain 1473eventq_index=0 1474fake_mem=false 1475pio_addr=0 1476pio_latency=100000 1477pio_size=8 1478ret_bad_addr=true 1479ret_data16=65535 1480ret_data32=4294967295 1481ret_data64=18446744073709551615 1482ret_data8=255 1483system=system 1484update_data=false 1485warn_access=warn 1486pio=system.membus.default 1487 1488[system.physmem] 1489type=DRAMCtrl 1490IDD0=0.075000 1491IDD02=0.000000 1492IDD2N=0.050000 1493IDD2N2=0.000000 1494IDD2P0=0.000000 1495IDD2P02=0.000000 1496IDD2P1=0.000000 1497IDD2P12=0.000000 1498IDD3N=0.057000 1499IDD3N2=0.000000 1500IDD3P0=0.000000 1501IDD3P02=0.000000 1502IDD3P1=0.000000 1503IDD3P12=0.000000 1504IDD4R=0.187000 1505IDD4R2=0.000000 1506IDD4W=0.165000 1507IDD4W2=0.000000 1508IDD5=0.220000 1509IDD52=0.000000 1510IDD6=0.000000 1511IDD62=0.000000 1512VDD=1.500000 1513VDD2=0.000000 1514activation_limit=4 1515addr_mapping=RoRaBaChCo 1516bank_groups_per_rank=0 1517banks_per_rank=8 1518burst_length=8 1519channels=1 1520clk_domain=system.clk_domain 1521conf_table_reported=true 1522device_bus_width=8 1523device_rowbuffer_size=1024
|
| 1524device_size=536870912
|
1521devices_per_rank=8 1522dll=true 1523eventq_index=0 1524in_addr_map=true 1525max_accesses_per_row=16 1526mem_sched_policy=frfcfs 1527min_writes_per_switch=16 1528null=false 1529page_policy=open_adaptive
| 1525devices_per_rank=8 1526dll=true 1527eventq_index=0 1528in_addr_map=true 1529max_accesses_per_row=16 1530mem_sched_policy=frfcfs 1531min_writes_per_switch=16 1532null=false 1533page_policy=open_adaptive
|
1530range=0:134217727
| 1534range=2147483648:2415919103
|
1531ranks_per_channel=2 1532read_buffer_size=32 1533static_backend_latency=10000 1534static_frontend_latency=10000 1535tBURST=5000 1536tCCD_L=0 1537tCK=1250 1538tCL=13750 1539tCS=2500 1540tRAS=35000 1541tRCD=13750 1542tREFI=7800000 1543tRFC=260000 1544tRP=13750 1545tRRD=6000 1546tRRD_L=0 1547tRTP=7500 1548tRTW=2500 1549tWR=15000 1550tWTR=7500 1551tXAW=30000 1552tXP=0 1553tXPDLL=0 1554tXS=0 1555tXSDLL=0 1556write_buffer_size=64 1557write_high_thresh_perc=85 1558write_low_thresh_perc=50
| 1535ranks_per_channel=2 1536read_buffer_size=32 1537static_backend_latency=10000 1538static_frontend_latency=10000 1539tBURST=5000 1540tCCD_L=0 1541tCK=1250 1542tCL=13750 1543tCS=2500 1544tRAS=35000 1545tRCD=13750 1546tREFI=7800000 1547tRFC=260000 1548tRP=13750 1549tRRD=6000 1550tRRD_L=0 1551tRTP=7500 1552tRTW=2500 1553tWR=15000 1554tWTR=7500 1555tXAW=30000 1556tXP=0 1557tXPDLL=0 1558tXS=0 1559tXSDLL=0 1560write_buffer_size=64 1561write_high_thresh_perc=85 1562write_low_thresh_perc=50
|
1559port=system.membus.master[6]
| 1563port=system.membus.master[5]
|
1560 1561[system.realview] 1562type=RealView
| 1564 1565[system.realview] 1566type=RealView
|
1563children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
| 1567children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
|
1564eventq_index=0 1565intrctrl=system.intrctrl
| 1568eventq_index=0 1569intrctrl=system.intrctrl
|
1566pci_cfg_base=0
| 1570pci_cfg_base=805306368
|
1567pci_cfg_gen_offsets=false 1568pci_io_base=0 1569system=system 1570
| 1571pci_cfg_gen_offsets=false 1572pci_io_base=0 1573system=system 1574
|
1571[system.realview.a9scu] 1572type=A9SCU 1573clk_domain=system.clk_domain 1574eventq_index=0 1575pio_addr=520093696 1576pio_latency=100000 1577system=system 1578pio=system.membus.master[4] 1579
| |
1580[system.realview.aaci_fake] 1581type=AmbaFake 1582amba_id=0 1583clk_domain=system.clk_domain 1584eventq_index=0 1585ignore_access=false
| 1575[system.realview.aaci_fake] 1576type=AmbaFake 1577amba_id=0 1578clk_domain=system.clk_domain 1579eventq_index=0 1580ignore_access=false
|
1586pio_addr=268451840
| 1581pio_addr=470024192
|
1587pio_latency=100000 1588system=system
| 1582pio_latency=100000 1583system=system
|
1589pio=system.iobus.master[21]
| 1584pio=system.iobus.master[18]
|
1590 1591[system.realview.cf_ctrl] 1592type=IdeController
| 1585 1586[system.realview.cf_ctrl] 1587type=IdeController
|
1593BAR0=402653184
| 1588BAR0=471465984
|
1594BAR0LegacyIO=true
| 1589BAR0LegacyIO=true
|
1595BAR0Size=16 1596BAR1=402653440
| 1590BAR0Size=256 1591BAR1=471466240
|
1597BAR1LegacyIO=true
| 1592BAR1LegacyIO=true
|
1598BAR1Size=1
| 1593BAR1Size=4096
|
1599BAR2=1 1600BAR2LegacyIO=false 1601BAR2Size=8 1602BAR3=1 1603BAR3LegacyIO=false 1604BAR3Size=4 1605BAR4=1 1606BAR4LegacyIO=false 1607BAR4Size=16 1608BAR5=1 1609BAR5LegacyIO=false 1610BAR5Size=0 1611BIST=0 1612CacheLineSize=0 1613CapabilityPtr=0 1614CardbusCIS=0 1615ClassCode=1 1616Command=1 1617DeviceID=28945 1618ExpansionROM=0 1619HeaderType=0 1620InterruptLine=31 1621InterruptPin=1 1622LatencyTimer=0 1623LegacyIOBase=0 1624MSICAPBaseOffset=0 1625MSICAPCapId=0 1626MSICAPMaskBits=0 1627MSICAPMsgAddr=0 1628MSICAPMsgCtrl=0 1629MSICAPMsgData=0 1630MSICAPMsgUpperAddr=0 1631MSICAPNextCapability=0 1632MSICAPPendingBits=0 1633MSIXCAPBaseOffset=0 1634MSIXCAPCapId=0 1635MSIXCAPNextCapability=0 1636MSIXMsgCtrl=0 1637MSIXPbaOffset=0 1638MSIXTableOffset=0 1639MaximumLatency=0 1640MinimumGrant=0 1641PMCAPBaseOffset=0 1642PMCAPCapId=0 1643PMCAPCapabilities=0 1644PMCAPCtrlStatus=0 1645PMCAPNextCapability=0 1646PXCAPBaseOffset=0 1647PXCAPCapId=0 1648PXCAPCapabilities=0 1649PXCAPDevCap2=0 1650PXCAPDevCapabilities=0 1651PXCAPDevCtrl=0 1652PXCAPDevCtrl2=0 1653PXCAPDevStatus=0 1654PXCAPLinkCap=0 1655PXCAPLinkCtrl=0 1656PXCAPLinkStatus=0 1657PXCAPNextCapability=0 1658ProgIF=133 1659Revision=0 1660Status=640 1661SubClassCode=1 1662SubsystemID=0 1663SubsystemVendorID=0 1664VendorID=32902 1665clk_domain=system.clk_domain 1666config_latency=20000 1667ctrl_offset=2
| 1594BAR2=1 1595BAR2LegacyIO=false 1596BAR2Size=8 1597BAR3=1 1598BAR3LegacyIO=false 1599BAR3Size=4 1600BAR4=1 1601BAR4LegacyIO=false 1602BAR4Size=16 1603BAR5=1 1604BAR5LegacyIO=false 1605BAR5Size=0 1606BIST=0 1607CacheLineSize=0 1608CapabilityPtr=0 1609CardbusCIS=0 1610ClassCode=1 1611Command=1 1612DeviceID=28945 1613ExpansionROM=0 1614HeaderType=0 1615InterruptLine=31 1616InterruptPin=1 1617LatencyTimer=0 1618LegacyIOBase=0 1619MSICAPBaseOffset=0 1620MSICAPCapId=0 1621MSICAPMaskBits=0 1622MSICAPMsgAddr=0 1623MSICAPMsgCtrl=0 1624MSICAPMsgData=0 1625MSICAPMsgUpperAddr=0 1626MSICAPNextCapability=0 1627MSICAPPendingBits=0 1628MSIXCAPBaseOffset=0 1629MSIXCAPCapId=0 1630MSIXCAPNextCapability=0 1631MSIXMsgCtrl=0 1632MSIXPbaOffset=0 1633MSIXTableOffset=0 1634MaximumLatency=0 1635MinimumGrant=0 1636PMCAPBaseOffset=0 1637PMCAPCapId=0 1638PMCAPCapabilities=0 1639PMCAPCtrlStatus=0 1640PMCAPNextCapability=0 1641PXCAPBaseOffset=0 1642PXCAPCapId=0 1643PXCAPCapabilities=0 1644PXCAPDevCap2=0 1645PXCAPDevCapabilities=0 1646PXCAPDevCtrl=0 1647PXCAPDevCtrl2=0 1648PXCAPDevStatus=0 1649PXCAPLinkCap=0 1650PXCAPLinkCtrl=0 1651PXCAPLinkStatus=0 1652PXCAPNextCapability=0 1653ProgIF=133 1654Revision=0 1655Status=640 1656SubClassCode=1 1657SubsystemID=0 1658SubsystemVendorID=0 1659VendorID=32902 1660clk_domain=system.clk_domain 1661config_latency=20000 1662ctrl_offset=2
|
1668disks=system.cf0
| 1663disks=
|
1669eventq_index=0
| 1664eventq_index=0
|
1670io_shift=1
| 1665io_shift=2
|
1671pci_bus=2
| 1666pci_bus=2
|
1672pci_dev=7
| 1667pci_dev=0
|
1673pci_func=0 1674pio_latency=30000 1675platform=system.realview 1676system=system
| 1668pci_func=0 1669pio_latency=30000 1670platform=system.realview 1671system=system
|
1677config=system.iobus.master[8]
| 1672config=system.iobus.master[9]
|
1678dma=system.iobus.slave[2]
| 1673dma=system.iobus.slave[2]
|
1679pio=system.iobus.master[7]
| 1674pio=system.iobus.master[8]
|
1680 1681[system.realview.clcd] 1682type=Pl111 1683amba_id=1315089 1684clk_domain=system.clk_domain 1685enable_capture=true 1686eventq_index=0 1687gic=system.realview.gic
| 1675 1676[system.realview.clcd] 1677type=Pl111 1678amba_id=1315089 1679clk_domain=system.clk_domain 1680enable_capture=true 1681eventq_index=0 1682gic=system.realview.gic
|
1688int_num=55 1689pio_addr=268566528
| 1683int_num=46 1684pio_addr=471793664
|
1690pio_latency=10000 1691pixel_clock=41667 1692system=system 1693vnc=system.vncserver 1694dma=system.iobus.slave[1] 1695pio=system.iobus.master[4] 1696
| 1685pio_latency=10000 1686pixel_clock=41667 1687system=system 1688vnc=system.vncserver 1689dma=system.iobus.slave[1] 1690pio=system.iobus.master[4] 1691
|
1697[system.realview.dmac_fake] 1698type=AmbaFake 1699amba_id=0
| 1692[system.realview.energy_ctrl] 1693type=EnergyCtrl
|
1700clk_domain=system.clk_domain
| 1694clk_domain=system.clk_domain
|
| 1695dvfs_handler=system.dvfs_handler
|
1701eventq_index=0
| 1696eventq_index=0
|
1702ignore_access=false 1703pio_addr=268632064
| 1697pio_addr=470286336
|
1704pio_latency=100000 1705system=system
| 1698pio_latency=100000 1699system=system
|
1706pio=system.iobus.master[9]
| 1700pio=system.iobus.master[22]
|
1707
| 1701
|
1708[system.realview.energy_ctrl] 1709type=EnergyCtrl
| 1702[system.realview.ethernet] 1703type=IGbE 1704BAR0=0 1705BAR0LegacyIO=false 1706BAR0Size=131072 1707BAR1=0 1708BAR1LegacyIO=false 1709BAR1Size=0 1710BAR2=0 1711BAR2LegacyIO=false 1712BAR2Size=0 1713BAR3=0 1714BAR3LegacyIO=false 1715BAR3Size=0 1716BAR4=0 1717BAR4LegacyIO=false 1718BAR4Size=0 1719BAR5=0 1720BAR5LegacyIO=false 1721BAR5Size=0 1722BIST=0 1723CacheLineSize=0 1724CapabilityPtr=0 1725CardbusCIS=0 1726ClassCode=2 1727Command=0 1728DeviceID=4213 1729ExpansionROM=0 1730HeaderType=0 1731InterruptLine=1 1732InterruptPin=1 1733LatencyTimer=0 1734LegacyIOBase=0 1735MSICAPBaseOffset=0 1736MSICAPCapId=0 1737MSICAPMaskBits=0 1738MSICAPMsgAddr=0 1739MSICAPMsgCtrl=0 1740MSICAPMsgData=0 1741MSICAPMsgUpperAddr=0 1742MSICAPNextCapability=0 1743MSICAPPendingBits=0 1744MSIXCAPBaseOffset=0 1745MSIXCAPCapId=0 1746MSIXCAPNextCapability=0 1747MSIXMsgCtrl=0 1748MSIXPbaOffset=0 1749MSIXTableOffset=0 1750MaximumLatency=0 1751MinimumGrant=255 1752PMCAPBaseOffset=0 1753PMCAPCapId=0 1754PMCAPCapabilities=0 1755PMCAPCtrlStatus=0 1756PMCAPNextCapability=0 1757PXCAPBaseOffset=0 1758PXCAPCapId=0 1759PXCAPCapabilities=0 1760PXCAPDevCap2=0 1761PXCAPDevCapabilities=0 1762PXCAPDevCtrl=0 1763PXCAPDevCtrl2=0 1764PXCAPDevStatus=0 1765PXCAPLinkCap=0 1766PXCAPLinkCtrl=0 1767PXCAPLinkStatus=0 1768PXCAPNextCapability=0 1769ProgIF=0 1770Revision=0 1771Status=0 1772SubClassCode=0 1773SubsystemID=4104 1774SubsystemVendorID=32902 1775VendorID=32902
|
1710clk_domain=system.clk_domain
| 1776clk_domain=system.clk_domain
|
1711dvfs_handler=system.dvfs_handler
| 1777config_latency=20000
|
1712eventq_index=0
| 1778eventq_index=0
|
1713pio_addr=268496896 1714pio_latency=100000
| 1779fetch_comp_delay=10000 1780fetch_delay=10000 1781hardware_address=00:90:00:00:00:01 1782pci_bus=0 1783pci_dev=0 1784pci_func=0 1785phy_epid=896 1786phy_pid=680 1787pio_latency=30000 1788platform=system.realview 1789rx_desc_cache_size=64 1790rx_fifo_size=393216 1791rx_write_delay=0
|
1715system=system
| 1792system=system
|
| 1793tx_desc_cache_size=64 1794tx_fifo_size=393216 1795tx_read_delay=0 1796wb_comp_delay=10000 1797wb_delay=10000 1798config=system.iobus.master[26] 1799dma=system.iobus.slave[4]
|
1716pio=system.iobus.master[25] 1717
| 1800pio=system.iobus.master[25] 1801
|
1718[system.realview.flash_fake] 1719type=IsaFake 1720clk_domain=system.clk_domain
| 1802[system.realview.generic_timer] 1803type=GenericTimer
|
1721eventq_index=0
| 1804eventq_index=0
|
1722fake_mem=true 1723pio_addr=1073741824 1724pio_latency=100000 1725pio_size=536870912 1726ret_bad_addr=false 1727ret_data16=65535 1728ret_data32=4294967295 1729ret_data64=18446744073709551615 1730ret_data8=255
| 1805gic=system.realview.gic 1806int_num=29
|
1731system=system
| 1807system=system
|
1732update_data=false 1733warn_access= 1734pio=system.iobus.master[24]
| |
1735 1736[system.realview.gic] 1737type=Pl390 1738clk_domain=system.clk_domain
| 1808 1809[system.realview.gic] 1810type=Pl390 1811clk_domain=system.clk_domain
|
1739cpu_addr=520093952
| 1812cpu_addr=738205696
|
1740cpu_pio_delay=10000
| 1813cpu_pio_delay=10000
|
1741dist_addr=520097792
| 1814dist_addr=738201600
|
1742dist_pio_delay=10000 1743eventq_index=0 1744int_latency=10000 1745it_lines=128 1746msix_addr=0 1747platform=system.realview 1748system=system 1749pio=system.membus.master[2] 1750
| 1815dist_pio_delay=10000 1816eventq_index=0 1817int_latency=10000 1818it_lines=128 1819msix_addr=0 1820platform=system.realview 1821system=system 1822pio=system.membus.master[2] 1823
|
1751[system.realview.gpio0_fake] 1752type=AmbaFake 1753amba_id=0
| 1824[system.realview.hdlcd] 1825type=HDLcd 1826amba_id=1314816
|
1754clk_domain=system.clk_domain
| 1827clk_domain=system.clk_domain
|
| 1828enable_capture=true
|
1755eventq_index=0
| 1829eventq_index=0
|
1756ignore_access=false 1757pio_addr=268513280 1758pio_latency=100000
| 1830gic=system.realview.gic 1831int_num=117 1832pio_addr=721420288 1833pio_latency=10000 1834pixel_clock=7299
|
1759system=system
| 1835system=system
|
1760pio=system.iobus.master[16]
| 1836vnc=system.vncserver 1837dma=system.membus.slave[0] 1838pio=system.iobus.master[5]
|
1761
| 1839
|
1762[system.realview.gpio1_fake] 1763type=AmbaFake 1764amba_id=0
| 1840[system.realview.ide] 1841type=IdeController 1842BAR0=1 1843BAR0LegacyIO=false 1844BAR0Size=8 1845BAR1=1 1846BAR1LegacyIO=false 1847BAR1Size=4 1848BAR2=1 1849BAR2LegacyIO=false 1850BAR2Size=8 1851BAR3=1 1852BAR3LegacyIO=false 1853BAR3Size=4 1854BAR4=1 1855BAR4LegacyIO=false 1856BAR4Size=16 1857BAR5=1 1858BAR5LegacyIO=false 1859BAR5Size=0 1860BIST=0 1861CacheLineSize=0 1862CapabilityPtr=0 1863CardbusCIS=0 1864ClassCode=1 1865Command=0 1866DeviceID=28945 1867ExpansionROM=0 1868HeaderType=0 1869InterruptLine=2 1870InterruptPin=2 1871LatencyTimer=0 1872LegacyIOBase=0 1873MSICAPBaseOffset=0 1874MSICAPCapId=0 1875MSICAPMaskBits=0 1876MSICAPMsgAddr=0 1877MSICAPMsgCtrl=0 1878MSICAPMsgData=0 1879MSICAPMsgUpperAddr=0 1880MSICAPNextCapability=0 1881MSICAPPendingBits=0 1882MSIXCAPBaseOffset=0 1883MSIXCAPCapId=0 1884MSIXCAPNextCapability=0 1885MSIXMsgCtrl=0 1886MSIXPbaOffset=0 1887MSIXTableOffset=0 1888MaximumLatency=0 1889MinimumGrant=0 1890PMCAPBaseOffset=0 1891PMCAPCapId=0 1892PMCAPCapabilities=0 1893PMCAPCtrlStatus=0 1894PMCAPNextCapability=0 1895PXCAPBaseOffset=0 1896PXCAPCapId=0 1897PXCAPCapabilities=0 1898PXCAPDevCap2=0 1899PXCAPDevCapabilities=0 1900PXCAPDevCtrl=0 1901PXCAPDevCtrl2=0 1902PXCAPDevStatus=0 1903PXCAPLinkCap=0 1904PXCAPLinkCtrl=0 1905PXCAPLinkStatus=0 1906PXCAPNextCapability=0 1907ProgIF=133 1908Revision=0 1909Status=640 1910SubClassCode=1 1911SubsystemID=0 1912SubsystemVendorID=0 1913VendorID=32902
|
1765clk_domain=system.clk_domain
| 1914clk_domain=system.clk_domain
|
| 1915config_latency=20000 1916ctrl_offset=0 1917disks=system.cf0
|
1766eventq_index=0
| 1918eventq_index=0
|
1767ignore_access=false 1768pio_addr=268517376 1769pio_latency=100000
| 1919io_shift=0 1920pci_bus=0 1921pci_dev=1 1922pci_func=0 1923pio_latency=30000 1924platform=system.realview
|
1770system=system
| 1925system=system
|
1771pio=system.iobus.master[17]
| 1926config=system.iobus.master[24] 1927dma=system.iobus.slave[3] 1928pio=system.iobus.master[23]
|
1772
| 1929
|
1773[system.realview.gpio2_fake] 1774type=AmbaFake 1775amba_id=0 1776clk_domain=system.clk_domain 1777eventq_index=0 1778ignore_access=false 1779pio_addr=268521472 1780pio_latency=100000 1781system=system 1782pio=system.iobus.master[18] 1783
| |
1784[system.realview.kmi0] 1785type=Pl050 1786amba_id=1314896 1787clk_domain=system.clk_domain 1788eventq_index=0 1789gic=system.realview.gic 1790int_delay=1000000
| 1930[system.realview.kmi0] 1931type=Pl050 1932amba_id=1314896 1933clk_domain=system.clk_domain 1934eventq_index=0 1935gic=system.realview.gic 1936int_delay=1000000
|
1791int_num=52
| 1937int_num=44
|
1792is_mouse=false
| 1938is_mouse=false
|
1793pio_addr=268460032
| 1939pio_addr=470155264
|
1794pio_latency=100000 1795system=system 1796vnc=system.vncserver
| 1940pio_latency=100000 1941system=system 1942vnc=system.vncserver
|
1797pio=system.iobus.master[5]
| 1943pio=system.iobus.master[6]
|
1798 1799[system.realview.kmi1] 1800type=Pl050 1801amba_id=1314896 1802clk_domain=system.clk_domain 1803eventq_index=0 1804gic=system.realview.gic 1805int_delay=1000000
| 1944 1945[system.realview.kmi1] 1946type=Pl050 1947amba_id=1314896 1948clk_domain=system.clk_domain 1949eventq_index=0 1950gic=system.realview.gic 1951int_delay=1000000
|
1806int_num=53
| 1952int_num=45
|
1807is_mouse=true
| 1953is_mouse=true
|
1808pio_addr=268464128
| 1954pio_addr=470220800
|
1809pio_latency=100000 1810system=system 1811vnc=system.vncserver
| 1955pio_latency=100000 1956system=system 1957vnc=system.vncserver
|
1812pio=system.iobus.master[6]
| 1958pio=system.iobus.master[7]
|
1813 1814[system.realview.l2x0_fake] 1815type=IsaFake 1816clk_domain=system.clk_domain 1817eventq_index=0 1818fake_mem=false
| 1959 1960[system.realview.l2x0_fake] 1961type=IsaFake 1962clk_domain=system.clk_domain 1963eventq_index=0 1964fake_mem=false
|
1819pio_addr=520101888
| 1965pio_addr=739246080
|
1820pio_latency=100000 1821pio_size=4095 1822ret_bad_addr=false 1823ret_data16=65535 1824ret_data32=4294967295 1825ret_data64=18446744073709551615 1826ret_data8=255 1827system=system 1828update_data=false 1829warn_access=
| 1966pio_latency=100000 1967pio_size=4095 1968ret_bad_addr=false 1969ret_data16=65535 1970ret_data32=4294967295 1971ret_data64=18446744073709551615 1972ret_data8=255 1973system=system 1974update_data=false 1975warn_access=
|
1830pio=system.membus.master[3]
| 1976pio=system.iobus.master[12]
|
1831
| 1977
|
| 1978[system.realview.lan_fake] 1979type=IsaFake 1980clk_domain=system.clk_domain 1981eventq_index=0 1982fake_mem=false 1983pio_addr=436207616 1984pio_latency=100000 1985pio_size=65535 1986ret_bad_addr=false 1987ret_data16=65535 1988ret_data32=4294967295 1989ret_data64=18446744073709551615 1990ret_data8=255 1991system=system 1992update_data=false 1993warn_access= 1994pio=system.iobus.master[19] 1995
|
1832[system.realview.local_cpu_timer] 1833type=CpuLocalTimer 1834clk_domain=system.clk_domain 1835eventq_index=0 1836gic=system.realview.gic 1837int_num_timer=29 1838int_num_watchdog=30
| 1996[system.realview.local_cpu_timer] 1997type=CpuLocalTimer 1998clk_domain=system.clk_domain 1999eventq_index=0 2000gic=system.realview.gic 2001int_num_timer=29 2002int_num_watchdog=30
|
1839pio_addr=520095232
| 2003pio_addr=738721792
|
1840pio_latency=100000 1841system=system
| 2004pio_latency=100000 2005system=system
|
1842pio=system.membus.master[5]
| 2006pio=system.membus.master[3]
|
1843 1844[system.realview.mmc_fake] 1845type=AmbaFake 1846amba_id=0 1847clk_domain=system.clk_domain 1848eventq_index=0 1849ignore_access=false
| 2007 2008[system.realview.mmc_fake] 2009type=AmbaFake 2010amba_id=0 2011clk_domain=system.clk_domain 2012eventq_index=0 2013ignore_access=false
|
1850pio_addr=268455936
| 2014pio_addr=470089728
|
1851pio_latency=100000 1852system=system
| 2015pio_latency=100000 2016system=system
|
1853pio=system.iobus.master[22]
| 2017pio=system.iobus.master[21]
|
1854 1855[system.realview.nvmem] 1856type=SimpleMemory 1857bandwidth=73.000000 1858clk_domain=system.clk_domain 1859conf_table_reported=false 1860eventq_index=0 1861in_addr_map=true 1862latency=30000 1863latency_var=0 1864null=false
| 2018 2019[system.realview.nvmem] 2020type=SimpleMemory 2021bandwidth=73.000000 2022clk_domain=system.clk_domain 2023conf_table_reported=false 2024eventq_index=0 2025in_addr_map=true 2026latency=30000 2027latency_var=0 2028null=false
|
1865range=2147483648:2214592511
| 2029range=0:67108863
|
1866port=system.membus.master[1] 1867
| 2030port=system.membus.master[1] 2031
|
| 2032[system.realview.pciconfig] 2033type=PciConfigAll 2034bus=0 2035clk_domain=system.clk_domain 2036eventq_index=0 2037pio_addr=0 2038pio_latency=30000 2039platform=system.realview 2040size=268435456 2041system=system 2042pio=system.iobus.default 2043
|
1868[system.realview.realview_io] 1869type=RealViewCtrl 1870clk_domain=system.clk_domain 1871eventq_index=0
| 2044[system.realview.realview_io] 2045type=RealViewCtrl 2046clk_domain=system.clk_domain 2047eventq_index=0
|
1872idreg=0 1873pio_addr=268435456
| 2048idreg=35979264 2049pio_addr=469827584
|
1874pio_latency=100000
| 2050pio_latency=100000
|
1875proc_id0=201326592 1876proc_id1=201327138
| 2051proc_id0=335544320 2052proc_id1=335544320
|
1877system=system 1878pio=system.iobus.master[1] 1879 1880[system.realview.rtc] 1881type=PL031 1882amba_id=3412017 1883clk_domain=system.clk_domain 1884eventq_index=0 1885gic=system.realview.gic 1886int_delay=100000
| 2053system=system 2054pio=system.iobus.master[1] 2055 2056[system.realview.rtc] 2057type=PL031 2058amba_id=3412017 2059clk_domain=system.clk_domain 2060eventq_index=0 2061gic=system.realview.gic 2062int_delay=100000
|
1887int_num=42 1888pio_addr=268529664
| 2063int_num=36 2064pio_addr=471269376
|
1889pio_latency=100000 1890system=system 1891time=Thu Jan 1 00:00:00 2009
| 2065pio_latency=100000 2066system=system 2067time=Thu Jan 1 00:00:00 2009
|
1892pio=system.iobus.master[23]
| 2068pio=system.iobus.master[10]
|
1893
| 2069
|
1894[system.realview.sci_fake] 1895type=AmbaFake 1896amba_id=0 1897clk_domain=system.clk_domain 1898eventq_index=0 1899ignore_access=false 1900pio_addr=268492800 1901pio_latency=100000 1902system=system 1903pio=system.iobus.master[20] 1904 1905[system.realview.smc_fake] 1906type=AmbaFake 1907amba_id=0 1908clk_domain=system.clk_domain 1909eventq_index=0 1910ignore_access=false 1911pio_addr=269357056 1912pio_latency=100000 1913system=system 1914pio=system.iobus.master[13] 1915
| |
1916[system.realview.sp810_fake] 1917type=AmbaFake 1918amba_id=0 1919clk_domain=system.clk_domain 1920eventq_index=0 1921ignore_access=true
| 2070[system.realview.sp810_fake] 2071type=AmbaFake 2072amba_id=0 2073clk_domain=system.clk_domain 2074eventq_index=0 2075ignore_access=true
|
1922pio_addr=268439552
| 2076pio_addr=469893120
|
1923pio_latency=100000 1924system=system
| 2077pio_latency=100000 2078system=system
|
1925pio=system.iobus.master[14]
| 2079pio=system.iobus.master[16]
|
1926
| 2080
|
1927[system.realview.ssp_fake] 1928type=AmbaFake 1929amba_id=0 1930clk_domain=system.clk_domain 1931eventq_index=0 1932ignore_access=false 1933pio_addr=268488704 1934pio_latency=100000 1935system=system 1936pio=system.iobus.master[19] 1937
| |
1938[system.realview.timer0] 1939type=Sp804 1940amba_id=1316868 1941clk_domain=system.clk_domain 1942clock0=1000000 1943clock1=1000000 1944eventq_index=0 1945gic=system.realview.gic
| 2081[system.realview.timer0] 2082type=Sp804 2083amba_id=1316868 2084clk_domain=system.clk_domain 2085clock0=1000000 2086clock1=1000000 2087eventq_index=0 2088gic=system.realview.gic
|
1946int_num0=36 1947int_num1=36 1948pio_addr=268505088
| 2089int_num0=34 2090int_num1=34 2091pio_addr=470876160
|
1949pio_latency=100000 1950system=system 1951pio=system.iobus.master[2] 1952 1953[system.realview.timer1] 1954type=Sp804 1955amba_id=1316868 1956clk_domain=system.clk_domain 1957clock0=1000000 1958clock1=1000000 1959eventq_index=0 1960gic=system.realview.gic
| 2092pio_latency=100000 2093system=system 2094pio=system.iobus.master[2] 2095 2096[system.realview.timer1] 2097type=Sp804 2098amba_id=1316868 2099clk_domain=system.clk_domain 2100clock0=1000000 2101clock1=1000000 2102eventq_index=0 2103gic=system.realview.gic
|
1961int_num0=37 1962int_num1=37 1963pio_addr=268509184
| 2104int_num0=35 2105int_num1=35 2106pio_addr=470941696
|
1964pio_latency=100000 1965system=system 1966pio=system.iobus.master[3] 1967 1968[system.realview.uart] 1969type=Pl011 1970clk_domain=system.clk_domain 1971end_on_eot=false 1972eventq_index=0 1973gic=system.realview.gic 1974int_delay=100000
| 2107pio_latency=100000 2108system=system 2109pio=system.iobus.master[3] 2110 2111[system.realview.uart] 2112type=Pl011 2113clk_domain=system.clk_domain 2114end_on_eot=false 2115eventq_index=0 2116gic=system.realview.gic 2117int_delay=100000
|
1975int_num=44 1976pio_addr=268472320
| 2118int_num=37 2119pio_addr=470351872
|
1977pio_latency=100000 1978platform=system.realview 1979system=system 1980terminal=system.terminal 1981pio=system.iobus.master[0] 1982 1983[system.realview.uart1_fake] 1984type=AmbaFake 1985amba_id=0 1986clk_domain=system.clk_domain 1987eventq_index=0 1988ignore_access=false
| 2120pio_latency=100000 2121platform=system.realview 2122system=system 2123terminal=system.terminal 2124pio=system.iobus.master[0] 2125 2126[system.realview.uart1_fake] 2127type=AmbaFake 2128amba_id=0 2129clk_domain=system.clk_domain 2130eventq_index=0 2131ignore_access=false
|
1989pio_addr=268476416
| 2132pio_addr=470417408
|
1990pio_latency=100000 1991system=system
| 2133pio_latency=100000 2134system=system
|
1992pio=system.iobus.master[10]
| 2135pio=system.iobus.master[13]
|
1993 1994[system.realview.uart2_fake] 1995type=AmbaFake 1996amba_id=0 1997clk_domain=system.clk_domain 1998eventq_index=0 1999ignore_access=false
| 2136 2137[system.realview.uart2_fake] 2138type=AmbaFake 2139amba_id=0 2140clk_domain=system.clk_domain 2141eventq_index=0 2142ignore_access=false
|
2000pio_addr=268480512
| 2143pio_addr=470482944
|
2001pio_latency=100000 2002system=system
| 2144pio_latency=100000 2145system=system
|
2003pio=system.iobus.master[11]
| 2146pio=system.iobus.master[14]
|
2004 2005[system.realview.uart3_fake] 2006type=AmbaFake 2007amba_id=0 2008clk_domain=system.clk_domain 2009eventq_index=0 2010ignore_access=false
| 2147 2148[system.realview.uart3_fake] 2149type=AmbaFake 2150amba_id=0 2151clk_domain=system.clk_domain 2152eventq_index=0 2153ignore_access=false
|
2011pio_addr=268484608
| 2154pio_addr=470548480
|
2012pio_latency=100000 2013system=system
| 2155pio_latency=100000 2156system=system
|
2014pio=system.iobus.master[12]
| 2157pio=system.iobus.master[15]
|
2015
| 2158
|
| 2159[system.realview.usb_fake] 2160type=IsaFake 2161clk_domain=system.clk_domain 2162eventq_index=0 2163fake_mem=false 2164pio_addr=452984832 2165pio_latency=100000 2166pio_size=131071 2167ret_bad_addr=false 2168ret_data16=65535 2169ret_data32=4294967295 2170ret_data64=18446744073709551615 2171ret_data8=255 2172system=system 2173update_data=false 2174warn_access= 2175pio=system.iobus.master[20] 2176 2177[system.realview.vgic] 2178type=VGic 2179clk_domain=system.clk_domain 2180eventq_index=0 2181gic=system.realview.gic 2182hv_addr=738213888 2183pio_delay=10000 2184platform=system.realview 2185ppint=25 2186system=system 2187vcpu_addr=738222080 2188pio=system.membus.master[4] 2189 2190[system.realview.vram] 2191type=SimpleMemory 2192bandwidth=73.000000 2193clk_domain=system.clk_domain 2194conf_table_reported=false 2195eventq_index=0 2196in_addr_map=true 2197latency=30000 2198latency_var=0 2199null=false 2200range=402653184:436207615 2201port=system.iobus.master[11] 2202
|
2016[system.realview.watchdog_fake] 2017type=AmbaFake 2018amba_id=0 2019clk_domain=system.clk_domain 2020eventq_index=0 2021ignore_access=false
| 2203[system.realview.watchdog_fake] 2204type=AmbaFake 2205amba_id=0 2206clk_domain=system.clk_domain 2207eventq_index=0 2208ignore_access=false
|
2022pio_addr=268500992
| 2209pio_addr=470745088
|
2023pio_latency=100000 2024system=system
| 2210pio_latency=100000 2211system=system
|
2025pio=system.iobus.master[15]
| 2212pio=system.iobus.master[17]
|
2026 2027[system.terminal] 2028type=Terminal 2029eventq_index=0 2030intr_control=system.intrctrl 2031number=0 2032output=true 2033port=3456 2034 2035[system.toL2Bus] 2036type=CoherentXBar 2037clk_domain=system.cpu_clk_domain 2038eventq_index=0 2039header_cycles=1 2040snoop_filter=Null 2041system=system 2042use_default_range=false 2043width=8 2044master=system.l2c.cpu_side 2045slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side 2046 2047[system.vncserver] 2048type=VncServer 2049eventq_index=0 2050frame_capture=false 2051number=0 2052port=5900 2053 2054[system.voltage_domain] 2055type=VoltageDomain 2056eventq_index=0 2057voltage=1.000000 2058
| 2213 2214[system.terminal] 2215type=Terminal 2216eventq_index=0 2217intr_control=system.intrctrl 2218number=0 2219output=true 2220port=3456 2221 2222[system.toL2Bus] 2223type=CoherentXBar 2224clk_domain=system.cpu_clk_domain 2225eventq_index=0 2226header_cycles=1 2227snoop_filter=Null 2228system=system 2229use_default_range=false 2230width=8 2231master=system.l2c.cpu_side 2232slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side 2233 2234[system.vncserver] 2235type=VncServer 2236eventq_index=0 2237frame_capture=false 2238number=0 2239port=5900 2240 2241[system.voltage_domain] 2242type=VoltageDomain 2243eventq_index=0 2244voltage=1.000000 2245
|