Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini

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config.ini (10038:7eccd14e2610)	config.ini (10242:cb4e86c17767)
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxArmSystem 13children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain 14atags_addr=256	1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxArmSystem 13children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain 14atags_addr=256
15boot_loader=/dist/binaries/boot.arm 16boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1	15boot_loader=/home/stever/m5/m5_system_2.0b3/binaries/boot.arm 16boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
17boot_release_addr=65528 18cache_line_size=64 19clk_domain=system.clk_domain 20dtb_filename= 21early_kernel_symbols=false 22enable_context_switch_stats_dump=false 23eventq_index=0 24flags_addr=268435504 25gic_cpu_addr=520093952 26have_generic_timer=false 27have_large_asid_64=false 28have_lpae=false 29have_security=false 30have_virtualization=false 31highest_el_is_64=false 32init_param=0	17boot_release_addr=65528 18cache_line_size=64 19clk_domain=system.clk_domain 20dtb_filename= 21early_kernel_symbols=false 22enable_context_switch_stats_dump=false 23eventq_index=0 24flags_addr=268435504 25gic_cpu_addr=520093952 26have_generic_timer=false 27have_large_asid_64=false 28have_lpae=false 29have_security=false 30have_virtualization=false 31highest_el_is_64=false 32init_param=0
33kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8	33kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8
34load_addr_mask=268435455 35load_offset=0 36machine_type=RealView_PBX 37mem_mode=timing 38mem_ranges=0:134217727 39memories=system.physmem system.realview.nvmem 40multi_proc=true 41num_work_ids=16 42panic_on_oops=true 43panic_on_panic=true 44phys_addr_range_64=40	34load_addr_mask=268435455 35load_offset=0 36machine_type=RealView_PBX 37mem_mode=timing 38mem_ranges=0:134217727 39memories=system.physmem system.realview.nvmem 40multi_proc=true 41num_work_ids=16 42panic_on_oops=true 43panic_on_panic=true 44phys_addr_range_64=40
45readfile=tests/halt.sh	45readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
46reset_addr_64=0 47symbolfile= 48work_begin_ckpt_count=0 49work_begin_cpu_id_exit=-1 50work_begin_exit_count=0 51work_cpus_ckpt_count=0 52work_end_ckpt_count=0 53work_end_exit_count=0 54work_item_id=-1 55system_port=system.membus.slave[0] 56 57[system.bridge] 58type=Bridge 59clk_domain=system.clk_domain 60delay=50000 61eventq_index=0 62ranges=268435456:520093695 1073741824:1610612735 63req_size=16 64resp_size=16 65master=system.iobus.slave[0] 66slave=system.membus.master[0] 67 68[system.cf0] 69type=IdeDisk 70children=image 71delay=1000000 72driveID=master 73eventq_index=0 74image=system.cf0.image 75 76[system.cf0.image] 77type=CowDiskImage 78children=child 79child=system.cf0.image.child 80eventq_index=0 81image_file= 82read_only=false 83table_size=65536 84 85[system.cf0.image.child] 86type=RawDiskImage 87eventq_index=0	46reset_addr_64=0 47symbolfile= 48work_begin_ckpt_count=0 49work_begin_cpu_id_exit=-1 50work_begin_exit_count=0 51work_cpus_ckpt_count=0 52work_end_ckpt_count=0 53work_end_exit_count=0 54work_item_id=-1 55system_port=system.membus.slave[0] 56 57[system.bridge] 58type=Bridge 59clk_domain=system.clk_domain 60delay=50000 61eventq_index=0 62ranges=268435456:520093695 1073741824:1610612735 63req_size=16 64resp_size=16 65master=system.iobus.slave[0] 66slave=system.membus.master[0] 67 68[system.cf0] 69type=IdeDisk 70children=image 71delay=1000000 72driveID=master 73eventq_index=0 74image=system.cf0.image 75 76[system.cf0.image] 77type=CowDiskImage 78children=child 79child=system.cf0.image.child 80eventq_index=0 81image_file= 82read_only=false 83table_size=65536 84 85[system.cf0.image.child] 86type=RawDiskImage 87eventq_index=0
88image_file=/dist/disks/linux-arm-ael.img	88image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-arm-ael.img
89read_only=true 90 91[system.clk_domain] 92type=SrcClockDomain 93clock=1000 94eventq_index=0 95voltage_domain=system.voltage_domain 96 97[system.cpu0] 98type=DerivO3CPU 99children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer 100LFSTSize=1024 101LQEntries=32 102LSQCheckLoads=true 103LSQDepCheckShift=4 104SQEntries=32 105SSITSize=1024 106activity=0 107backComSize=5 108branchPred=system.cpu0.branchPred 109cachePorts=200 110checker=Null 111clk_domain=system.cpu_clk_domain 112commitToDecodeDelay=1 113commitToFetchDelay=1 114commitToIEWDelay=1 115commitToRenameDelay=1 116commitWidth=8 117cpu_id=0 118decodeToFetchDelay=1 119decodeToRenameDelay=1 120decodeWidth=8 121dispatchWidth=8 122do_checkpoint_insts=true 123do_quiesce=true 124do_statistics_insts=true 125dstage2_mmu=system.cpu0.dstage2_mmu 126dtb=system.cpu0.dtb 127eventq_index=0 128fetchBufferSize=64 129fetchToDecodeDelay=1 130fetchTrapLatency=1 131fetchWidth=8 132forwardComSize=5 133fuPool=system.cpu0.fuPool 134function_trace=false 135function_trace_start=0 136iewToCommitDelay=1 137iewToDecodeDelay=1 138iewToFetchDelay=1 139iewToRenameDelay=1 140interrupts=system.cpu0.interrupts 141isa=system.cpu0.isa 142issueToExecuteDelay=1 143issueWidth=8 144istage2_mmu=system.cpu0.istage2_mmu 145itb=system.cpu0.itb 146max_insts_all_threads=0 147max_insts_any_thread=0 148max_loads_all_threads=0 149max_loads_any_thread=0 150needsTSO=false 151numIQEntries=64 152numPhysCCRegs=0 153numPhysFloatRegs=256 154numPhysIntRegs=256 155numROBEntries=192 156numRobs=1 157numThreads=1 158profile=0 159progress_interval=0 160renameToDecodeDelay=1 161renameToFetchDelay=1 162renameToIEWDelay=2 163renameToROBDelay=1 164renameWidth=8 165simpoint_start_insts= 166smtCommitPolicy=RoundRobin 167smtFetchPolicy=SingleThread 168smtIQPolicy=Partitioned 169smtIQThreshold=100 170smtLSQPolicy=Partitioned 171smtLSQThreshold=100 172smtNumFetchingThreads=1 173smtROBPolicy=Partitioned 174smtROBThreshold=100	89read_only=true 90 91[system.clk_domain] 92type=SrcClockDomain 93clock=1000 94eventq_index=0 95voltage_domain=system.voltage_domain 96 97[system.cpu0] 98type=DerivO3CPU 99children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer 100LFSTSize=1024 101LQEntries=32 102LSQCheckLoads=true 103LSQDepCheckShift=4 104SQEntries=32 105SSITSize=1024 106activity=0 107backComSize=5 108branchPred=system.cpu0.branchPred 109cachePorts=200 110checker=Null 111clk_domain=system.cpu_clk_domain 112commitToDecodeDelay=1 113commitToFetchDelay=1 114commitToIEWDelay=1 115commitToRenameDelay=1 116commitWidth=8 117cpu_id=0 118decodeToFetchDelay=1 119decodeToRenameDelay=1 120decodeWidth=8 121dispatchWidth=8 122do_checkpoint_insts=true 123do_quiesce=true 124do_statistics_insts=true 125dstage2_mmu=system.cpu0.dstage2_mmu 126dtb=system.cpu0.dtb 127eventq_index=0 128fetchBufferSize=64 129fetchToDecodeDelay=1 130fetchTrapLatency=1 131fetchWidth=8 132forwardComSize=5 133fuPool=system.cpu0.fuPool 134function_trace=false 135function_trace_start=0 136iewToCommitDelay=1 137iewToDecodeDelay=1 138iewToFetchDelay=1 139iewToRenameDelay=1 140interrupts=system.cpu0.interrupts 141isa=system.cpu0.isa 142issueToExecuteDelay=1 143issueWidth=8 144istage2_mmu=system.cpu0.istage2_mmu 145itb=system.cpu0.itb 146max_insts_all_threads=0 147max_insts_any_thread=0 148max_loads_all_threads=0 149max_loads_any_thread=0 150needsTSO=false 151numIQEntries=64 152numPhysCCRegs=0 153numPhysFloatRegs=256 154numPhysIntRegs=256 155numROBEntries=192 156numRobs=1 157numThreads=1 158profile=0 159progress_interval=0 160renameToDecodeDelay=1 161renameToFetchDelay=1 162renameToIEWDelay=2 163renameToROBDelay=1 164renameWidth=8 165simpoint_start_insts= 166smtCommitPolicy=RoundRobin 167smtFetchPolicy=SingleThread 168smtIQPolicy=Partitioned 169smtIQThreshold=100 170smtLSQPolicy=Partitioned 171smtLSQThreshold=100 172smtNumFetchingThreads=1 173smtROBPolicy=Partitioned 174smtROBThreshold=100
	175socket_id=0
175squashWidth=8 176store_set_clear_period=250000 177switched_out=false 178system=system 179tracer=system.cpu0.tracer 180trapLatency=13 181wbDepth=1 182wbWidth=8 183workload= 184dcache_port=system.cpu0.dcache.cpu_side 185icache_port=system.cpu0.icache.cpu_side 186 187[system.cpu0.branchPred] 188type=BranchPredictor 189BTBEntries=4096 190BTBTagSize=16 191RASSize=16 192choiceCtrBits=2 193choicePredictorSize=8192 194eventq_index=0 195globalCtrBits=2 196globalPredictorSize=8192 197instShiftAmt=2 198localCtrBits=2 199localHistoryTableSize=2048 200localPredictorSize=2048 201numThreads=1 202predType=tournament 203 204[system.cpu0.dcache] 205type=BaseCache 206children=tags 207addr_ranges=0:18446744073709551615 208assoc=4 209clk_domain=system.cpu_clk_domain 210eventq_index=0 211forward_snoops=true 212hit_latency=2 213is_top_level=true 214max_miss_count=0 215mshrs=4 216prefetch_on_access=false 217prefetcher=Null 218response_latency=2 219sequential_access=false 220size=32768 221system=system 222tags=system.cpu0.dcache.tags 223tgts_per_mshr=20 224two_queue=false 225write_buffers=8 226cpu_side=system.cpu0.dcache_port 227mem_side=system.toL2Bus.slave[1] 228 229[system.cpu0.dcache.tags] 230type=LRU 231assoc=4 232block_size=64 233clk_domain=system.cpu_clk_domain 234eventq_index=0 235hit_latency=2 236sequential_access=false 237size=32768 238 239[system.cpu0.dstage2_mmu] 240type=ArmStage2MMU 241children=stage2_tlb 242eventq_index=0 243stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb 244tlb=system.cpu0.dtb 245 246[system.cpu0.dstage2_mmu.stage2_tlb] 247type=ArmTLB 248children=walker 249eventq_index=0 250is_stage2=true 251size=32 252walker=system.cpu0.dstage2_mmu.stage2_tlb.walker 253 254[system.cpu0.dstage2_mmu.stage2_tlb.walker] 255type=ArmTableWalker 256clk_domain=system.cpu_clk_domain 257eventq_index=0 258is_stage2=true 259num_squash_per_cycle=2 260sys=system 261port=system.toL2Bus.slave[5] 262 263[system.cpu0.dtb] 264type=ArmTLB 265children=walker 266eventq_index=0 267is_stage2=false 268size=64 269walker=system.cpu0.dtb.walker 270 271[system.cpu0.dtb.walker] 272type=ArmTableWalker 273clk_domain=system.cpu_clk_domain 274eventq_index=0 275is_stage2=false 276num_squash_per_cycle=2 277sys=system 278port=system.toL2Bus.slave[3] 279 280[system.cpu0.fuPool] 281type=FUPool 282children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 283FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 284eventq_index=0 285 286[system.cpu0.fuPool.FUList0] 287type=FUDesc 288children=opList 289count=6 290eventq_index=0 291opList=system.cpu0.fuPool.FUList0.opList 292 293[system.cpu0.fuPool.FUList0.opList] 294type=OpDesc 295eventq_index=0 296issueLat=1 297opClass=IntAlu 298opLat=1 299 300[system.cpu0.fuPool.FUList1] 301type=FUDesc 302children=opList0 opList1 303count=2 304eventq_index=0 305opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 306 307[system.cpu0.fuPool.FUList1.opList0] 308type=OpDesc 309eventq_index=0 310issueLat=1 311opClass=IntMult 312opLat=3 313 314[system.cpu0.fuPool.FUList1.opList1] 315type=OpDesc 316eventq_index=0 317issueLat=19 318opClass=IntDiv 319opLat=20 320 321[system.cpu0.fuPool.FUList2] 322type=FUDesc 323children=opList0 opList1 opList2 324count=4 325eventq_index=0 326opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 327 328[system.cpu0.fuPool.FUList2.opList0] 329type=OpDesc 330eventq_index=0 331issueLat=1 332opClass=FloatAdd 333opLat=2 334 335[system.cpu0.fuPool.FUList2.opList1] 336type=OpDesc 337eventq_index=0 338issueLat=1 339opClass=FloatCmp 340opLat=2 341 342[system.cpu0.fuPool.FUList2.opList2] 343type=OpDesc 344eventq_index=0 345issueLat=1 346opClass=FloatCvt 347opLat=2 348 349[system.cpu0.fuPool.FUList3] 350type=FUDesc 351children=opList0 opList1 opList2 352count=2 353eventq_index=0 354opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 355 356[system.cpu0.fuPool.FUList3.opList0] 357type=OpDesc 358eventq_index=0 359issueLat=1 360opClass=FloatMult 361opLat=4 362 363[system.cpu0.fuPool.FUList3.opList1] 364type=OpDesc 365eventq_index=0 366issueLat=12 367opClass=FloatDiv 368opLat=12 369 370[system.cpu0.fuPool.FUList3.opList2] 371type=OpDesc 372eventq_index=0 373issueLat=24 374opClass=FloatSqrt 375opLat=24 376 377[system.cpu0.fuPool.FUList4] 378type=FUDesc 379children=opList 380count=0 381eventq_index=0 382opList=system.cpu0.fuPool.FUList4.opList 383 384[system.cpu0.fuPool.FUList4.opList] 385type=OpDesc 386eventq_index=0 387issueLat=1 388opClass=MemRead 389opLat=1 390 391[system.cpu0.fuPool.FUList5] 392type=FUDesc 393children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 394count=4 395eventq_index=0 396opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 397 398[system.cpu0.fuPool.FUList5.opList00] 399type=OpDesc 400eventq_index=0 401issueLat=1 402opClass=SimdAdd 403opLat=1 404 405[system.cpu0.fuPool.FUList5.opList01] 406type=OpDesc 407eventq_index=0 408issueLat=1 409opClass=SimdAddAcc 410opLat=1 411 412[system.cpu0.fuPool.FUList5.opList02] 413type=OpDesc 414eventq_index=0 415issueLat=1 416opClass=SimdAlu 417opLat=1 418 419[system.cpu0.fuPool.FUList5.opList03] 420type=OpDesc 421eventq_index=0 422issueLat=1 423opClass=SimdCmp 424opLat=1 425 426[system.cpu0.fuPool.FUList5.opList04] 427type=OpDesc 428eventq_index=0 429issueLat=1 430opClass=SimdCvt 431opLat=1 432 433[system.cpu0.fuPool.FUList5.opList05] 434type=OpDesc 435eventq_index=0 436issueLat=1 437opClass=SimdMisc 438opLat=1 439 440[system.cpu0.fuPool.FUList5.opList06] 441type=OpDesc 442eventq_index=0 443issueLat=1 444opClass=SimdMult 445opLat=1 446 447[system.cpu0.fuPool.FUList5.opList07] 448type=OpDesc 449eventq_index=0 450issueLat=1 451opClass=SimdMultAcc 452opLat=1 453 454[system.cpu0.fuPool.FUList5.opList08] 455type=OpDesc 456eventq_index=0 457issueLat=1 458opClass=SimdShift 459opLat=1 460 461[system.cpu0.fuPool.FUList5.opList09] 462type=OpDesc 463eventq_index=0 464issueLat=1 465opClass=SimdShiftAcc 466opLat=1 467 468[system.cpu0.fuPool.FUList5.opList10] 469type=OpDesc 470eventq_index=0 471issueLat=1 472opClass=SimdSqrt 473opLat=1 474 475[system.cpu0.fuPool.FUList5.opList11] 476type=OpDesc 477eventq_index=0 478issueLat=1 479opClass=SimdFloatAdd 480opLat=1 481 482[system.cpu0.fuPool.FUList5.opList12] 483type=OpDesc 484eventq_index=0 485issueLat=1 486opClass=SimdFloatAlu 487opLat=1 488 489[system.cpu0.fuPool.FUList5.opList13] 490type=OpDesc 491eventq_index=0 492issueLat=1 493opClass=SimdFloatCmp 494opLat=1 495 496[system.cpu0.fuPool.FUList5.opList14] 497type=OpDesc 498eventq_index=0 499issueLat=1 500opClass=SimdFloatCvt 501opLat=1 502 503[system.cpu0.fuPool.FUList5.opList15] 504type=OpDesc 505eventq_index=0 506issueLat=1 507opClass=SimdFloatDiv 508opLat=1 509 510[system.cpu0.fuPool.FUList5.opList16] 511type=OpDesc 512eventq_index=0 513issueLat=1 514opClass=SimdFloatMisc 515opLat=1 516 517[system.cpu0.fuPool.FUList5.opList17] 518type=OpDesc 519eventq_index=0 520issueLat=1 521opClass=SimdFloatMult 522opLat=1 523 524[system.cpu0.fuPool.FUList5.opList18] 525type=OpDesc 526eventq_index=0 527issueLat=1 528opClass=SimdFloatMultAcc 529opLat=1 530 531[system.cpu0.fuPool.FUList5.opList19] 532type=OpDesc 533eventq_index=0 534issueLat=1 535opClass=SimdFloatSqrt 536opLat=1 537 538[system.cpu0.fuPool.FUList6] 539type=FUDesc 540children=opList 541count=0 542eventq_index=0 543opList=system.cpu0.fuPool.FUList6.opList 544 545[system.cpu0.fuPool.FUList6.opList] 546type=OpDesc 547eventq_index=0 548issueLat=1 549opClass=MemWrite 550opLat=1 551 552[system.cpu0.fuPool.FUList7] 553type=FUDesc 554children=opList0 opList1 555count=4 556eventq_index=0 557opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 558 559[system.cpu0.fuPool.FUList7.opList0] 560type=OpDesc 561eventq_index=0 562issueLat=1 563opClass=MemRead 564opLat=1 565 566[system.cpu0.fuPool.FUList7.opList1] 567type=OpDesc 568eventq_index=0 569issueLat=1 570opClass=MemWrite 571opLat=1 572 573[system.cpu0.fuPool.FUList8] 574type=FUDesc 575children=opList 576count=1 577eventq_index=0 578opList=system.cpu0.fuPool.FUList8.opList 579 580[system.cpu0.fuPool.FUList8.opList] 581type=OpDesc 582eventq_index=0 583issueLat=3 584opClass=IprAccess 585opLat=3 586 587[system.cpu0.icache] 588type=BaseCache 589children=tags 590addr_ranges=0:18446744073709551615 591assoc=1 592clk_domain=system.cpu_clk_domain 593eventq_index=0 594forward_snoops=true 595hit_latency=2 596is_top_level=true 597max_miss_count=0 598mshrs=4 599prefetch_on_access=false 600prefetcher=Null 601response_latency=2 602sequential_access=false 603size=32768 604system=system 605tags=system.cpu0.icache.tags 606tgts_per_mshr=20 607two_queue=false 608write_buffers=8 609cpu_side=system.cpu0.icache_port 610mem_side=system.toL2Bus.slave[0] 611 612[system.cpu0.icache.tags] 613type=LRU 614assoc=1 615block_size=64 616clk_domain=system.cpu_clk_domain 617eventq_index=0 618hit_latency=2 619sequential_access=false 620size=32768 621 622[system.cpu0.interrupts] 623type=ArmInterrupts 624eventq_index=0 625 626[system.cpu0.isa] 627type=ArmISA 628eventq_index=0 629fpsid=1090793632 630id_aa64afr0_el1=0 631id_aa64afr1_el1=0 632id_aa64dfr0_el1=1052678 633id_aa64dfr1_el1=0 634id_aa64isar0_el1=0 635id_aa64isar1_el1=0 636id_aa64mmfr0_el1=15728642 637id_aa64mmfr1_el1=0 638id_aa64pfr0_el1=17 639id_aa64pfr1_el1=0 640id_isar0=34607377 641id_isar1=34677009 642id_isar2=555950401 643id_isar3=17899825 644id_isar4=268501314 645id_isar5=0 646id_mmfr0=270536963 647id_mmfr1=0 648id_mmfr2=19070976 649id_mmfr3=34611729 650id_pfr0=49 651id_pfr1=4113 652midr=1091551472 653system=system 654 655[system.cpu0.istage2_mmu] 656type=ArmStage2MMU 657children=stage2_tlb 658eventq_index=0 659stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb 660tlb=system.cpu0.itb 661 662[system.cpu0.istage2_mmu.stage2_tlb] 663type=ArmTLB 664children=walker 665eventq_index=0 666is_stage2=true 667size=32 668walker=system.cpu0.istage2_mmu.stage2_tlb.walker 669 670[system.cpu0.istage2_mmu.stage2_tlb.walker] 671type=ArmTableWalker 672clk_domain=system.cpu_clk_domain 673eventq_index=0 674is_stage2=true 675num_squash_per_cycle=2 676sys=system 677port=system.toL2Bus.slave[4] 678 679[system.cpu0.itb] 680type=ArmTLB 681children=walker 682eventq_index=0 683is_stage2=false 684size=64 685walker=system.cpu0.itb.walker 686 687[system.cpu0.itb.walker] 688type=ArmTableWalker 689clk_domain=system.cpu_clk_domain 690eventq_index=0 691is_stage2=false 692num_squash_per_cycle=2 693sys=system 694port=system.toL2Bus.slave[2] 695 696[system.cpu0.tracer] 697type=ExeTracer 698eventq_index=0 699 700[system.cpu1] 701type=DerivO3CPU 702children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer 703LFSTSize=1024 704LQEntries=32 705LSQCheckLoads=true 706LSQDepCheckShift=4 707SQEntries=32 708SSITSize=1024 709activity=0 710backComSize=5 711branchPred=system.cpu1.branchPred 712cachePorts=200 713checker=Null 714clk_domain=system.cpu_clk_domain 715commitToDecodeDelay=1 716commitToFetchDelay=1 717commitToIEWDelay=1 718commitToRenameDelay=1 719commitWidth=8 720cpu_id=1 721decodeToFetchDelay=1 722decodeToRenameDelay=1 723decodeWidth=8 724dispatchWidth=8 725do_checkpoint_insts=true 726do_quiesce=true 727do_statistics_insts=true 728dstage2_mmu=system.cpu1.dstage2_mmu 729dtb=system.cpu1.dtb 730eventq_index=0 731fetchBufferSize=64 732fetchToDecodeDelay=1 733fetchTrapLatency=1 734fetchWidth=8 735forwardComSize=5 736fuPool=system.cpu1.fuPool 737function_trace=false 738function_trace_start=0 739iewToCommitDelay=1 740iewToDecodeDelay=1 741iewToFetchDelay=1 742iewToRenameDelay=1 743interrupts=system.cpu1.interrupts 744isa=system.cpu1.isa 745issueToExecuteDelay=1 746issueWidth=8 747istage2_mmu=system.cpu1.istage2_mmu 748itb=system.cpu1.itb 749max_insts_all_threads=0 750max_insts_any_thread=0 751max_loads_all_threads=0 752max_loads_any_thread=0 753needsTSO=false 754numIQEntries=64 755numPhysCCRegs=0 756numPhysFloatRegs=256 757numPhysIntRegs=256 758numROBEntries=192 759numRobs=1 760numThreads=1 761profile=0 762progress_interval=0 763renameToDecodeDelay=1 764renameToFetchDelay=1 765renameToIEWDelay=2 766renameToROBDelay=1 767renameWidth=8 768simpoint_start_insts= 769smtCommitPolicy=RoundRobin 770smtFetchPolicy=SingleThread 771smtIQPolicy=Partitioned 772smtIQThreshold=100 773smtLSQPolicy=Partitioned 774smtLSQThreshold=100 775smtNumFetchingThreads=1 776smtROBPolicy=Partitioned 777smtROBThreshold=100	176squashWidth=8 177store_set_clear_period=250000 178switched_out=false 179system=system 180tracer=system.cpu0.tracer 181trapLatency=13 182wbDepth=1 183wbWidth=8 184workload= 185dcache_port=system.cpu0.dcache.cpu_side 186icache_port=system.cpu0.icache.cpu_side 187 188[system.cpu0.branchPred] 189type=BranchPredictor 190BTBEntries=4096 191BTBTagSize=16 192RASSize=16 193choiceCtrBits=2 194choicePredictorSize=8192 195eventq_index=0 196globalCtrBits=2 197globalPredictorSize=8192 198instShiftAmt=2 199localCtrBits=2 200localHistoryTableSize=2048 201localPredictorSize=2048 202numThreads=1 203predType=tournament 204 205[system.cpu0.dcache] 206type=BaseCache 207children=tags 208addr_ranges=0:18446744073709551615 209assoc=4 210clk_domain=system.cpu_clk_domain 211eventq_index=0 212forward_snoops=true 213hit_latency=2 214is_top_level=true 215max_miss_count=0 216mshrs=4 217prefetch_on_access=false 218prefetcher=Null 219response_latency=2 220sequential_access=false 221size=32768 222system=system 223tags=system.cpu0.dcache.tags 224tgts_per_mshr=20 225two_queue=false 226write_buffers=8 227cpu_side=system.cpu0.dcache_port 228mem_side=system.toL2Bus.slave[1] 229 230[system.cpu0.dcache.tags] 231type=LRU 232assoc=4 233block_size=64 234clk_domain=system.cpu_clk_domain 235eventq_index=0 236hit_latency=2 237sequential_access=false 238size=32768 239 240[system.cpu0.dstage2_mmu] 241type=ArmStage2MMU 242children=stage2_tlb 243eventq_index=0 244stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb 245tlb=system.cpu0.dtb 246 247[system.cpu0.dstage2_mmu.stage2_tlb] 248type=ArmTLB 249children=walker 250eventq_index=0 251is_stage2=true 252size=32 253walker=system.cpu0.dstage2_mmu.stage2_tlb.walker 254 255[system.cpu0.dstage2_mmu.stage2_tlb.walker] 256type=ArmTableWalker 257clk_domain=system.cpu_clk_domain 258eventq_index=0 259is_stage2=true 260num_squash_per_cycle=2 261sys=system 262port=system.toL2Bus.slave[5] 263 264[system.cpu0.dtb] 265type=ArmTLB 266children=walker 267eventq_index=0 268is_stage2=false 269size=64 270walker=system.cpu0.dtb.walker 271 272[system.cpu0.dtb.walker] 273type=ArmTableWalker 274clk_domain=system.cpu_clk_domain 275eventq_index=0 276is_stage2=false 277num_squash_per_cycle=2 278sys=system 279port=system.toL2Bus.slave[3] 280 281[system.cpu0.fuPool] 282type=FUPool 283children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 284FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 285eventq_index=0 286 287[system.cpu0.fuPool.FUList0] 288type=FUDesc 289children=opList 290count=6 291eventq_index=0 292opList=system.cpu0.fuPool.FUList0.opList 293 294[system.cpu0.fuPool.FUList0.opList] 295type=OpDesc 296eventq_index=0 297issueLat=1 298opClass=IntAlu 299opLat=1 300 301[system.cpu0.fuPool.FUList1] 302type=FUDesc 303children=opList0 opList1 304count=2 305eventq_index=0 306opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 307 308[system.cpu0.fuPool.FUList1.opList0] 309type=OpDesc 310eventq_index=0 311issueLat=1 312opClass=IntMult 313opLat=3 314 315[system.cpu0.fuPool.FUList1.opList1] 316type=OpDesc 317eventq_index=0 318issueLat=19 319opClass=IntDiv 320opLat=20 321 322[system.cpu0.fuPool.FUList2] 323type=FUDesc 324children=opList0 opList1 opList2 325count=4 326eventq_index=0 327opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 328 329[system.cpu0.fuPool.FUList2.opList0] 330type=OpDesc 331eventq_index=0 332issueLat=1 333opClass=FloatAdd 334opLat=2 335 336[system.cpu0.fuPool.FUList2.opList1] 337type=OpDesc 338eventq_index=0 339issueLat=1 340opClass=FloatCmp 341opLat=2 342 343[system.cpu0.fuPool.FUList2.opList2] 344type=OpDesc 345eventq_index=0 346issueLat=1 347opClass=FloatCvt 348opLat=2 349 350[system.cpu0.fuPool.FUList3] 351type=FUDesc 352children=opList0 opList1 opList2 353count=2 354eventq_index=0 355opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 356 357[system.cpu0.fuPool.FUList3.opList0] 358type=OpDesc 359eventq_index=0 360issueLat=1 361opClass=FloatMult 362opLat=4 363 364[system.cpu0.fuPool.FUList3.opList1] 365type=OpDesc 366eventq_index=0 367issueLat=12 368opClass=FloatDiv 369opLat=12 370 371[system.cpu0.fuPool.FUList3.opList2] 372type=OpDesc 373eventq_index=0 374issueLat=24 375opClass=FloatSqrt 376opLat=24 377 378[system.cpu0.fuPool.FUList4] 379type=FUDesc 380children=opList 381count=0 382eventq_index=0 383opList=system.cpu0.fuPool.FUList4.opList 384 385[system.cpu0.fuPool.FUList4.opList] 386type=OpDesc 387eventq_index=0 388issueLat=1 389opClass=MemRead 390opLat=1 391 392[system.cpu0.fuPool.FUList5] 393type=FUDesc 394children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 395count=4 396eventq_index=0 397opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 398 399[system.cpu0.fuPool.FUList5.opList00] 400type=OpDesc 401eventq_index=0 402issueLat=1 403opClass=SimdAdd 404opLat=1 405 406[system.cpu0.fuPool.FUList5.opList01] 407type=OpDesc 408eventq_index=0 409issueLat=1 410opClass=SimdAddAcc 411opLat=1 412 413[system.cpu0.fuPool.FUList5.opList02] 414type=OpDesc 415eventq_index=0 416issueLat=1 417opClass=SimdAlu 418opLat=1 419 420[system.cpu0.fuPool.FUList5.opList03] 421type=OpDesc 422eventq_index=0 423issueLat=1 424opClass=SimdCmp 425opLat=1 426 427[system.cpu0.fuPool.FUList5.opList04] 428type=OpDesc 429eventq_index=0 430issueLat=1 431opClass=SimdCvt 432opLat=1 433 434[system.cpu0.fuPool.FUList5.opList05] 435type=OpDesc 436eventq_index=0 437issueLat=1 438opClass=SimdMisc 439opLat=1 440 441[system.cpu0.fuPool.FUList5.opList06] 442type=OpDesc 443eventq_index=0 444issueLat=1 445opClass=SimdMult 446opLat=1 447 448[system.cpu0.fuPool.FUList5.opList07] 449type=OpDesc 450eventq_index=0 451issueLat=1 452opClass=SimdMultAcc 453opLat=1 454 455[system.cpu0.fuPool.FUList5.opList08] 456type=OpDesc 457eventq_index=0 458issueLat=1 459opClass=SimdShift 460opLat=1 461 462[system.cpu0.fuPool.FUList5.opList09] 463type=OpDesc 464eventq_index=0 465issueLat=1 466opClass=SimdShiftAcc 467opLat=1 468 469[system.cpu0.fuPool.FUList5.opList10] 470type=OpDesc 471eventq_index=0 472issueLat=1 473opClass=SimdSqrt 474opLat=1 475 476[system.cpu0.fuPool.FUList5.opList11] 477type=OpDesc 478eventq_index=0 479issueLat=1 480opClass=SimdFloatAdd 481opLat=1 482 483[system.cpu0.fuPool.FUList5.opList12] 484type=OpDesc 485eventq_index=0 486issueLat=1 487opClass=SimdFloatAlu 488opLat=1 489 490[system.cpu0.fuPool.FUList5.opList13] 491type=OpDesc 492eventq_index=0 493issueLat=1 494opClass=SimdFloatCmp 495opLat=1 496 497[system.cpu0.fuPool.FUList5.opList14] 498type=OpDesc 499eventq_index=0 500issueLat=1 501opClass=SimdFloatCvt 502opLat=1 503 504[system.cpu0.fuPool.FUList5.opList15] 505type=OpDesc 506eventq_index=0 507issueLat=1 508opClass=SimdFloatDiv 509opLat=1 510 511[system.cpu0.fuPool.FUList5.opList16] 512type=OpDesc 513eventq_index=0 514issueLat=1 515opClass=SimdFloatMisc 516opLat=1 517 518[system.cpu0.fuPool.FUList5.opList17] 519type=OpDesc 520eventq_index=0 521issueLat=1 522opClass=SimdFloatMult 523opLat=1 524 525[system.cpu0.fuPool.FUList5.opList18] 526type=OpDesc 527eventq_index=0 528issueLat=1 529opClass=SimdFloatMultAcc 530opLat=1 531 532[system.cpu0.fuPool.FUList5.opList19] 533type=OpDesc 534eventq_index=0 535issueLat=1 536opClass=SimdFloatSqrt 537opLat=1 538 539[system.cpu0.fuPool.FUList6] 540type=FUDesc 541children=opList 542count=0 543eventq_index=0 544opList=system.cpu0.fuPool.FUList6.opList 545 546[system.cpu0.fuPool.FUList6.opList] 547type=OpDesc 548eventq_index=0 549issueLat=1 550opClass=MemWrite 551opLat=1 552 553[system.cpu0.fuPool.FUList7] 554type=FUDesc 555children=opList0 opList1 556count=4 557eventq_index=0 558opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 559 560[system.cpu0.fuPool.FUList7.opList0] 561type=OpDesc 562eventq_index=0 563issueLat=1 564opClass=MemRead 565opLat=1 566 567[system.cpu0.fuPool.FUList7.opList1] 568type=OpDesc 569eventq_index=0 570issueLat=1 571opClass=MemWrite 572opLat=1 573 574[system.cpu0.fuPool.FUList8] 575type=FUDesc 576children=opList 577count=1 578eventq_index=0 579opList=system.cpu0.fuPool.FUList8.opList 580 581[system.cpu0.fuPool.FUList8.opList] 582type=OpDesc 583eventq_index=0 584issueLat=3 585opClass=IprAccess 586opLat=3 587 588[system.cpu0.icache] 589type=BaseCache 590children=tags 591addr_ranges=0:18446744073709551615 592assoc=1 593clk_domain=system.cpu_clk_domain 594eventq_index=0 595forward_snoops=true 596hit_latency=2 597is_top_level=true 598max_miss_count=0 599mshrs=4 600prefetch_on_access=false 601prefetcher=Null 602response_latency=2 603sequential_access=false 604size=32768 605system=system 606tags=system.cpu0.icache.tags 607tgts_per_mshr=20 608two_queue=false 609write_buffers=8 610cpu_side=system.cpu0.icache_port 611mem_side=system.toL2Bus.slave[0] 612 613[system.cpu0.icache.tags] 614type=LRU 615assoc=1 616block_size=64 617clk_domain=system.cpu_clk_domain 618eventq_index=0 619hit_latency=2 620sequential_access=false 621size=32768 622 623[system.cpu0.interrupts] 624type=ArmInterrupts 625eventq_index=0 626 627[system.cpu0.isa] 628type=ArmISA 629eventq_index=0 630fpsid=1090793632 631id_aa64afr0_el1=0 632id_aa64afr1_el1=0 633id_aa64dfr0_el1=1052678 634id_aa64dfr1_el1=0 635id_aa64isar0_el1=0 636id_aa64isar1_el1=0 637id_aa64mmfr0_el1=15728642 638id_aa64mmfr1_el1=0 639id_aa64pfr0_el1=17 640id_aa64pfr1_el1=0 641id_isar0=34607377 642id_isar1=34677009 643id_isar2=555950401 644id_isar3=17899825 645id_isar4=268501314 646id_isar5=0 647id_mmfr0=270536963 648id_mmfr1=0 649id_mmfr2=19070976 650id_mmfr3=34611729 651id_pfr0=49 652id_pfr1=4113 653midr=1091551472 654system=system 655 656[system.cpu0.istage2_mmu] 657type=ArmStage2MMU 658children=stage2_tlb 659eventq_index=0 660stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb 661tlb=system.cpu0.itb 662 663[system.cpu0.istage2_mmu.stage2_tlb] 664type=ArmTLB 665children=walker 666eventq_index=0 667is_stage2=true 668size=32 669walker=system.cpu0.istage2_mmu.stage2_tlb.walker 670 671[system.cpu0.istage2_mmu.stage2_tlb.walker] 672type=ArmTableWalker 673clk_domain=system.cpu_clk_domain 674eventq_index=0 675is_stage2=true 676num_squash_per_cycle=2 677sys=system 678port=system.toL2Bus.slave[4] 679 680[system.cpu0.itb] 681type=ArmTLB 682children=walker 683eventq_index=0 684is_stage2=false 685size=64 686walker=system.cpu0.itb.walker 687 688[system.cpu0.itb.walker] 689type=ArmTableWalker 690clk_domain=system.cpu_clk_domain 691eventq_index=0 692is_stage2=false 693num_squash_per_cycle=2 694sys=system 695port=system.toL2Bus.slave[2] 696 697[system.cpu0.tracer] 698type=ExeTracer 699eventq_index=0 700 701[system.cpu1] 702type=DerivO3CPU 703children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer 704LFSTSize=1024 705LQEntries=32 706LSQCheckLoads=true 707LSQDepCheckShift=4 708SQEntries=32 709SSITSize=1024 710activity=0 711backComSize=5 712branchPred=system.cpu1.branchPred 713cachePorts=200 714checker=Null 715clk_domain=system.cpu_clk_domain 716commitToDecodeDelay=1 717commitToFetchDelay=1 718commitToIEWDelay=1 719commitToRenameDelay=1 720commitWidth=8 721cpu_id=1 722decodeToFetchDelay=1 723decodeToRenameDelay=1 724decodeWidth=8 725dispatchWidth=8 726do_checkpoint_insts=true 727do_quiesce=true 728do_statistics_insts=true 729dstage2_mmu=system.cpu1.dstage2_mmu 730dtb=system.cpu1.dtb 731eventq_index=0 732fetchBufferSize=64 733fetchToDecodeDelay=1 734fetchTrapLatency=1 735fetchWidth=8 736forwardComSize=5 737fuPool=system.cpu1.fuPool 738function_trace=false 739function_trace_start=0 740iewToCommitDelay=1 741iewToDecodeDelay=1 742iewToFetchDelay=1 743iewToRenameDelay=1 744interrupts=system.cpu1.interrupts 745isa=system.cpu1.isa 746issueToExecuteDelay=1 747issueWidth=8 748istage2_mmu=system.cpu1.istage2_mmu 749itb=system.cpu1.itb 750max_insts_all_threads=0 751max_insts_any_thread=0 752max_loads_all_threads=0 753max_loads_any_thread=0 754needsTSO=false 755numIQEntries=64 756numPhysCCRegs=0 757numPhysFloatRegs=256 758numPhysIntRegs=256 759numROBEntries=192 760numRobs=1 761numThreads=1 762profile=0 763progress_interval=0 764renameToDecodeDelay=1 765renameToFetchDelay=1 766renameToIEWDelay=2 767renameToROBDelay=1 768renameWidth=8 769simpoint_start_insts= 770smtCommitPolicy=RoundRobin 771smtFetchPolicy=SingleThread 772smtIQPolicy=Partitioned 773smtIQThreshold=100 774smtLSQPolicy=Partitioned 775smtLSQThreshold=100 776smtNumFetchingThreads=1 777smtROBPolicy=Partitioned 778smtROBThreshold=100
	779socket_id=0
778squashWidth=8 779store_set_clear_period=250000 780switched_out=false 781system=system 782tracer=system.cpu1.tracer 783trapLatency=13 784wbDepth=1 785wbWidth=8 786workload= 787dcache_port=system.cpu1.dcache.cpu_side 788icache_port=system.cpu1.icache.cpu_side 789 790[system.cpu1.branchPred] 791type=BranchPredictor 792BTBEntries=4096 793BTBTagSize=16 794RASSize=16 795choiceCtrBits=2 796choicePredictorSize=8192 797eventq_index=0 798globalCtrBits=2 799globalPredictorSize=8192 800instShiftAmt=2 801localCtrBits=2 802localHistoryTableSize=2048 803localPredictorSize=2048 804numThreads=1 805predType=tournament 806 807[system.cpu1.dcache] 808type=BaseCache 809children=tags 810addr_ranges=0:18446744073709551615 811assoc=4 812clk_domain=system.cpu_clk_domain 813eventq_index=0 814forward_snoops=true 815hit_latency=2 816is_top_level=true 817max_miss_count=0 818mshrs=4 819prefetch_on_access=false 820prefetcher=Null 821response_latency=2 822sequential_access=false 823size=32768 824system=system 825tags=system.cpu1.dcache.tags 826tgts_per_mshr=20 827two_queue=false 828write_buffers=8 829cpu_side=system.cpu1.dcache_port 830mem_side=system.toL2Bus.slave[7] 831 832[system.cpu1.dcache.tags] 833type=LRU 834assoc=4 835block_size=64 836clk_domain=system.cpu_clk_domain 837eventq_index=0 838hit_latency=2 839sequential_access=false 840size=32768 841 842[system.cpu1.dstage2_mmu] 843type=ArmStage2MMU 844children=stage2_tlb 845eventq_index=0 846stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb 847tlb=system.cpu1.dtb 848 849[system.cpu1.dstage2_mmu.stage2_tlb] 850type=ArmTLB 851children=walker 852eventq_index=0 853is_stage2=true 854size=32 855walker=system.cpu1.dstage2_mmu.stage2_tlb.walker 856 857[system.cpu1.dstage2_mmu.stage2_tlb.walker] 858type=ArmTableWalker 859clk_domain=system.cpu_clk_domain 860eventq_index=0 861is_stage2=true 862num_squash_per_cycle=2 863sys=system 864port=system.toL2Bus.slave[11] 865 866[system.cpu1.dtb] 867type=ArmTLB 868children=walker 869eventq_index=0 870is_stage2=false 871size=64 872walker=system.cpu1.dtb.walker 873 874[system.cpu1.dtb.walker] 875type=ArmTableWalker 876clk_domain=system.cpu_clk_domain 877eventq_index=0 878is_stage2=false 879num_squash_per_cycle=2 880sys=system 881port=system.toL2Bus.slave[9] 882 883[system.cpu1.fuPool] 884type=FUPool 885children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 886FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 887eventq_index=0 888 889[system.cpu1.fuPool.FUList0] 890type=FUDesc 891children=opList 892count=6 893eventq_index=0 894opList=system.cpu1.fuPool.FUList0.opList 895 896[system.cpu1.fuPool.FUList0.opList] 897type=OpDesc 898eventq_index=0 899issueLat=1 900opClass=IntAlu 901opLat=1 902 903[system.cpu1.fuPool.FUList1] 904type=FUDesc 905children=opList0 opList1 906count=2 907eventq_index=0 908opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 909 910[system.cpu1.fuPool.FUList1.opList0] 911type=OpDesc 912eventq_index=0 913issueLat=1 914opClass=IntMult 915opLat=3 916 917[system.cpu1.fuPool.FUList1.opList1] 918type=OpDesc 919eventq_index=0 920issueLat=19 921opClass=IntDiv 922opLat=20 923 924[system.cpu1.fuPool.FUList2] 925type=FUDesc 926children=opList0 opList1 opList2 927count=4 928eventq_index=0 929opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 930 931[system.cpu1.fuPool.FUList2.opList0] 932type=OpDesc 933eventq_index=0 934issueLat=1 935opClass=FloatAdd 936opLat=2 937 938[system.cpu1.fuPool.FUList2.opList1] 939type=OpDesc 940eventq_index=0 941issueLat=1 942opClass=FloatCmp 943opLat=2 944 945[system.cpu1.fuPool.FUList2.opList2] 946type=OpDesc 947eventq_index=0 948issueLat=1 949opClass=FloatCvt 950opLat=2 951 952[system.cpu1.fuPool.FUList3] 953type=FUDesc 954children=opList0 opList1 opList2 955count=2 956eventq_index=0 957opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 958 959[system.cpu1.fuPool.FUList3.opList0] 960type=OpDesc 961eventq_index=0 962issueLat=1 963opClass=FloatMult 964opLat=4 965 966[system.cpu1.fuPool.FUList3.opList1] 967type=OpDesc 968eventq_index=0 969issueLat=12 970opClass=FloatDiv 971opLat=12 972 973[system.cpu1.fuPool.FUList3.opList2] 974type=OpDesc 975eventq_index=0 976issueLat=24 977opClass=FloatSqrt 978opLat=24 979 980[system.cpu1.fuPool.FUList4] 981type=FUDesc 982children=opList 983count=0 984eventq_index=0 985opList=system.cpu1.fuPool.FUList4.opList 986 987[system.cpu1.fuPool.FUList4.opList] 988type=OpDesc 989eventq_index=0 990issueLat=1 991opClass=MemRead 992opLat=1 993 994[system.cpu1.fuPool.FUList5] 995type=FUDesc 996children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 997count=4 998eventq_index=0 999opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 1000 1001[system.cpu1.fuPool.FUList5.opList00] 1002type=OpDesc 1003eventq_index=0 1004issueLat=1 1005opClass=SimdAdd 1006opLat=1 1007 1008[system.cpu1.fuPool.FUList5.opList01] 1009type=OpDesc 1010eventq_index=0 1011issueLat=1 1012opClass=SimdAddAcc 1013opLat=1 1014 1015[system.cpu1.fuPool.FUList5.opList02] 1016type=OpDesc 1017eventq_index=0 1018issueLat=1 1019opClass=SimdAlu 1020opLat=1 1021 1022[system.cpu1.fuPool.FUList5.opList03] 1023type=OpDesc 1024eventq_index=0 1025issueLat=1 1026opClass=SimdCmp 1027opLat=1 1028 1029[system.cpu1.fuPool.FUList5.opList04] 1030type=OpDesc 1031eventq_index=0 1032issueLat=1 1033opClass=SimdCvt 1034opLat=1 1035 1036[system.cpu1.fuPool.FUList5.opList05] 1037type=OpDesc 1038eventq_index=0 1039issueLat=1 1040opClass=SimdMisc 1041opLat=1 1042 1043[system.cpu1.fuPool.FUList5.opList06] 1044type=OpDesc 1045eventq_index=0 1046issueLat=1 1047opClass=SimdMult 1048opLat=1 1049 1050[system.cpu1.fuPool.FUList5.opList07] 1051type=OpDesc 1052eventq_index=0 1053issueLat=1 1054opClass=SimdMultAcc 1055opLat=1 1056 1057[system.cpu1.fuPool.FUList5.opList08] 1058type=OpDesc 1059eventq_index=0 1060issueLat=1 1061opClass=SimdShift 1062opLat=1 1063 1064[system.cpu1.fuPool.FUList5.opList09] 1065type=OpDesc 1066eventq_index=0 1067issueLat=1 1068opClass=SimdShiftAcc 1069opLat=1 1070 1071[system.cpu1.fuPool.FUList5.opList10] 1072type=OpDesc 1073eventq_index=0 1074issueLat=1 1075opClass=SimdSqrt 1076opLat=1 1077 1078[system.cpu1.fuPool.FUList5.opList11] 1079type=OpDesc 1080eventq_index=0 1081issueLat=1 1082opClass=SimdFloatAdd 1083opLat=1 1084 1085[system.cpu1.fuPool.FUList5.opList12] 1086type=OpDesc 1087eventq_index=0 1088issueLat=1 1089opClass=SimdFloatAlu 1090opLat=1 1091 1092[system.cpu1.fuPool.FUList5.opList13] 1093type=OpDesc 1094eventq_index=0 1095issueLat=1 1096opClass=SimdFloatCmp 1097opLat=1 1098 1099[system.cpu1.fuPool.FUList5.opList14] 1100type=OpDesc 1101eventq_index=0 1102issueLat=1 1103opClass=SimdFloatCvt 1104opLat=1 1105 1106[system.cpu1.fuPool.FUList5.opList15] 1107type=OpDesc 1108eventq_index=0 1109issueLat=1 1110opClass=SimdFloatDiv 1111opLat=1 1112 1113[system.cpu1.fuPool.FUList5.opList16] 1114type=OpDesc 1115eventq_index=0 1116issueLat=1 1117opClass=SimdFloatMisc 1118opLat=1 1119 1120[system.cpu1.fuPool.FUList5.opList17] 1121type=OpDesc 1122eventq_index=0 1123issueLat=1 1124opClass=SimdFloatMult 1125opLat=1 1126 1127[system.cpu1.fuPool.FUList5.opList18] 1128type=OpDesc 1129eventq_index=0 1130issueLat=1 1131opClass=SimdFloatMultAcc 1132opLat=1 1133 1134[system.cpu1.fuPool.FUList5.opList19] 1135type=OpDesc 1136eventq_index=0 1137issueLat=1 1138opClass=SimdFloatSqrt 1139opLat=1 1140 1141[system.cpu1.fuPool.FUList6] 1142type=FUDesc 1143children=opList 1144count=0 1145eventq_index=0 1146opList=system.cpu1.fuPool.FUList6.opList 1147 1148[system.cpu1.fuPool.FUList6.opList] 1149type=OpDesc 1150eventq_index=0 1151issueLat=1 1152opClass=MemWrite 1153opLat=1 1154 1155[system.cpu1.fuPool.FUList7] 1156type=FUDesc 1157children=opList0 opList1 1158count=4 1159eventq_index=0 1160opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 1161 1162[system.cpu1.fuPool.FUList7.opList0] 1163type=OpDesc 1164eventq_index=0 1165issueLat=1 1166opClass=MemRead 1167opLat=1 1168 1169[system.cpu1.fuPool.FUList7.opList1] 1170type=OpDesc 1171eventq_index=0 1172issueLat=1 1173opClass=MemWrite 1174opLat=1 1175 1176[system.cpu1.fuPool.FUList8] 1177type=FUDesc 1178children=opList 1179count=1 1180eventq_index=0 1181opList=system.cpu1.fuPool.FUList8.opList 1182 1183[system.cpu1.fuPool.FUList8.opList] 1184type=OpDesc 1185eventq_index=0 1186issueLat=3 1187opClass=IprAccess 1188opLat=3 1189 1190[system.cpu1.icache] 1191type=BaseCache 1192children=tags 1193addr_ranges=0:18446744073709551615 1194assoc=1 1195clk_domain=system.cpu_clk_domain 1196eventq_index=0 1197forward_snoops=true 1198hit_latency=2 1199is_top_level=true 1200max_miss_count=0 1201mshrs=4 1202prefetch_on_access=false 1203prefetcher=Null 1204response_latency=2 1205sequential_access=false 1206size=32768 1207system=system 1208tags=system.cpu1.icache.tags 1209tgts_per_mshr=20 1210two_queue=false 1211write_buffers=8 1212cpu_side=system.cpu1.icache_port 1213mem_side=system.toL2Bus.slave[6] 1214 1215[system.cpu1.icache.tags] 1216type=LRU 1217assoc=1 1218block_size=64 1219clk_domain=system.cpu_clk_domain 1220eventq_index=0 1221hit_latency=2 1222sequential_access=false 1223size=32768 1224 1225[system.cpu1.interrupts] 1226type=ArmInterrupts 1227eventq_index=0 1228 1229[system.cpu1.isa] 1230type=ArmISA 1231eventq_index=0 1232fpsid=1090793632 1233id_aa64afr0_el1=0 1234id_aa64afr1_el1=0 1235id_aa64dfr0_el1=1052678 1236id_aa64dfr1_el1=0 1237id_aa64isar0_el1=0 1238id_aa64isar1_el1=0 1239id_aa64mmfr0_el1=15728642 1240id_aa64mmfr1_el1=0 1241id_aa64pfr0_el1=17 1242id_aa64pfr1_el1=0 1243id_isar0=34607377 1244id_isar1=34677009 1245id_isar2=555950401 1246id_isar3=17899825 1247id_isar4=268501314 1248id_isar5=0 1249id_mmfr0=270536963 1250id_mmfr1=0 1251id_mmfr2=19070976 1252id_mmfr3=34611729 1253id_pfr0=49 1254id_pfr1=4113 1255midr=1091551472 1256system=system 1257 1258[system.cpu1.istage2_mmu] 1259type=ArmStage2MMU 1260children=stage2_tlb 1261eventq_index=0 1262stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb 1263tlb=system.cpu1.itb 1264 1265[system.cpu1.istage2_mmu.stage2_tlb] 1266type=ArmTLB 1267children=walker 1268eventq_index=0 1269is_stage2=true 1270size=32 1271walker=system.cpu1.istage2_mmu.stage2_tlb.walker 1272 1273[system.cpu1.istage2_mmu.stage2_tlb.walker] 1274type=ArmTableWalker 1275clk_domain=system.cpu_clk_domain 1276eventq_index=0 1277is_stage2=true 1278num_squash_per_cycle=2 1279sys=system 1280port=system.toL2Bus.slave[10] 1281 1282[system.cpu1.itb] 1283type=ArmTLB 1284children=walker 1285eventq_index=0 1286is_stage2=false 1287size=64 1288walker=system.cpu1.itb.walker 1289 1290[system.cpu1.itb.walker] 1291type=ArmTableWalker 1292clk_domain=system.cpu_clk_domain 1293eventq_index=0 1294is_stage2=false 1295num_squash_per_cycle=2 1296sys=system 1297port=system.toL2Bus.slave[8] 1298 1299[system.cpu1.tracer] 1300type=ExeTracer 1301eventq_index=0 1302 1303[system.cpu_clk_domain] 1304type=SrcClockDomain 1305clock=500 1306eventq_index=0 1307voltage_domain=system.voltage_domain 1308 1309[system.intrctrl] 1310type=IntrControl 1311eventq_index=0 1312sys=system 1313 1314[system.iobus] 1315type=NoncoherentBus 1316clk_domain=system.clk_domain 1317eventq_index=0 1318header_cycles=1 1319use_default_range=false 1320width=8 1321master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side 1322slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 1323 1324[system.iocache] 1325type=BaseCache 1326children=tags 1327addr_ranges=0:134217727 1328assoc=8 1329clk_domain=system.clk_domain 1330eventq_index=0 1331forward_snoops=false 1332hit_latency=50 1333is_top_level=true 1334max_miss_count=0 1335mshrs=20 1336prefetch_on_access=false 1337prefetcher=Null 1338response_latency=50 1339sequential_access=false 1340size=1024 1341system=system 1342tags=system.iocache.tags 1343tgts_per_mshr=12 1344two_queue=false 1345write_buffers=8 1346cpu_side=system.iobus.master[25] 1347mem_side=system.membus.slave[2] 1348 1349[system.iocache.tags] 1350type=LRU 1351assoc=8 1352block_size=64 1353clk_domain=system.clk_domain 1354eventq_index=0 1355hit_latency=50 1356sequential_access=false 1357size=1024 1358 1359[system.l2c] 1360type=BaseCache 1361children=tags 1362addr_ranges=0:18446744073709551615 1363assoc=8 1364clk_domain=system.cpu_clk_domain 1365eventq_index=0 1366forward_snoops=true 1367hit_latency=20 1368is_top_level=false 1369max_miss_count=0 1370mshrs=20 1371prefetch_on_access=false 1372prefetcher=Null 1373response_latency=20 1374sequential_access=false 1375size=4194304 1376system=system 1377tags=system.l2c.tags 1378tgts_per_mshr=12 1379two_queue=false 1380write_buffers=8 1381cpu_side=system.toL2Bus.master[0] 1382mem_side=system.membus.slave[1] 1383 1384[system.l2c.tags] 1385type=LRU 1386assoc=8 1387block_size=64 1388clk_domain=system.cpu_clk_domain 1389eventq_index=0 1390hit_latency=20 1391sequential_access=false 1392size=4194304 1393 1394[system.membus] 1395type=CoherentBus 1396children=badaddr_responder 1397clk_domain=system.clk_domain 1398eventq_index=0 1399header_cycles=1 1400system=system 1401use_default_range=false 1402width=8 1403default=system.membus.badaddr_responder.pio 1404master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port 1405slave=system.system_port system.l2c.mem_side system.iocache.mem_side 1406 1407[system.membus.badaddr_responder] 1408type=IsaFake 1409clk_domain=system.clk_domain 1410eventq_index=0 1411fake_mem=false 1412pio_addr=0 1413pio_latency=100000 1414pio_size=8 1415ret_bad_addr=true 1416ret_data16=65535 1417ret_data32=4294967295 1418ret_data64=18446744073709551615 1419ret_data8=255 1420system=system 1421update_data=false 1422warn_access=warn 1423pio=system.membus.default 1424 1425[system.physmem]	780squashWidth=8 781store_set_clear_period=250000 782switched_out=false 783system=system 784tracer=system.cpu1.tracer 785trapLatency=13 786wbDepth=1 787wbWidth=8 788workload= 789dcache_port=system.cpu1.dcache.cpu_side 790icache_port=system.cpu1.icache.cpu_side 791 792[system.cpu1.branchPred] 793type=BranchPredictor 794BTBEntries=4096 795BTBTagSize=16 796RASSize=16 797choiceCtrBits=2 798choicePredictorSize=8192 799eventq_index=0 800globalCtrBits=2 801globalPredictorSize=8192 802instShiftAmt=2 803localCtrBits=2 804localHistoryTableSize=2048 805localPredictorSize=2048 806numThreads=1 807predType=tournament 808 809[system.cpu1.dcache] 810type=BaseCache 811children=tags 812addr_ranges=0:18446744073709551615 813assoc=4 814clk_domain=system.cpu_clk_domain 815eventq_index=0 816forward_snoops=true 817hit_latency=2 818is_top_level=true 819max_miss_count=0 820mshrs=4 821prefetch_on_access=false 822prefetcher=Null 823response_latency=2 824sequential_access=false 825size=32768 826system=system 827tags=system.cpu1.dcache.tags 828tgts_per_mshr=20 829two_queue=false 830write_buffers=8 831cpu_side=system.cpu1.dcache_port 832mem_side=system.toL2Bus.slave[7] 833 834[system.cpu1.dcache.tags] 835type=LRU 836assoc=4 837block_size=64 838clk_domain=system.cpu_clk_domain 839eventq_index=0 840hit_latency=2 841sequential_access=false 842size=32768 843 844[system.cpu1.dstage2_mmu] 845type=ArmStage2MMU 846children=stage2_tlb 847eventq_index=0 848stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb 849tlb=system.cpu1.dtb 850 851[system.cpu1.dstage2_mmu.stage2_tlb] 852type=ArmTLB 853children=walker 854eventq_index=0 855is_stage2=true 856size=32 857walker=system.cpu1.dstage2_mmu.stage2_tlb.walker 858 859[system.cpu1.dstage2_mmu.stage2_tlb.walker] 860type=ArmTableWalker 861clk_domain=system.cpu_clk_domain 862eventq_index=0 863is_stage2=true 864num_squash_per_cycle=2 865sys=system 866port=system.toL2Bus.slave[11] 867 868[system.cpu1.dtb] 869type=ArmTLB 870children=walker 871eventq_index=0 872is_stage2=false 873size=64 874walker=system.cpu1.dtb.walker 875 876[system.cpu1.dtb.walker] 877type=ArmTableWalker 878clk_domain=system.cpu_clk_domain 879eventq_index=0 880is_stage2=false 881num_squash_per_cycle=2 882sys=system 883port=system.toL2Bus.slave[9] 884 885[system.cpu1.fuPool] 886type=FUPool 887children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 888FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 889eventq_index=0 890 891[system.cpu1.fuPool.FUList0] 892type=FUDesc 893children=opList 894count=6 895eventq_index=0 896opList=system.cpu1.fuPool.FUList0.opList 897 898[system.cpu1.fuPool.FUList0.opList] 899type=OpDesc 900eventq_index=0 901issueLat=1 902opClass=IntAlu 903opLat=1 904 905[system.cpu1.fuPool.FUList1] 906type=FUDesc 907children=opList0 opList1 908count=2 909eventq_index=0 910opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 911 912[system.cpu1.fuPool.FUList1.opList0] 913type=OpDesc 914eventq_index=0 915issueLat=1 916opClass=IntMult 917opLat=3 918 919[system.cpu1.fuPool.FUList1.opList1] 920type=OpDesc 921eventq_index=0 922issueLat=19 923opClass=IntDiv 924opLat=20 925 926[system.cpu1.fuPool.FUList2] 927type=FUDesc 928children=opList0 opList1 opList2 929count=4 930eventq_index=0 931opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 932 933[system.cpu1.fuPool.FUList2.opList0] 934type=OpDesc 935eventq_index=0 936issueLat=1 937opClass=FloatAdd 938opLat=2 939 940[system.cpu1.fuPool.FUList2.opList1] 941type=OpDesc 942eventq_index=0 943issueLat=1 944opClass=FloatCmp 945opLat=2 946 947[system.cpu1.fuPool.FUList2.opList2] 948type=OpDesc 949eventq_index=0 950issueLat=1 951opClass=FloatCvt 952opLat=2 953 954[system.cpu1.fuPool.FUList3] 955type=FUDesc 956children=opList0 opList1 opList2 957count=2 958eventq_index=0 959opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 960 961[system.cpu1.fuPool.FUList3.opList0] 962type=OpDesc 963eventq_index=0 964issueLat=1 965opClass=FloatMult 966opLat=4 967 968[system.cpu1.fuPool.FUList3.opList1] 969type=OpDesc 970eventq_index=0 971issueLat=12 972opClass=FloatDiv 973opLat=12 974 975[system.cpu1.fuPool.FUList3.opList2] 976type=OpDesc 977eventq_index=0 978issueLat=24 979opClass=FloatSqrt 980opLat=24 981 982[system.cpu1.fuPool.FUList4] 983type=FUDesc 984children=opList 985count=0 986eventq_index=0 987opList=system.cpu1.fuPool.FUList4.opList 988 989[system.cpu1.fuPool.FUList4.opList] 990type=OpDesc 991eventq_index=0 992issueLat=1 993opClass=MemRead 994opLat=1 995 996[system.cpu1.fuPool.FUList5] 997type=FUDesc 998children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 999count=4 1000eventq_index=0 1001opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 1002 1003[system.cpu1.fuPool.FUList5.opList00] 1004type=OpDesc 1005eventq_index=0 1006issueLat=1 1007opClass=SimdAdd 1008opLat=1 1009 1010[system.cpu1.fuPool.FUList5.opList01] 1011type=OpDesc 1012eventq_index=0 1013issueLat=1 1014opClass=SimdAddAcc 1015opLat=1 1016 1017[system.cpu1.fuPool.FUList5.opList02] 1018type=OpDesc 1019eventq_index=0 1020issueLat=1 1021opClass=SimdAlu 1022opLat=1 1023 1024[system.cpu1.fuPool.FUList5.opList03] 1025type=OpDesc 1026eventq_index=0 1027issueLat=1 1028opClass=SimdCmp 1029opLat=1 1030 1031[system.cpu1.fuPool.FUList5.opList04] 1032type=OpDesc 1033eventq_index=0 1034issueLat=1 1035opClass=SimdCvt 1036opLat=1 1037 1038[system.cpu1.fuPool.FUList5.opList05] 1039type=OpDesc 1040eventq_index=0 1041issueLat=1 1042opClass=SimdMisc 1043opLat=1 1044 1045[system.cpu1.fuPool.FUList5.opList06] 1046type=OpDesc 1047eventq_index=0 1048issueLat=1 1049opClass=SimdMult 1050opLat=1 1051 1052[system.cpu1.fuPool.FUList5.opList07] 1053type=OpDesc 1054eventq_index=0 1055issueLat=1 1056opClass=SimdMultAcc 1057opLat=1 1058 1059[system.cpu1.fuPool.FUList5.opList08] 1060type=OpDesc 1061eventq_index=0 1062issueLat=1 1063opClass=SimdShift 1064opLat=1 1065 1066[system.cpu1.fuPool.FUList5.opList09] 1067type=OpDesc 1068eventq_index=0 1069issueLat=1 1070opClass=SimdShiftAcc 1071opLat=1 1072 1073[system.cpu1.fuPool.FUList5.opList10] 1074type=OpDesc 1075eventq_index=0 1076issueLat=1 1077opClass=SimdSqrt 1078opLat=1 1079 1080[system.cpu1.fuPool.FUList5.opList11] 1081type=OpDesc 1082eventq_index=0 1083issueLat=1 1084opClass=SimdFloatAdd 1085opLat=1 1086 1087[system.cpu1.fuPool.FUList5.opList12] 1088type=OpDesc 1089eventq_index=0 1090issueLat=1 1091opClass=SimdFloatAlu 1092opLat=1 1093 1094[system.cpu1.fuPool.FUList5.opList13] 1095type=OpDesc 1096eventq_index=0 1097issueLat=1 1098opClass=SimdFloatCmp 1099opLat=1 1100 1101[system.cpu1.fuPool.FUList5.opList14] 1102type=OpDesc 1103eventq_index=0 1104issueLat=1 1105opClass=SimdFloatCvt 1106opLat=1 1107 1108[system.cpu1.fuPool.FUList5.opList15] 1109type=OpDesc 1110eventq_index=0 1111issueLat=1 1112opClass=SimdFloatDiv 1113opLat=1 1114 1115[system.cpu1.fuPool.FUList5.opList16] 1116type=OpDesc 1117eventq_index=0 1118issueLat=1 1119opClass=SimdFloatMisc 1120opLat=1 1121 1122[system.cpu1.fuPool.FUList5.opList17] 1123type=OpDesc 1124eventq_index=0 1125issueLat=1 1126opClass=SimdFloatMult 1127opLat=1 1128 1129[system.cpu1.fuPool.FUList5.opList18] 1130type=OpDesc 1131eventq_index=0 1132issueLat=1 1133opClass=SimdFloatMultAcc 1134opLat=1 1135 1136[system.cpu1.fuPool.FUList5.opList19] 1137type=OpDesc 1138eventq_index=0 1139issueLat=1 1140opClass=SimdFloatSqrt 1141opLat=1 1142 1143[system.cpu1.fuPool.FUList6] 1144type=FUDesc 1145children=opList 1146count=0 1147eventq_index=0 1148opList=system.cpu1.fuPool.FUList6.opList 1149 1150[system.cpu1.fuPool.FUList6.opList] 1151type=OpDesc 1152eventq_index=0 1153issueLat=1 1154opClass=MemWrite 1155opLat=1 1156 1157[system.cpu1.fuPool.FUList7] 1158type=FUDesc 1159children=opList0 opList1 1160count=4 1161eventq_index=0 1162opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 1163 1164[system.cpu1.fuPool.FUList7.opList0] 1165type=OpDesc 1166eventq_index=0 1167issueLat=1 1168opClass=MemRead 1169opLat=1 1170 1171[system.cpu1.fuPool.FUList7.opList1] 1172type=OpDesc 1173eventq_index=0 1174issueLat=1 1175opClass=MemWrite 1176opLat=1 1177 1178[system.cpu1.fuPool.FUList8] 1179type=FUDesc 1180children=opList 1181count=1 1182eventq_index=0 1183opList=system.cpu1.fuPool.FUList8.opList 1184 1185[system.cpu1.fuPool.FUList8.opList] 1186type=OpDesc 1187eventq_index=0 1188issueLat=3 1189opClass=IprAccess 1190opLat=3 1191 1192[system.cpu1.icache] 1193type=BaseCache 1194children=tags 1195addr_ranges=0:18446744073709551615 1196assoc=1 1197clk_domain=system.cpu_clk_domain 1198eventq_index=0 1199forward_snoops=true 1200hit_latency=2 1201is_top_level=true 1202max_miss_count=0 1203mshrs=4 1204prefetch_on_access=false 1205prefetcher=Null 1206response_latency=2 1207sequential_access=false 1208size=32768 1209system=system 1210tags=system.cpu1.icache.tags 1211tgts_per_mshr=20 1212two_queue=false 1213write_buffers=8 1214cpu_side=system.cpu1.icache_port 1215mem_side=system.toL2Bus.slave[6] 1216 1217[system.cpu1.icache.tags] 1218type=LRU 1219assoc=1 1220block_size=64 1221clk_domain=system.cpu_clk_domain 1222eventq_index=0 1223hit_latency=2 1224sequential_access=false 1225size=32768 1226 1227[system.cpu1.interrupts] 1228type=ArmInterrupts 1229eventq_index=0 1230 1231[system.cpu1.isa] 1232type=ArmISA 1233eventq_index=0 1234fpsid=1090793632 1235id_aa64afr0_el1=0 1236id_aa64afr1_el1=0 1237id_aa64dfr0_el1=1052678 1238id_aa64dfr1_el1=0 1239id_aa64isar0_el1=0 1240id_aa64isar1_el1=0 1241id_aa64mmfr0_el1=15728642 1242id_aa64mmfr1_el1=0 1243id_aa64pfr0_el1=17 1244id_aa64pfr1_el1=0 1245id_isar0=34607377 1246id_isar1=34677009 1247id_isar2=555950401 1248id_isar3=17899825 1249id_isar4=268501314 1250id_isar5=0 1251id_mmfr0=270536963 1252id_mmfr1=0 1253id_mmfr2=19070976 1254id_mmfr3=34611729 1255id_pfr0=49 1256id_pfr1=4113 1257midr=1091551472 1258system=system 1259 1260[system.cpu1.istage2_mmu] 1261type=ArmStage2MMU 1262children=stage2_tlb 1263eventq_index=0 1264stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb 1265tlb=system.cpu1.itb 1266 1267[system.cpu1.istage2_mmu.stage2_tlb] 1268type=ArmTLB 1269children=walker 1270eventq_index=0 1271is_stage2=true 1272size=32 1273walker=system.cpu1.istage2_mmu.stage2_tlb.walker 1274 1275[system.cpu1.istage2_mmu.stage2_tlb.walker] 1276type=ArmTableWalker 1277clk_domain=system.cpu_clk_domain 1278eventq_index=0 1279is_stage2=true 1280num_squash_per_cycle=2 1281sys=system 1282port=system.toL2Bus.slave[10] 1283 1284[system.cpu1.itb] 1285type=ArmTLB 1286children=walker 1287eventq_index=0 1288is_stage2=false 1289size=64 1290walker=system.cpu1.itb.walker 1291 1292[system.cpu1.itb.walker] 1293type=ArmTableWalker 1294clk_domain=system.cpu_clk_domain 1295eventq_index=0 1296is_stage2=false 1297num_squash_per_cycle=2 1298sys=system 1299port=system.toL2Bus.slave[8] 1300 1301[system.cpu1.tracer] 1302type=ExeTracer 1303eventq_index=0 1304 1305[system.cpu_clk_domain] 1306type=SrcClockDomain 1307clock=500 1308eventq_index=0 1309voltage_domain=system.voltage_domain 1310 1311[system.intrctrl] 1312type=IntrControl 1313eventq_index=0 1314sys=system 1315 1316[system.iobus] 1317type=NoncoherentBus 1318clk_domain=system.clk_domain 1319eventq_index=0 1320header_cycles=1 1321use_default_range=false 1322width=8 1323master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side 1324slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 1325 1326[system.iocache] 1327type=BaseCache 1328children=tags 1329addr_ranges=0:134217727 1330assoc=8 1331clk_domain=system.clk_domain 1332eventq_index=0 1333forward_snoops=false 1334hit_latency=50 1335is_top_level=true 1336max_miss_count=0 1337mshrs=20 1338prefetch_on_access=false 1339prefetcher=Null 1340response_latency=50 1341sequential_access=false 1342size=1024 1343system=system 1344tags=system.iocache.tags 1345tgts_per_mshr=12 1346two_queue=false 1347write_buffers=8 1348cpu_side=system.iobus.master[25] 1349mem_side=system.membus.slave[2] 1350 1351[system.iocache.tags] 1352type=LRU 1353assoc=8 1354block_size=64 1355clk_domain=system.clk_domain 1356eventq_index=0 1357hit_latency=50 1358sequential_access=false 1359size=1024 1360 1361[system.l2c] 1362type=BaseCache 1363children=tags 1364addr_ranges=0:18446744073709551615 1365assoc=8 1366clk_domain=system.cpu_clk_domain 1367eventq_index=0 1368forward_snoops=true 1369hit_latency=20 1370is_top_level=false 1371max_miss_count=0 1372mshrs=20 1373prefetch_on_access=false 1374prefetcher=Null 1375response_latency=20 1376sequential_access=false 1377size=4194304 1378system=system 1379tags=system.l2c.tags 1380tgts_per_mshr=12 1381two_queue=false 1382write_buffers=8 1383cpu_side=system.toL2Bus.master[0] 1384mem_side=system.membus.slave[1] 1385 1386[system.l2c.tags] 1387type=LRU 1388assoc=8 1389block_size=64 1390clk_domain=system.cpu_clk_domain 1391eventq_index=0 1392hit_latency=20 1393sequential_access=false 1394size=4194304 1395 1396[system.membus] 1397type=CoherentBus 1398children=badaddr_responder 1399clk_domain=system.clk_domain 1400eventq_index=0 1401header_cycles=1 1402system=system 1403use_default_range=false 1404width=8 1405default=system.membus.badaddr_responder.pio 1406master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port 1407slave=system.system_port system.l2c.mem_side system.iocache.mem_side 1408 1409[system.membus.badaddr_responder] 1410type=IsaFake 1411clk_domain=system.clk_domain 1412eventq_index=0 1413fake_mem=false 1414pio_addr=0 1415pio_latency=100000 1416pio_size=8 1417ret_bad_addr=true 1418ret_data16=65535 1419ret_data32=4294967295 1420ret_data64=18446744073709551615 1421ret_data8=255 1422system=system 1423update_data=false 1424warn_access=warn 1425pio=system.membus.default 1426 1427[system.physmem]
1426type=SimpleDRAM	1428type=DRAMCtrl
1427activation_limit=4	1429activation_limit=4
1428addr_mapping=RaBaChCo	1430addr_mapping=RoRaBaChCo
1429banks_per_rank=8 1430burst_length=8 1431channels=1 1432clk_domain=system.clk_domain 1433conf_table_reported=true 1434device_bus_width=8 1435device_rowbuffer_size=1024 1436devices_per_rank=8 1437eventq_index=0 1438in_addr_map=true	1431banks_per_rank=8 1432burst_length=8 1433channels=1 1434clk_domain=system.clk_domain 1435conf_table_reported=true 1436device_bus_width=8 1437device_rowbuffer_size=1024 1438devices_per_rank=8 1439eventq_index=0 1440in_addr_map=true
	1441max_accesses_per_row=16
1439mem_sched_policy=frfcfs	1442mem_sched_policy=frfcfs
	1443min_writes_per_switch=16
1440null=false	1444null=false
1441page_policy=open	1445page_policy=open_adaptive
1442range=0:134217727 1443ranks_per_channel=2 1444read_buffer_size=32 1445static_backend_latency=10000 1446static_frontend_latency=10000 1447tBURST=5000	1446range=0:134217727 1447ranks_per_channel=2 1448read_buffer_size=32 1449static_backend_latency=10000 1450static_frontend_latency=10000 1451tBURST=5000
	1452tCK=1250
1448tCL=13750 1449tRAS=35000 1450tRCD=13750 1451tREFI=7800000	1453tCL=13750 1454tRAS=35000 1455tRCD=13750 1456tREFI=7800000
1452tRFC=300000	1457tRFC=260000
1453tRP=13750	1458tRP=13750
1454tRRD=6250	1459tRRD=6000 1460tRTP=7500 1461tRTW=2500 1462tWR=15000
1455tWTR=7500	1463tWTR=7500
1456tXAW=40000 1457write_buffer_size=32 1458write_high_thresh_perc=70 1459write_low_thresh_perc=0	1464tXAW=30000 1465write_buffer_size=64 1466write_high_thresh_perc=85 1467write_low_thresh_perc=50
1460port=system.membus.master[6] 1461 1462[system.realview] 1463type=RealView 1464children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake 1465eventq_index=0 1466intrctrl=system.intrctrl 1467max_mem_size=268435456 1468mem_start_addr=0 1469pci_cfg_base=0 1470system=system 1471 1472[system.realview.a9scu] 1473type=A9SCU 1474clk_domain=system.clk_domain 1475eventq_index=0 1476pio_addr=520093696 1477pio_latency=100000 1478system=system 1479pio=system.membus.master[4] 1480 1481[system.realview.aaci_fake] 1482type=AmbaFake 1483amba_id=0 1484clk_domain=system.clk_domain 1485eventq_index=0 1486ignore_access=false 1487pio_addr=268451840 1488pio_latency=100000 1489system=system 1490pio=system.iobus.master[21] 1491 1492[system.realview.cf_ctrl] 1493type=IdeController 1494BAR0=402653184 1495BAR0LegacyIO=true 1496BAR0Size=16 1497BAR1=402653440 1498BAR1LegacyIO=true 1499BAR1Size=1 1500BAR2=1 1501BAR2LegacyIO=false 1502BAR2Size=8 1503BAR3=1 1504BAR3LegacyIO=false 1505BAR3Size=4 1506BAR4=1 1507BAR4LegacyIO=false 1508BAR4Size=16 1509BAR5=1 1510BAR5LegacyIO=false 1511BAR5Size=0 1512BIST=0 1513CacheLineSize=0 1514CapabilityPtr=0 1515CardbusCIS=0 1516ClassCode=1 1517Command=1 1518DeviceID=28945 1519ExpansionROM=0 1520HeaderType=0 1521InterruptLine=31 1522InterruptPin=1 1523LatencyTimer=0 1524MSICAPBaseOffset=0 1525MSICAPCapId=0 1526MSICAPMaskBits=0 1527MSICAPMsgAddr=0 1528MSICAPMsgCtrl=0 1529MSICAPMsgData=0 1530MSICAPMsgUpperAddr=0 1531MSICAPNextCapability=0 1532MSICAPPendingBits=0 1533MSIXCAPBaseOffset=0 1534MSIXCAPCapId=0 1535MSIXCAPNextCapability=0 1536MSIXMsgCtrl=0 1537MSIXPbaOffset=0 1538MSIXTableOffset=0 1539MaximumLatency=0 1540MinimumGrant=0 1541PMCAPBaseOffset=0 1542PMCAPCapId=0 1543PMCAPCapabilities=0 1544PMCAPCtrlStatus=0 1545PMCAPNextCapability=0 1546PXCAPBaseOffset=0 1547PXCAPCapId=0 1548PXCAPCapabilities=0 1549PXCAPDevCap2=0 1550PXCAPDevCapabilities=0 1551PXCAPDevCtrl=0 1552PXCAPDevCtrl2=0 1553PXCAPDevStatus=0 1554PXCAPLinkCap=0 1555PXCAPLinkCtrl=0 1556PXCAPLinkStatus=0 1557PXCAPNextCapability=0 1558ProgIF=133 1559Revision=0 1560Status=640 1561SubClassCode=1 1562SubsystemID=0 1563SubsystemVendorID=0 1564VendorID=32902 1565clk_domain=system.clk_domain 1566config_latency=20000 1567ctrl_offset=2 1568disks=system.cf0 1569eventq_index=0 1570io_shift=1 1571pci_bus=2 1572pci_dev=7 1573pci_func=0 1574pio_latency=30000 1575platform=system.realview 1576system=system 1577config=system.iobus.master[8] 1578dma=system.iobus.slave[2] 1579pio=system.iobus.master[7] 1580 1581[system.realview.clcd] 1582type=Pl111 1583amba_id=1315089 1584clk_domain=system.clk_domain 1585enable_capture=true 1586eventq_index=0 1587gic=system.realview.gic 1588int_num=55 1589pio_addr=268566528 1590pio_latency=10000 1591pixel_clock=41667 1592system=system 1593vnc=system.vncserver 1594dma=system.iobus.slave[1] 1595pio=system.iobus.master[4] 1596 1597[system.realview.dmac_fake] 1598type=AmbaFake 1599amba_id=0 1600clk_domain=system.clk_domain 1601eventq_index=0 1602ignore_access=false 1603pio_addr=268632064 1604pio_latency=100000 1605system=system 1606pio=system.iobus.master[9] 1607 1608[system.realview.flash_fake] 1609type=IsaFake 1610clk_domain=system.clk_domain 1611eventq_index=0 1612fake_mem=true 1613pio_addr=1073741824 1614pio_latency=100000 1615pio_size=536870912 1616ret_bad_addr=false 1617ret_data16=65535 1618ret_data32=4294967295 1619ret_data64=18446744073709551615 1620ret_data8=255 1621system=system 1622update_data=false 1623warn_access= 1624pio=system.iobus.master[24] 1625 1626[system.realview.gic] 1627type=Pl390 1628clk_domain=system.clk_domain 1629cpu_addr=520093952 1630cpu_pio_delay=10000 1631dist_addr=520097792 1632dist_pio_delay=10000 1633eventq_index=0 1634int_latency=10000 1635it_lines=128 1636msix_addr=0 1637platform=system.realview 1638system=system 1639pio=system.membus.master[2] 1640 1641[system.realview.gpio0_fake] 1642type=AmbaFake 1643amba_id=0 1644clk_domain=system.clk_domain 1645eventq_index=0 1646ignore_access=false 1647pio_addr=268513280 1648pio_latency=100000 1649system=system 1650pio=system.iobus.master[16] 1651 1652[system.realview.gpio1_fake] 1653type=AmbaFake 1654amba_id=0 1655clk_domain=system.clk_domain 1656eventq_index=0 1657ignore_access=false 1658pio_addr=268517376 1659pio_latency=100000 1660system=system 1661pio=system.iobus.master[17] 1662 1663[system.realview.gpio2_fake] 1664type=AmbaFake 1665amba_id=0 1666clk_domain=system.clk_domain 1667eventq_index=0 1668ignore_access=false 1669pio_addr=268521472 1670pio_latency=100000 1671system=system 1672pio=system.iobus.master[18] 1673 1674[system.realview.kmi0] 1675type=Pl050 1676amba_id=1314896 1677clk_domain=system.clk_domain 1678eventq_index=0 1679gic=system.realview.gic 1680int_delay=1000000 1681int_num=52 1682is_mouse=false 1683pio_addr=268460032 1684pio_latency=100000 1685system=system 1686vnc=system.vncserver 1687pio=system.iobus.master[5] 1688 1689[system.realview.kmi1] 1690type=Pl050 1691amba_id=1314896 1692clk_domain=system.clk_domain 1693eventq_index=0 1694gic=system.realview.gic 1695int_delay=1000000 1696int_num=53 1697is_mouse=true 1698pio_addr=268464128 1699pio_latency=100000 1700system=system 1701vnc=system.vncserver 1702pio=system.iobus.master[6] 1703 1704[system.realview.l2x0_fake] 1705type=IsaFake 1706clk_domain=system.clk_domain 1707eventq_index=0 1708fake_mem=false 1709pio_addr=520101888 1710pio_latency=100000 1711pio_size=4095 1712ret_bad_addr=false 1713ret_data16=65535 1714ret_data32=4294967295 1715ret_data64=18446744073709551615 1716ret_data8=255 1717system=system 1718update_data=false 1719warn_access= 1720pio=system.membus.master[3] 1721 1722[system.realview.local_cpu_timer] 1723type=CpuLocalTimer 1724clk_domain=system.clk_domain 1725eventq_index=0 1726gic=system.realview.gic 1727int_num_timer=29 1728int_num_watchdog=30 1729pio_addr=520095232 1730pio_latency=100000 1731system=system 1732pio=system.membus.master[5] 1733 1734[system.realview.mmc_fake] 1735type=AmbaFake 1736amba_id=0 1737clk_domain=system.clk_domain 1738eventq_index=0 1739ignore_access=false 1740pio_addr=268455936 1741pio_latency=100000 1742system=system 1743pio=system.iobus.master[22] 1744 1745[system.realview.nvmem] 1746type=SimpleMemory 1747bandwidth=73.000000 1748clk_domain=system.clk_domain 1749conf_table_reported=false 1750eventq_index=0 1751in_addr_map=true 1752latency=30000 1753latency_var=0 1754null=false 1755range=2147483648:2214592511 1756port=system.membus.master[1] 1757 1758[system.realview.realview_io] 1759type=RealViewCtrl 1760clk_domain=system.clk_domain 1761eventq_index=0 1762idreg=0 1763pio_addr=268435456 1764pio_latency=100000 1765proc_id0=201326592 1766proc_id1=201327138 1767system=system 1768pio=system.iobus.master[1] 1769 1770[system.realview.rtc] 1771type=PL031 1772amba_id=3412017 1773clk_domain=system.clk_domain 1774eventq_index=0 1775gic=system.realview.gic 1776int_delay=100000 1777int_num=42 1778pio_addr=268529664 1779pio_latency=100000 1780system=system 1781time=Thu Jan 1 00:00:00 2009 1782pio=system.iobus.master[23] 1783 1784[system.realview.sci_fake] 1785type=AmbaFake 1786amba_id=0 1787clk_domain=system.clk_domain 1788eventq_index=0 1789ignore_access=false 1790pio_addr=268492800 1791pio_latency=100000 1792system=system 1793pio=system.iobus.master[20] 1794 1795[system.realview.smc_fake] 1796type=AmbaFake 1797amba_id=0 1798clk_domain=system.clk_domain 1799eventq_index=0 1800ignore_access=false 1801pio_addr=269357056 1802pio_latency=100000 1803system=system 1804pio=system.iobus.master[13] 1805 1806[system.realview.sp810_fake] 1807type=AmbaFake 1808amba_id=0 1809clk_domain=system.clk_domain 1810eventq_index=0 1811ignore_access=true 1812pio_addr=268439552 1813pio_latency=100000 1814system=system 1815pio=system.iobus.master[14] 1816 1817[system.realview.ssp_fake] 1818type=AmbaFake 1819amba_id=0 1820clk_domain=system.clk_domain 1821eventq_index=0 1822ignore_access=false 1823pio_addr=268488704 1824pio_latency=100000 1825system=system 1826pio=system.iobus.master[19] 1827 1828[system.realview.timer0] 1829type=Sp804 1830amba_id=1316868 1831clk_domain=system.clk_domain 1832clock0=1000000 1833clock1=1000000 1834eventq_index=0 1835gic=system.realview.gic 1836int_num0=36 1837int_num1=36 1838pio_addr=268505088 1839pio_latency=100000 1840system=system 1841pio=system.iobus.master[2] 1842 1843[system.realview.timer1] 1844type=Sp804 1845amba_id=1316868 1846clk_domain=system.clk_domain 1847clock0=1000000 1848clock1=1000000 1849eventq_index=0 1850gic=system.realview.gic 1851int_num0=37 1852int_num1=37 1853pio_addr=268509184 1854pio_latency=100000 1855system=system 1856pio=system.iobus.master[3] 1857 1858[system.realview.uart] 1859type=Pl011 1860clk_domain=system.clk_domain 1861end_on_eot=false 1862eventq_index=0 1863gic=system.realview.gic 1864int_delay=100000 1865int_num=44 1866pio_addr=268472320 1867pio_latency=100000 1868platform=system.realview 1869system=system 1870terminal=system.terminal 1871pio=system.iobus.master[0] 1872 1873[system.realview.uart1_fake] 1874type=AmbaFake 1875amba_id=0 1876clk_domain=system.clk_domain 1877eventq_index=0 1878ignore_access=false 1879pio_addr=268476416 1880pio_latency=100000 1881system=system 1882pio=system.iobus.master[10] 1883 1884[system.realview.uart2_fake] 1885type=AmbaFake 1886amba_id=0 1887clk_domain=system.clk_domain 1888eventq_index=0 1889ignore_access=false 1890pio_addr=268480512 1891pio_latency=100000 1892system=system 1893pio=system.iobus.master[11] 1894 1895[system.realview.uart3_fake] 1896type=AmbaFake 1897amba_id=0 1898clk_domain=system.clk_domain 1899eventq_index=0 1900ignore_access=false 1901pio_addr=268484608 1902pio_latency=100000 1903system=system 1904pio=system.iobus.master[12] 1905 1906[system.realview.watchdog_fake] 1907type=AmbaFake 1908amba_id=0 1909clk_domain=system.clk_domain 1910eventq_index=0 1911ignore_access=false 1912pio_addr=268500992 1913pio_latency=100000 1914system=system 1915pio=system.iobus.master[15] 1916 1917[system.terminal] 1918type=Terminal 1919eventq_index=0 1920intr_control=system.intrctrl 1921number=0 1922output=true 1923port=3456 1924 1925[system.toL2Bus] 1926type=CoherentBus 1927clk_domain=system.cpu_clk_domain 1928eventq_index=0 1929header_cycles=1 1930system=system 1931use_default_range=false 1932width=8 1933master=system.l2c.cpu_side 1934slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port 1935 1936[system.vncserver] 1937type=VncServer 1938eventq_index=0 1939frame_capture=false 1940number=0 1941port=5900 1942 1943[system.voltage_domain] 1944type=VoltageDomain 1945eventq_index=0 1946voltage=1.000000 1947	1468port=system.membus.master[6] 1469 1470[system.realview] 1471type=RealView 1472children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake 1473eventq_index=0 1474intrctrl=system.intrctrl 1475max_mem_size=268435456 1476mem_start_addr=0 1477pci_cfg_base=0 1478system=system 1479 1480[system.realview.a9scu] 1481type=A9SCU 1482clk_domain=system.clk_domain 1483eventq_index=0 1484pio_addr=520093696 1485pio_latency=100000 1486system=system 1487pio=system.membus.master[4] 1488 1489[system.realview.aaci_fake] 1490type=AmbaFake 1491amba_id=0 1492clk_domain=system.clk_domain 1493eventq_index=0 1494ignore_access=false 1495pio_addr=268451840 1496pio_latency=100000 1497system=system 1498pio=system.iobus.master[21] 1499 1500[system.realview.cf_ctrl] 1501type=IdeController 1502BAR0=402653184 1503BAR0LegacyIO=true 1504BAR0Size=16 1505BAR1=402653440 1506BAR1LegacyIO=true 1507BAR1Size=1 1508BAR2=1 1509BAR2LegacyIO=false 1510BAR2Size=8 1511BAR3=1 1512BAR3LegacyIO=false 1513BAR3Size=4 1514BAR4=1 1515BAR4LegacyIO=false 1516BAR4Size=16 1517BAR5=1 1518BAR5LegacyIO=false 1519BAR5Size=0 1520BIST=0 1521CacheLineSize=0 1522CapabilityPtr=0 1523CardbusCIS=0 1524ClassCode=1 1525Command=1 1526DeviceID=28945 1527ExpansionROM=0 1528HeaderType=0 1529InterruptLine=31 1530InterruptPin=1 1531LatencyTimer=0 1532MSICAPBaseOffset=0 1533MSICAPCapId=0 1534MSICAPMaskBits=0 1535MSICAPMsgAddr=0 1536MSICAPMsgCtrl=0 1537MSICAPMsgData=0 1538MSICAPMsgUpperAddr=0 1539MSICAPNextCapability=0 1540MSICAPPendingBits=0 1541MSIXCAPBaseOffset=0 1542MSIXCAPCapId=0 1543MSIXCAPNextCapability=0 1544MSIXMsgCtrl=0 1545MSIXPbaOffset=0 1546MSIXTableOffset=0 1547MaximumLatency=0 1548MinimumGrant=0 1549PMCAPBaseOffset=0 1550PMCAPCapId=0 1551PMCAPCapabilities=0 1552PMCAPCtrlStatus=0 1553PMCAPNextCapability=0 1554PXCAPBaseOffset=0 1555PXCAPCapId=0 1556PXCAPCapabilities=0 1557PXCAPDevCap2=0 1558PXCAPDevCapabilities=0 1559PXCAPDevCtrl=0 1560PXCAPDevCtrl2=0 1561PXCAPDevStatus=0 1562PXCAPLinkCap=0 1563PXCAPLinkCtrl=0 1564PXCAPLinkStatus=0 1565PXCAPNextCapability=0 1566ProgIF=133 1567Revision=0 1568Status=640 1569SubClassCode=1 1570SubsystemID=0 1571SubsystemVendorID=0 1572VendorID=32902 1573clk_domain=system.clk_domain 1574config_latency=20000 1575ctrl_offset=2 1576disks=system.cf0 1577eventq_index=0 1578io_shift=1 1579pci_bus=2 1580pci_dev=7 1581pci_func=0 1582pio_latency=30000 1583platform=system.realview 1584system=system 1585config=system.iobus.master[8] 1586dma=system.iobus.slave[2] 1587pio=system.iobus.master[7] 1588 1589[system.realview.clcd] 1590type=Pl111 1591amba_id=1315089 1592clk_domain=system.clk_domain 1593enable_capture=true 1594eventq_index=0 1595gic=system.realview.gic 1596int_num=55 1597pio_addr=268566528 1598pio_latency=10000 1599pixel_clock=41667 1600system=system 1601vnc=system.vncserver 1602dma=system.iobus.slave[1] 1603pio=system.iobus.master[4] 1604 1605[system.realview.dmac_fake] 1606type=AmbaFake 1607amba_id=0 1608clk_domain=system.clk_domain 1609eventq_index=0 1610ignore_access=false 1611pio_addr=268632064 1612pio_latency=100000 1613system=system 1614pio=system.iobus.master[9] 1615 1616[system.realview.flash_fake] 1617type=IsaFake 1618clk_domain=system.clk_domain 1619eventq_index=0 1620fake_mem=true 1621pio_addr=1073741824 1622pio_latency=100000 1623pio_size=536870912 1624ret_bad_addr=false 1625ret_data16=65535 1626ret_data32=4294967295 1627ret_data64=18446744073709551615 1628ret_data8=255 1629system=system 1630update_data=false 1631warn_access= 1632pio=system.iobus.master[24] 1633 1634[system.realview.gic] 1635type=Pl390 1636clk_domain=system.clk_domain 1637cpu_addr=520093952 1638cpu_pio_delay=10000 1639dist_addr=520097792 1640dist_pio_delay=10000 1641eventq_index=0 1642int_latency=10000 1643it_lines=128 1644msix_addr=0 1645platform=system.realview 1646system=system 1647pio=system.membus.master[2] 1648 1649[system.realview.gpio0_fake] 1650type=AmbaFake 1651amba_id=0 1652clk_domain=system.clk_domain 1653eventq_index=0 1654ignore_access=false 1655pio_addr=268513280 1656pio_latency=100000 1657system=system 1658pio=system.iobus.master[16] 1659 1660[system.realview.gpio1_fake] 1661type=AmbaFake 1662amba_id=0 1663clk_domain=system.clk_domain 1664eventq_index=0 1665ignore_access=false 1666pio_addr=268517376 1667pio_latency=100000 1668system=system 1669pio=system.iobus.master[17] 1670 1671[system.realview.gpio2_fake] 1672type=AmbaFake 1673amba_id=0 1674clk_domain=system.clk_domain 1675eventq_index=0 1676ignore_access=false 1677pio_addr=268521472 1678pio_latency=100000 1679system=system 1680pio=system.iobus.master[18] 1681 1682[system.realview.kmi0] 1683type=Pl050 1684amba_id=1314896 1685clk_domain=system.clk_domain 1686eventq_index=0 1687gic=system.realview.gic 1688int_delay=1000000 1689int_num=52 1690is_mouse=false 1691pio_addr=268460032 1692pio_latency=100000 1693system=system 1694vnc=system.vncserver 1695pio=system.iobus.master[5] 1696 1697[system.realview.kmi1] 1698type=Pl050 1699amba_id=1314896 1700clk_domain=system.clk_domain 1701eventq_index=0 1702gic=system.realview.gic 1703int_delay=1000000 1704int_num=53 1705is_mouse=true 1706pio_addr=268464128 1707pio_latency=100000 1708system=system 1709vnc=system.vncserver 1710pio=system.iobus.master[6] 1711 1712[system.realview.l2x0_fake] 1713type=IsaFake 1714clk_domain=system.clk_domain 1715eventq_index=0 1716fake_mem=false 1717pio_addr=520101888 1718pio_latency=100000 1719pio_size=4095 1720ret_bad_addr=false 1721ret_data16=65535 1722ret_data32=4294967295 1723ret_data64=18446744073709551615 1724ret_data8=255 1725system=system 1726update_data=false 1727warn_access= 1728pio=system.membus.master[3] 1729 1730[system.realview.local_cpu_timer] 1731type=CpuLocalTimer 1732clk_domain=system.clk_domain 1733eventq_index=0 1734gic=system.realview.gic 1735int_num_timer=29 1736int_num_watchdog=30 1737pio_addr=520095232 1738pio_latency=100000 1739system=system 1740pio=system.membus.master[5] 1741 1742[system.realview.mmc_fake] 1743type=AmbaFake 1744amba_id=0 1745clk_domain=system.clk_domain 1746eventq_index=0 1747ignore_access=false 1748pio_addr=268455936 1749pio_latency=100000 1750system=system 1751pio=system.iobus.master[22] 1752 1753[system.realview.nvmem] 1754type=SimpleMemory 1755bandwidth=73.000000 1756clk_domain=system.clk_domain 1757conf_table_reported=false 1758eventq_index=0 1759in_addr_map=true 1760latency=30000 1761latency_var=0 1762null=false 1763range=2147483648:2214592511 1764port=system.membus.master[1] 1765 1766[system.realview.realview_io] 1767type=RealViewCtrl 1768clk_domain=system.clk_domain 1769eventq_index=0 1770idreg=0 1771pio_addr=268435456 1772pio_latency=100000 1773proc_id0=201326592 1774proc_id1=201327138 1775system=system 1776pio=system.iobus.master[1] 1777 1778[system.realview.rtc] 1779type=PL031 1780amba_id=3412017 1781clk_domain=system.clk_domain 1782eventq_index=0 1783gic=system.realview.gic 1784int_delay=100000 1785int_num=42 1786pio_addr=268529664 1787pio_latency=100000 1788system=system 1789time=Thu Jan 1 00:00:00 2009 1790pio=system.iobus.master[23] 1791 1792[system.realview.sci_fake] 1793type=AmbaFake 1794amba_id=0 1795clk_domain=system.clk_domain 1796eventq_index=0 1797ignore_access=false 1798pio_addr=268492800 1799pio_latency=100000 1800system=system 1801pio=system.iobus.master[20] 1802 1803[system.realview.smc_fake] 1804type=AmbaFake 1805amba_id=0 1806clk_domain=system.clk_domain 1807eventq_index=0 1808ignore_access=false 1809pio_addr=269357056 1810pio_latency=100000 1811system=system 1812pio=system.iobus.master[13] 1813 1814[system.realview.sp810_fake] 1815type=AmbaFake 1816amba_id=0 1817clk_domain=system.clk_domain 1818eventq_index=0 1819ignore_access=true 1820pio_addr=268439552 1821pio_latency=100000 1822system=system 1823pio=system.iobus.master[14] 1824 1825[system.realview.ssp_fake] 1826type=AmbaFake 1827amba_id=0 1828clk_domain=system.clk_domain 1829eventq_index=0 1830ignore_access=false 1831pio_addr=268488704 1832pio_latency=100000 1833system=system 1834pio=system.iobus.master[19] 1835 1836[system.realview.timer0] 1837type=Sp804 1838amba_id=1316868 1839clk_domain=system.clk_domain 1840clock0=1000000 1841clock1=1000000 1842eventq_index=0 1843gic=system.realview.gic 1844int_num0=36 1845int_num1=36 1846pio_addr=268505088 1847pio_latency=100000 1848system=system 1849pio=system.iobus.master[2] 1850 1851[system.realview.timer1] 1852type=Sp804 1853amba_id=1316868 1854clk_domain=system.clk_domain 1855clock0=1000000 1856clock1=1000000 1857eventq_index=0 1858gic=system.realview.gic 1859int_num0=37 1860int_num1=37 1861pio_addr=268509184 1862pio_latency=100000 1863system=system 1864pio=system.iobus.master[3] 1865 1866[system.realview.uart] 1867type=Pl011 1868clk_domain=system.clk_domain 1869end_on_eot=false 1870eventq_index=0 1871gic=system.realview.gic 1872int_delay=100000 1873int_num=44 1874pio_addr=268472320 1875pio_latency=100000 1876platform=system.realview 1877system=system 1878terminal=system.terminal 1879pio=system.iobus.master[0] 1880 1881[system.realview.uart1_fake] 1882type=AmbaFake 1883amba_id=0 1884clk_domain=system.clk_domain 1885eventq_index=0 1886ignore_access=false 1887pio_addr=268476416 1888pio_latency=100000 1889system=system 1890pio=system.iobus.master[10] 1891 1892[system.realview.uart2_fake] 1893type=AmbaFake 1894amba_id=0 1895clk_domain=system.clk_domain 1896eventq_index=0 1897ignore_access=false 1898pio_addr=268480512 1899pio_latency=100000 1900system=system 1901pio=system.iobus.master[11] 1902 1903[system.realview.uart3_fake] 1904type=AmbaFake 1905amba_id=0 1906clk_domain=system.clk_domain 1907eventq_index=0 1908ignore_access=false 1909pio_addr=268484608 1910pio_latency=100000 1911system=system 1912pio=system.iobus.master[12] 1913 1914[system.realview.watchdog_fake] 1915type=AmbaFake 1916amba_id=0 1917clk_domain=system.clk_domain 1918eventq_index=0 1919ignore_access=false 1920pio_addr=268500992 1921pio_latency=100000 1922system=system 1923pio=system.iobus.master[15] 1924 1925[system.terminal] 1926type=Terminal 1927eventq_index=0 1928intr_control=system.intrctrl 1929number=0 1930output=true 1931port=3456 1932 1933[system.toL2Bus] 1934type=CoherentBus 1935clk_domain=system.cpu_clk_domain 1936eventq_index=0 1937header_cycles=1 1938system=system 1939use_default_range=false 1940width=8 1941master=system.l2c.cpu_side 1942slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port 1943 1944[system.vncserver] 1945type=VncServer 1946eventq_index=0 1947frame_capture=false 1948number=0 1949port=5900 1950 1951[system.voltage_domain] 1952type=VoltageDomain 1953eventq_index=0 1954voltage=1.000000 1955