1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=true
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
9time_sync_spin_threshold=100000000
10
11[system]
12type=LinuxArmSystem
13children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
14atags_addr=134217728
15boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
16boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
17cache_line_size=64
18clk_domain=system.clk_domain
19default_p_state=UNDEFINED
20dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
21early_kernel_symbols=false
22enable_context_switch_stats_dump=false
23eventq_index=0
24exit_on_work_items=false
25flags_addr=469827632
26gic_cpu_addr=738205696
27have_large_asid_64=false
28have_lpae=true
29have_security=false
30have_virtualization=false
31highest_el_is_64=false
32init_param=0
33kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
34kernel_addr_check=true
35load_addr_mask=268435455
36load_offset=2147483648
37machine_type=VExpress_EMM
38mem_mode=timing
39mem_ranges=2147483648:2415919103:0:0:0:0
40memories=system.physmem system.realview.nvmem system.realview.vram
41mmap_using_noreserve=false
42multi_proc=true
43multi_thread=false
44num_work_ids=16
45p_state_clk_gate_bins=20
46p_state_clk_gate_max=1000000000000
47p_state_clk_gate_min=1000
48panic_on_oops=true
49panic_on_panic=true
50phys_addr_range_64=40
51power_model=Null
52readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
53reset_addr_64=0
54symbolfile=
55thermal_components=
56thermal_model=Null
57work_begin_ckpt_count=0
58work_begin_cpu_id_exit=-1
59work_begin_exit_count=0
60work_cpus_ckpt_count=0
--- 33 unchanged lines hidden (view full) ---
94eventq_index=0
95image_file=
96read_only=false
97table_size=65536
98
99[system.cf0.image.child]
100type=RawDiskImage
101eventq_index=0
102image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
103read_only=true
104
105[system.clk_domain]
106type=SrcClockDomain
107clock=1000
108domain_id=-1
109eventq_index=0
110init_perf_level=0
--- 6 unchanged lines hidden (view full) ---
117LQEntries=16
118LSQCheckLoads=true
119LSQDepCheckShift=0
120SQEntries=16
121SSITSize=1024
122activity=0
123backComSize=5
124branchPred=system.cpu0.branchPred
125cacheStorePorts=200
126checker=Null
127clk_domain=system.cpu_clk_domain
128commitToDecodeDelay=1
129commitToFetchDelay=1
130commitToIEWDelay=1
131commitToRenameDelay=1
132commitWidth=8
133cpu_id=0
--- 59 unchanged lines hidden (view full) ---
193smtLSQThreshold=100
194smtNumFetchingThreads=1
195smtROBPolicy=Partitioned
196smtROBThreshold=100
197socket_id=0
198squashWidth=8
199store_set_clear_period=250000
200switched_out=false
201syscallRetryLatency=10000
202system=system
203tracer=system.cpu0.tracer
204trapLatency=13
205wbWidth=8
206workload=
207dcache_port=system.cpu0.dcache.cpu_side
208icache_port=system.cpu0.icache.cpu_side
209
--- 19 unchanged lines hidden (view full) ---
229
230[system.cpu0.dcache]
231type=Cache
232children=tags
233addr_ranges=0:18446744073709551615:0:0:0:0
234assoc=2
235clk_domain=system.cpu_clk_domain
236clusivity=mostly_incl
237data_latency=2
238default_p_state=UNDEFINED
239demand_mshr_reserve=1
240eventq_index=0
241is_read_only=false
242max_miss_count=0
243mshrs=6
244p_state_clk_gate_bins=20
245p_state_clk_gate_max=1000000000000
246p_state_clk_gate_min=1000
247power_model=Null
248prefetch_on_access=false
249prefetcher=Null
250response_latency=2
251sequential_access=false
252size=32768
253system=system
254tag_latency=2
255tags=system.cpu0.dcache.tags
256tgts_per_mshr=8
257write_buffers=16
258writeback_clean=true
259cpu_side=system.cpu0.dcache_port
260mem_side=system.cpu0.toL2Bus.slave[1]
261
262[system.cpu0.dcache.tags]
263type=LRU
264assoc=2
265block_size=64
266clk_domain=system.cpu_clk_domain
267data_latency=2
268default_p_state=UNDEFINED
269eventq_index=0
270p_state_clk_gate_bins=20
271p_state_clk_gate_max=1000000000000
272p_state_clk_gate_min=1000
273power_model=Null
274sequential_access=false
275size=32768
276tag_latency=2
277
278[system.cpu0.dstage2_mmu]
279type=ArmStage2MMU
280children=stage2_tlb
281eventq_index=0
282stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
283sys=system
284tlb=system.cpu0.dtb
--- 86 unchanged lines hidden (view full) ---
371type=OpDesc
372eventq_index=0
373opClass=IprAccess
374opLat=3
375pipelined=true
376
377[system.cpu0.fuPool.FUList2]
378type=FUDesc
379children=opList0 opList1
380count=1
381eventq_index=0
382opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1
383
384[system.cpu0.fuPool.FUList2.opList0]
385type=OpDesc
386eventq_index=0
387opClass=MemRead
388opLat=2
389pipelined=true
390
391[system.cpu0.fuPool.FUList2.opList1]
392type=OpDesc
393eventq_index=0
394opClass=FloatMemRead
395opLat=2
396pipelined=true
397
398[system.cpu0.fuPool.FUList3]
399type=FUDesc
400children=opList0 opList1
401count=1
402eventq_index=0
403opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1
404
405[system.cpu0.fuPool.FUList3.opList0]
406type=OpDesc
407eventq_index=0
408opClass=MemWrite
409opLat=2
410pipelined=true
411
412[system.cpu0.fuPool.FUList3.opList1]
413type=OpDesc
414eventq_index=0
415opClass=FloatMemWrite
416opLat=2
417pipelined=true
418
419[system.cpu0.fuPool.FUList4]
420type=FUDesc
421children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
422count=2
423eventq_index=0
424opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 system.cpu0.fuPool.FUList4.opList02 system.cpu0.fuPool.FUList4.opList03 system.cpu0.fuPool.FUList4.opList04 system.cpu0.fuPool.FUList4.opList05 system.cpu0.fuPool.FUList4.opList06 system.cpu0.fuPool.FUList4.opList07 system.cpu0.fuPool.FUList4.opList08 system.cpu0.fuPool.FUList4.opList09 system.cpu0.fuPool.FUList4.opList10 system.cpu0.fuPool.FUList4.opList11 system.cpu0.fuPool.FUList4.opList12 system.cpu0.fuPool.FUList4.opList13 system.cpu0.fuPool.FUList4.opList14 system.cpu0.fuPool.FUList4.opList15 system.cpu0.fuPool.FUList4.opList16 system.cpu0.fuPool.FUList4.opList17 system.cpu0.fuPool.FUList4.opList18 system.cpu0.fuPool.FUList4.opList19 system.cpu0.fuPool.FUList4.opList20 system.cpu0.fuPool.FUList4.opList21 system.cpu0.fuPool.FUList4.opList22 system.cpu0.fuPool.FUList4.opList23 system.cpu0.fuPool.FUList4.opList24 system.cpu0.fuPool.FUList4.opList25 system.cpu0.fuPool.FUList4.opList26 system.cpu0.fuPool.FUList4.opList27
425
426[system.cpu0.fuPool.FUList4.opList00]
427type=OpDesc
428eventq_index=0
429opClass=SimdAdd
430opLat=4
431pipelined=true
432
--- 115 unchanged lines hidden (view full) ---
548opClass=SimdFloatMult
549opLat=3
550pipelined=true
551
552[system.cpu0.fuPool.FUList4.opList18]
553type=OpDesc
554eventq_index=0
555opClass=SimdFloatMultAcc
556opLat=5
557pipelined=true
558
559[system.cpu0.fuPool.FUList4.opList19]
560type=OpDesc
561eventq_index=0
562opClass=SimdFloatSqrt
563opLat=9
564pipelined=true
--- 35 unchanged lines hidden (view full) ---
600
601[system.cpu0.fuPool.FUList4.opList25]
602type=OpDesc
603eventq_index=0
604opClass=FloatMult
605opLat=4
606pipelined=true
607
608[system.cpu0.fuPool.FUList4.opList26]
609type=OpDesc
610eventq_index=0
611opClass=FloatMultAcc
612opLat=5
613pipelined=true
614
615[system.cpu0.fuPool.FUList4.opList27]
616type=OpDesc
617eventq_index=0
618opClass=FloatMisc
619opLat=3
620pipelined=true
621
622[system.cpu0.icache]
623type=Cache
624children=tags
625addr_ranges=0:18446744073709551615:0:0:0:0
626assoc=2
627clk_domain=system.cpu_clk_domain
628clusivity=mostly_incl
629data_latency=1
630default_p_state=UNDEFINED
631demand_mshr_reserve=1
632eventq_index=0
633is_read_only=true
634max_miss_count=0
635mshrs=2
636p_state_clk_gate_bins=20
637p_state_clk_gate_max=1000000000000
638p_state_clk_gate_min=1000
639power_model=Null
640prefetch_on_access=false
641prefetcher=Null
642response_latency=1
643sequential_access=false
644size=32768
645system=system
646tag_latency=1
647tags=system.cpu0.icache.tags
648tgts_per_mshr=8
649write_buffers=8
650writeback_clean=true
651cpu_side=system.cpu0.icache_port
652mem_side=system.cpu0.toL2Bus.slave[0]
653
654[system.cpu0.icache.tags]
655type=LRU
656assoc=2
657block_size=64
658clk_domain=system.cpu_clk_domain
659data_latency=1
660default_p_state=UNDEFINED
661eventq_index=0
662p_state_clk_gate_bins=20
663p_state_clk_gate_max=1000000000000
664p_state_clk_gate_min=1000
665power_model=Null
666sequential_access=false
667size=32768
668tag_latency=1
669
670[system.cpu0.interrupts]
671type=ArmInterrupts
672eventq_index=0
673
674[system.cpu0.isa]
675type=ArmISA
676decoderFlavour=Generic
677eventq_index=0
678fpsid=1090793632
679id_aa64afr0_el1=0
680id_aa64afr1_el1=0
681id_aa64dfr0_el1=1052678
682id_aa64dfr1_el1=0
683id_aa64isar0_el1=0
684id_aa64isar1_el1=0
685id_aa64mmfr0_el1=15728642
686id_aa64mmfr1_el1=0
687id_isar0=34607377
688id_isar1=34677009
689id_isar2=555950401
690id_isar3=17899825
691id_isar4=268501314
692id_isar5=0
693id_mmfr0=270536963
694id_mmfr1=0
695id_mmfr2=19070976
696id_mmfr3=34611729
697midr=1091551472
698pmu=Null
699system=system
700
701[system.cpu0.istage2_mmu]
702type=ArmStage2MMU
703children=stage2_tlb
704eventq_index=0
--- 46 unchanged lines hidden (view full) ---
751
752[system.cpu0.l2cache]
753type=Cache
754children=prefetcher tags
755addr_ranges=0:18446744073709551615:0:0:0:0
756assoc=16
757clk_domain=system.cpu_clk_domain
758clusivity=mostly_excl
759data_latency=12
760default_p_state=UNDEFINED
761demand_mshr_reserve=1
762eventq_index=0
763is_read_only=false
764max_miss_count=0
765mshrs=16
766p_state_clk_gate_bins=20
767p_state_clk_gate_max=1000000000000
768p_state_clk_gate_min=1000
769power_model=Null
770prefetch_on_access=true
771prefetcher=system.cpu0.l2cache.prefetcher
772response_latency=12
773sequential_access=false
774size=1048576
775system=system
776tag_latency=12
777tags=system.cpu0.l2cache.tags
778tgts_per_mshr=8
779write_buffers=8
780writeback_clean=false
781cpu_side=system.cpu0.toL2Bus.master[0]
782mem_side=system.toL2Bus.slave[0]
783
784[system.cpu0.l2cache.prefetcher]
--- 26 unchanged lines hidden (view full) ---
811thresh_conf=4
812use_master_id=true
813
814[system.cpu0.l2cache.tags]
815type=RandomRepl
816assoc=16
817block_size=64
818clk_domain=system.cpu_clk_domain
819data_latency=12
820default_p_state=UNDEFINED
821eventq_index=0
822p_state_clk_gate_bins=20
823p_state_clk_gate_max=1000000000000
824p_state_clk_gate_min=1000
825power_model=Null
826sequential_access=false
827size=1048576
828tag_latency=12
829
830[system.cpu0.toL2Bus]
831type=CoherentXBar
832children=snoop_filter
833clk_domain=system.cpu_clk_domain
834default_p_state=UNDEFINED
835eventq_index=0
836forward_latency=0
--- 30 unchanged lines hidden (view full) ---
867LQEntries=16
868LSQCheckLoads=true
869LSQDepCheckShift=0
870SQEntries=16
871SSITSize=1024
872activity=0
873backComSize=5
874branchPred=system.cpu1.branchPred
875cacheStorePorts=200
876checker=Null
877clk_domain=system.cpu_clk_domain
878commitToDecodeDelay=1
879commitToFetchDelay=1
880commitToIEWDelay=1
881commitToRenameDelay=1
882commitWidth=8
883cpu_id=1
--- 59 unchanged lines hidden (view full) ---
943smtLSQThreshold=100
944smtNumFetchingThreads=1
945smtROBPolicy=Partitioned
946smtROBThreshold=100
947socket_id=0
948squashWidth=8
949store_set_clear_period=250000
950switched_out=false
951syscallRetryLatency=10000
952system=system
953tracer=system.cpu1.tracer
954trapLatency=13
955wbWidth=8
956workload=
957dcache_port=system.cpu1.dcache.cpu_side
958icache_port=system.cpu1.icache.cpu_side
959
--- 19 unchanged lines hidden (view full) ---
979
980[system.cpu1.dcache]
981type=Cache
982children=tags
983addr_ranges=0:18446744073709551615:0:0:0:0
984assoc=2
985clk_domain=system.cpu_clk_domain
986clusivity=mostly_incl
987data_latency=2
988default_p_state=UNDEFINED
989demand_mshr_reserve=1
990eventq_index=0
991is_read_only=false
992max_miss_count=0
993mshrs=6
994p_state_clk_gate_bins=20
995p_state_clk_gate_max=1000000000000
996p_state_clk_gate_min=1000
997power_model=Null
998prefetch_on_access=false
999prefetcher=Null
1000response_latency=2
1001sequential_access=false
1002size=32768
1003system=system
1004tag_latency=2
1005tags=system.cpu1.dcache.tags
1006tgts_per_mshr=8
1007write_buffers=16
1008writeback_clean=true
1009cpu_side=system.cpu1.dcache_port
1010mem_side=system.cpu1.toL2Bus.slave[1]
1011
1012[system.cpu1.dcache.tags]
1013type=LRU
1014assoc=2
1015block_size=64
1016clk_domain=system.cpu_clk_domain
1017data_latency=2
1018default_p_state=UNDEFINED
1019eventq_index=0
1020p_state_clk_gate_bins=20
1021p_state_clk_gate_max=1000000000000
1022p_state_clk_gate_min=1000
1023power_model=Null
1024sequential_access=false
1025size=32768
1026tag_latency=2
1027
1028[system.cpu1.dstage2_mmu]
1029type=ArmStage2MMU
1030children=stage2_tlb
1031eventq_index=0
1032stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
1033sys=system
1034tlb=system.cpu1.dtb
--- 86 unchanged lines hidden (view full) ---
1121type=OpDesc
1122eventq_index=0
1123opClass=IprAccess
1124opLat=3
1125pipelined=true
1126
1127[system.cpu1.fuPool.FUList2]
1128type=FUDesc
1129children=opList0 opList1
1130count=1
1131eventq_index=0
1132opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1
1133
1134[system.cpu1.fuPool.FUList2.opList0]
1135type=OpDesc
1136eventq_index=0
1137opClass=MemRead
1138opLat=2
1139pipelined=true
1140
1141[system.cpu1.fuPool.FUList2.opList1]
1142type=OpDesc
1143eventq_index=0
1144opClass=FloatMemRead
1145opLat=2
1146pipelined=true
1147
1148[system.cpu1.fuPool.FUList3]
1149type=FUDesc
1150children=opList0 opList1
1151count=1
1152eventq_index=0
1153opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1
1154
1155[system.cpu1.fuPool.FUList3.opList0]
1156type=OpDesc
1157eventq_index=0
1158opClass=MemWrite
1159opLat=2
1160pipelined=true
1161
1162[system.cpu1.fuPool.FUList3.opList1]
1163type=OpDesc
1164eventq_index=0
1165opClass=FloatMemWrite
1166opLat=2
1167pipelined=true
1168
1169[system.cpu1.fuPool.FUList4]
1170type=FUDesc
1171children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
1172count=2
1173eventq_index=0
1174opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 system.cpu1.fuPool.FUList4.opList02 system.cpu1.fuPool.FUList4.opList03 system.cpu1.fuPool.FUList4.opList04 system.cpu1.fuPool.FUList4.opList05 system.cpu1.fuPool.FUList4.opList06 system.cpu1.fuPool.FUList4.opList07 system.cpu1.fuPool.FUList4.opList08 system.cpu1.fuPool.FUList4.opList09 system.cpu1.fuPool.FUList4.opList10 system.cpu1.fuPool.FUList4.opList11 system.cpu1.fuPool.FUList4.opList12 system.cpu1.fuPool.FUList4.opList13 system.cpu1.fuPool.FUList4.opList14 system.cpu1.fuPool.FUList4.opList15 system.cpu1.fuPool.FUList4.opList16 system.cpu1.fuPool.FUList4.opList17 system.cpu1.fuPool.FUList4.opList18 system.cpu1.fuPool.FUList4.opList19 system.cpu1.fuPool.FUList4.opList20 system.cpu1.fuPool.FUList4.opList21 system.cpu1.fuPool.FUList4.opList22 system.cpu1.fuPool.FUList4.opList23 system.cpu1.fuPool.FUList4.opList24 system.cpu1.fuPool.FUList4.opList25 system.cpu1.fuPool.FUList4.opList26 system.cpu1.fuPool.FUList4.opList27
1175
1176[system.cpu1.fuPool.FUList4.opList00]
1177type=OpDesc
1178eventq_index=0
1179opClass=SimdAdd
1180opLat=4
1181pipelined=true
1182
--- 115 unchanged lines hidden (view full) ---
1298opClass=SimdFloatMult
1299opLat=3
1300pipelined=true
1301
1302[system.cpu1.fuPool.FUList4.opList18]
1303type=OpDesc
1304eventq_index=0
1305opClass=SimdFloatMultAcc
1306opLat=5
1307pipelined=true
1308
1309[system.cpu1.fuPool.FUList4.opList19]
1310type=OpDesc
1311eventq_index=0
1312opClass=SimdFloatSqrt
1313opLat=9
1314pipelined=true
--- 35 unchanged lines hidden (view full) ---
1350
1351[system.cpu1.fuPool.FUList4.opList25]
1352type=OpDesc
1353eventq_index=0
1354opClass=FloatMult
1355opLat=4
1356pipelined=true
1357
1358[system.cpu1.fuPool.FUList4.opList26]
1359type=OpDesc
1360eventq_index=0
1361opClass=FloatMultAcc
1362opLat=5
1363pipelined=true
1364
1365[system.cpu1.fuPool.FUList4.opList27]
1366type=OpDesc
1367eventq_index=0
1368opClass=FloatMisc
1369opLat=3
1370pipelined=true
1371
1372[system.cpu1.icache]
1373type=Cache
1374children=tags
1375addr_ranges=0:18446744073709551615:0:0:0:0
1376assoc=2
1377clk_domain=system.cpu_clk_domain
1378clusivity=mostly_incl
1379data_latency=1
1380default_p_state=UNDEFINED
1381demand_mshr_reserve=1
1382eventq_index=0
1383is_read_only=true
1384max_miss_count=0
1385mshrs=2
1386p_state_clk_gate_bins=20
1387p_state_clk_gate_max=1000000000000
1388p_state_clk_gate_min=1000
1389power_model=Null
1390prefetch_on_access=false
1391prefetcher=Null
1392response_latency=1
1393sequential_access=false
1394size=32768
1395system=system
1396tag_latency=1
1397tags=system.cpu1.icache.tags
1398tgts_per_mshr=8
1399write_buffers=8
1400writeback_clean=true
1401cpu_side=system.cpu1.icache_port
1402mem_side=system.cpu1.toL2Bus.slave[0]
1403
1404[system.cpu1.icache.tags]
1405type=LRU
1406assoc=2
1407block_size=64
1408clk_domain=system.cpu_clk_domain
1409data_latency=1
1410default_p_state=UNDEFINED
1411eventq_index=0
1412p_state_clk_gate_bins=20
1413p_state_clk_gate_max=1000000000000
1414p_state_clk_gate_min=1000
1415power_model=Null
1416sequential_access=false
1417size=32768
1418tag_latency=1
1419
1420[system.cpu1.interrupts]
1421type=ArmInterrupts
1422eventq_index=0
1423
1424[system.cpu1.isa]
1425type=ArmISA
1426decoderFlavour=Generic
1427eventq_index=0
1428fpsid=1090793632
1429id_aa64afr0_el1=0
1430id_aa64afr1_el1=0
1431id_aa64dfr0_el1=1052678
1432id_aa64dfr1_el1=0
1433id_aa64isar0_el1=0
1434id_aa64isar1_el1=0
1435id_aa64mmfr0_el1=15728642
1436id_aa64mmfr1_el1=0
1437id_isar0=34607377
1438id_isar1=34677009
1439id_isar2=555950401
1440id_isar3=17899825
1441id_isar4=268501314
1442id_isar5=0
1443id_mmfr0=270536963
1444id_mmfr1=0
1445id_mmfr2=19070976
1446id_mmfr3=34611729
1447midr=1091551472
1448pmu=Null
1449system=system
1450
1451[system.cpu1.istage2_mmu]
1452type=ArmStage2MMU
1453children=stage2_tlb
1454eventq_index=0
--- 46 unchanged lines hidden (view full) ---
1501
1502[system.cpu1.l2cache]
1503type=Cache
1504children=prefetcher tags
1505addr_ranges=0:18446744073709551615:0:0:0:0
1506assoc=16
1507clk_domain=system.cpu_clk_domain
1508clusivity=mostly_excl
1509data_latency=12
1510default_p_state=UNDEFINED
1511demand_mshr_reserve=1
1512eventq_index=0
1513is_read_only=false
1514max_miss_count=0
1515mshrs=16
1516p_state_clk_gate_bins=20
1517p_state_clk_gate_max=1000000000000
1518p_state_clk_gate_min=1000
1519power_model=Null
1520prefetch_on_access=true
1521prefetcher=system.cpu1.l2cache.prefetcher
1522response_latency=12
1523sequential_access=false
1524size=1048576
1525system=system
1526tag_latency=12
1527tags=system.cpu1.l2cache.tags
1528tgts_per_mshr=8
1529write_buffers=8
1530writeback_clean=false
1531cpu_side=system.cpu1.toL2Bus.master[0]
1532mem_side=system.toL2Bus.slave[1]
1533
1534[system.cpu1.l2cache.prefetcher]
--- 26 unchanged lines hidden (view full) ---
1561thresh_conf=4
1562use_master_id=true
1563
1564[system.cpu1.l2cache.tags]
1565type=RandomRepl
1566assoc=16
1567block_size=64
1568clk_domain=system.cpu_clk_domain
1569data_latency=12
1570default_p_state=UNDEFINED
1571eventq_index=0
1572p_state_clk_gate_bins=20
1573p_state_clk_gate_max=1000000000000
1574p_state_clk_gate_min=1000
1575power_model=Null
1576sequential_access=false
1577size=1048576
1578tag_latency=12
1579
1580[system.cpu1.toL2Bus]
1581type=CoherentXBar
1582children=snoop_filter
1583clk_domain=system.cpu_clk_domain
1584default_p_state=UNDEFINED
1585eventq_index=0
1586forward_latency=0
--- 63 unchanged lines hidden (view full) ---
1650
1651[system.iocache]
1652type=Cache
1653children=tags
1654addr_ranges=2147483648:2415919103:0:0:0:0
1655assoc=8
1656clk_domain=system.clk_domain
1657clusivity=mostly_incl
1658data_latency=50
1659default_p_state=UNDEFINED
1660demand_mshr_reserve=1
1661eventq_index=0
1662is_read_only=false
1663max_miss_count=0
1664mshrs=20
1665p_state_clk_gate_bins=20
1666p_state_clk_gate_max=1000000000000
1667p_state_clk_gate_min=1000
1668power_model=Null
1669prefetch_on_access=false
1670prefetcher=Null
1671response_latency=50
1672sequential_access=false
1673size=1024
1674system=system
1675tag_latency=50
1676tags=system.iocache.tags
1677tgts_per_mshr=12
1678write_buffers=8
1679writeback_clean=false
1680cpu_side=system.iobus.master[25]
1681mem_side=system.membus.slave[3]
1682
1683[system.iocache.tags]
1684type=LRU
1685assoc=8
1686block_size=64
1687clk_domain=system.clk_domain
1688data_latency=50
1689default_p_state=UNDEFINED
1690eventq_index=0
1691p_state_clk_gate_bins=20
1692p_state_clk_gate_max=1000000000000
1693p_state_clk_gate_min=1000
1694power_model=Null
1695sequential_access=false
1696size=1024
1697tag_latency=50
1698
1699[system.l2c]
1700type=Cache
1701children=tags
1702addr_ranges=0:18446744073709551615:0:0:0:0
1703assoc=8
1704clk_domain=system.cpu_clk_domain
1705clusivity=mostly_incl
1706data_latency=20
1707default_p_state=UNDEFINED
1708demand_mshr_reserve=1
1709eventq_index=0
1710is_read_only=false
1711max_miss_count=0
1712mshrs=20
1713p_state_clk_gate_bins=20
1714p_state_clk_gate_max=1000000000000
1715p_state_clk_gate_min=1000
1716power_model=Null
1717prefetch_on_access=false
1718prefetcher=Null
1719response_latency=20
1720sequential_access=false
1721size=4194304
1722system=system
1723tag_latency=20
1724tags=system.l2c.tags
1725tgts_per_mshr=12
1726write_buffers=8
1727writeback_clean=false
1728cpu_side=system.toL2Bus.master[0]
1729mem_side=system.membus.slave[2]
1730
1731[system.l2c.tags]
1732type=LRU
1733assoc=8
1734block_size=64
1735clk_domain=system.cpu_clk_domain
1736data_latency=20
1737default_p_state=UNDEFINED
1738eventq_index=0
1739p_state_clk_gate_bins=20
1740p_state_clk_gate_max=1000000000000
1741p_state_clk_gate_min=1000
1742power_model=Null
1743sequential_access=false
1744size=4194304
1745tag_latency=20
1746
1747[system.membus]
1748type=CoherentXBar
1749children=badaddr_responder snoop_filter
1750clk_domain=system.clk_domain
1751default_p_state=UNDEFINED
1752eventq_index=0
1753forward_latency=4
--- 1107 unchanged lines hidden ---
2type=Root
3children=system
4eventq_index=0
5full_system=true
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
9time_sync_spin_threshold=100000000
10
11[system]
12type=LinuxArmSystem
13children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
14atags_addr=134217728
15boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
16boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
17cache_line_size=64
18clk_domain=system.clk_domain
19default_p_state=UNDEFINED
20dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
21early_kernel_symbols=false
22enable_context_switch_stats_dump=false
23eventq_index=0
24exit_on_work_items=false
25flags_addr=469827632
26gic_cpu_addr=738205696
27have_large_asid_64=false
28have_lpae=true
29have_security=false
30have_virtualization=false
31highest_el_is_64=false
32init_param=0
33kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
34kernel_addr_check=true
35load_addr_mask=268435455
36load_offset=2147483648
37machine_type=VExpress_EMM
38mem_mode=timing
39mem_ranges=2147483648:2415919103:0:0:0:0
40memories=system.physmem system.realview.nvmem system.realview.vram
41mmap_using_noreserve=false
42multi_proc=true
43multi_thread=false
44num_work_ids=16
45p_state_clk_gate_bins=20
46p_state_clk_gate_max=1000000000000
47p_state_clk_gate_min=1000
48panic_on_oops=true
49panic_on_panic=true
50phys_addr_range_64=40
51power_model=Null
52readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
53reset_addr_64=0
54symbolfile=
55thermal_components=
56thermal_model=Null
57work_begin_ckpt_count=0
58work_begin_cpu_id_exit=-1
59work_begin_exit_count=0
60work_cpus_ckpt_count=0
--- 33 unchanged lines hidden (view full) ---
94eventq_index=0
95image_file=
96read_only=false
97table_size=65536
98
99[system.cf0.image.child]
100type=RawDiskImage
101eventq_index=0
102image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
103read_only=true
104
105[system.clk_domain]
106type=SrcClockDomain
107clock=1000
108domain_id=-1
109eventq_index=0
110init_perf_level=0
--- 6 unchanged lines hidden (view full) ---
117LQEntries=16
118LSQCheckLoads=true
119LSQDepCheckShift=0
120SQEntries=16
121SSITSize=1024
122activity=0
123backComSize=5
124branchPred=system.cpu0.branchPred
125cacheStorePorts=200
126checker=Null
127clk_domain=system.cpu_clk_domain
128commitToDecodeDelay=1
129commitToFetchDelay=1
130commitToIEWDelay=1
131commitToRenameDelay=1
132commitWidth=8
133cpu_id=0
--- 59 unchanged lines hidden (view full) ---
193smtLSQThreshold=100
194smtNumFetchingThreads=1
195smtROBPolicy=Partitioned
196smtROBThreshold=100
197socket_id=0
198squashWidth=8
199store_set_clear_period=250000
200switched_out=false
201syscallRetryLatency=10000
202system=system
203tracer=system.cpu0.tracer
204trapLatency=13
205wbWidth=8
206workload=
207dcache_port=system.cpu0.dcache.cpu_side
208icache_port=system.cpu0.icache.cpu_side
209
--- 19 unchanged lines hidden (view full) ---
229
230[system.cpu0.dcache]
231type=Cache
232children=tags
233addr_ranges=0:18446744073709551615:0:0:0:0
234assoc=2
235clk_domain=system.cpu_clk_domain
236clusivity=mostly_incl
237data_latency=2
238default_p_state=UNDEFINED
239demand_mshr_reserve=1
240eventq_index=0
241is_read_only=false
242max_miss_count=0
243mshrs=6
244p_state_clk_gate_bins=20
245p_state_clk_gate_max=1000000000000
246p_state_clk_gate_min=1000
247power_model=Null
248prefetch_on_access=false
249prefetcher=Null
250response_latency=2
251sequential_access=false
252size=32768
253system=system
254tag_latency=2
255tags=system.cpu0.dcache.tags
256tgts_per_mshr=8
257write_buffers=16
258writeback_clean=true
259cpu_side=system.cpu0.dcache_port
260mem_side=system.cpu0.toL2Bus.slave[1]
261
262[system.cpu0.dcache.tags]
263type=LRU
264assoc=2
265block_size=64
266clk_domain=system.cpu_clk_domain
267data_latency=2
268default_p_state=UNDEFINED
269eventq_index=0
270p_state_clk_gate_bins=20
271p_state_clk_gate_max=1000000000000
272p_state_clk_gate_min=1000
273power_model=Null
274sequential_access=false
275size=32768
276tag_latency=2
277
278[system.cpu0.dstage2_mmu]
279type=ArmStage2MMU
280children=stage2_tlb
281eventq_index=0
282stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
283sys=system
284tlb=system.cpu0.dtb
--- 86 unchanged lines hidden (view full) ---
371type=OpDesc
372eventq_index=0
373opClass=IprAccess
374opLat=3
375pipelined=true
376
377[system.cpu0.fuPool.FUList2]
378type=FUDesc
379children=opList0 opList1
380count=1
381eventq_index=0
382opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1
383
384[system.cpu0.fuPool.FUList2.opList0]
385type=OpDesc
386eventq_index=0
387opClass=MemRead
388opLat=2
389pipelined=true
390
391[system.cpu0.fuPool.FUList2.opList1]
392type=OpDesc
393eventq_index=0
394opClass=FloatMemRead
395opLat=2
396pipelined=true
397
398[system.cpu0.fuPool.FUList3]
399type=FUDesc
400children=opList0 opList1
401count=1
402eventq_index=0
403opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1
404
405[system.cpu0.fuPool.FUList3.opList0]
406type=OpDesc
407eventq_index=0
408opClass=MemWrite
409opLat=2
410pipelined=true
411
412[system.cpu0.fuPool.FUList3.opList1]
413type=OpDesc
414eventq_index=0
415opClass=FloatMemWrite
416opLat=2
417pipelined=true
418
419[system.cpu0.fuPool.FUList4]
420type=FUDesc
421children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
422count=2
423eventq_index=0
424opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 system.cpu0.fuPool.FUList4.opList02 system.cpu0.fuPool.FUList4.opList03 system.cpu0.fuPool.FUList4.opList04 system.cpu0.fuPool.FUList4.opList05 system.cpu0.fuPool.FUList4.opList06 system.cpu0.fuPool.FUList4.opList07 system.cpu0.fuPool.FUList4.opList08 system.cpu0.fuPool.FUList4.opList09 system.cpu0.fuPool.FUList4.opList10 system.cpu0.fuPool.FUList4.opList11 system.cpu0.fuPool.FUList4.opList12 system.cpu0.fuPool.FUList4.opList13 system.cpu0.fuPool.FUList4.opList14 system.cpu0.fuPool.FUList4.opList15 system.cpu0.fuPool.FUList4.opList16 system.cpu0.fuPool.FUList4.opList17 system.cpu0.fuPool.FUList4.opList18 system.cpu0.fuPool.FUList4.opList19 system.cpu0.fuPool.FUList4.opList20 system.cpu0.fuPool.FUList4.opList21 system.cpu0.fuPool.FUList4.opList22 system.cpu0.fuPool.FUList4.opList23 system.cpu0.fuPool.FUList4.opList24 system.cpu0.fuPool.FUList4.opList25 system.cpu0.fuPool.FUList4.opList26 system.cpu0.fuPool.FUList4.opList27
425
426[system.cpu0.fuPool.FUList4.opList00]
427type=OpDesc
428eventq_index=0
429opClass=SimdAdd
430opLat=4
431pipelined=true
432
--- 115 unchanged lines hidden (view full) ---
548opClass=SimdFloatMult
549opLat=3
550pipelined=true
551
552[system.cpu0.fuPool.FUList4.opList18]
553type=OpDesc
554eventq_index=0
555opClass=SimdFloatMultAcc
556opLat=5
557pipelined=true
558
559[system.cpu0.fuPool.FUList4.opList19]
560type=OpDesc
561eventq_index=0
562opClass=SimdFloatSqrt
563opLat=9
564pipelined=true
--- 35 unchanged lines hidden (view full) ---
600
601[system.cpu0.fuPool.FUList4.opList25]
602type=OpDesc
603eventq_index=0
604opClass=FloatMult
605opLat=4
606pipelined=true
607
608[system.cpu0.fuPool.FUList4.opList26]
609type=OpDesc
610eventq_index=0
611opClass=FloatMultAcc
612opLat=5
613pipelined=true
614
615[system.cpu0.fuPool.FUList4.opList27]
616type=OpDesc
617eventq_index=0
618opClass=FloatMisc
619opLat=3
620pipelined=true
621
622[system.cpu0.icache]
623type=Cache
624children=tags
625addr_ranges=0:18446744073709551615:0:0:0:0
626assoc=2
627clk_domain=system.cpu_clk_domain
628clusivity=mostly_incl
629data_latency=1
630default_p_state=UNDEFINED
631demand_mshr_reserve=1
632eventq_index=0
633is_read_only=true
634max_miss_count=0
635mshrs=2
636p_state_clk_gate_bins=20
637p_state_clk_gate_max=1000000000000
638p_state_clk_gate_min=1000
639power_model=Null
640prefetch_on_access=false
641prefetcher=Null
642response_latency=1
643sequential_access=false
644size=32768
645system=system
646tag_latency=1
647tags=system.cpu0.icache.tags
648tgts_per_mshr=8
649write_buffers=8
650writeback_clean=true
651cpu_side=system.cpu0.icache_port
652mem_side=system.cpu0.toL2Bus.slave[0]
653
654[system.cpu0.icache.tags]
655type=LRU
656assoc=2
657block_size=64
658clk_domain=system.cpu_clk_domain
659data_latency=1
660default_p_state=UNDEFINED
661eventq_index=0
662p_state_clk_gate_bins=20
663p_state_clk_gate_max=1000000000000
664p_state_clk_gate_min=1000
665power_model=Null
666sequential_access=false
667size=32768
668tag_latency=1
669
670[system.cpu0.interrupts]
671type=ArmInterrupts
672eventq_index=0
673
674[system.cpu0.isa]
675type=ArmISA
676decoderFlavour=Generic
677eventq_index=0
678fpsid=1090793632
679id_aa64afr0_el1=0
680id_aa64afr1_el1=0
681id_aa64dfr0_el1=1052678
682id_aa64dfr1_el1=0
683id_aa64isar0_el1=0
684id_aa64isar1_el1=0
685id_aa64mmfr0_el1=15728642
686id_aa64mmfr1_el1=0
687id_isar0=34607377
688id_isar1=34677009
689id_isar2=555950401
690id_isar3=17899825
691id_isar4=268501314
692id_isar5=0
693id_mmfr0=270536963
694id_mmfr1=0
695id_mmfr2=19070976
696id_mmfr3=34611729
697midr=1091551472
698pmu=Null
699system=system
700
701[system.cpu0.istage2_mmu]
702type=ArmStage2MMU
703children=stage2_tlb
704eventq_index=0
--- 46 unchanged lines hidden (view full) ---
751
752[system.cpu0.l2cache]
753type=Cache
754children=prefetcher tags
755addr_ranges=0:18446744073709551615:0:0:0:0
756assoc=16
757clk_domain=system.cpu_clk_domain
758clusivity=mostly_excl
759data_latency=12
760default_p_state=UNDEFINED
761demand_mshr_reserve=1
762eventq_index=0
763is_read_only=false
764max_miss_count=0
765mshrs=16
766p_state_clk_gate_bins=20
767p_state_clk_gate_max=1000000000000
768p_state_clk_gate_min=1000
769power_model=Null
770prefetch_on_access=true
771prefetcher=system.cpu0.l2cache.prefetcher
772response_latency=12
773sequential_access=false
774size=1048576
775system=system
776tag_latency=12
777tags=system.cpu0.l2cache.tags
778tgts_per_mshr=8
779write_buffers=8
780writeback_clean=false
781cpu_side=system.cpu0.toL2Bus.master[0]
782mem_side=system.toL2Bus.slave[0]
783
784[system.cpu0.l2cache.prefetcher]
--- 26 unchanged lines hidden (view full) ---
811thresh_conf=4
812use_master_id=true
813
814[system.cpu0.l2cache.tags]
815type=RandomRepl
816assoc=16
817block_size=64
818clk_domain=system.cpu_clk_domain
819data_latency=12
820default_p_state=UNDEFINED
821eventq_index=0
822p_state_clk_gate_bins=20
823p_state_clk_gate_max=1000000000000
824p_state_clk_gate_min=1000
825power_model=Null
826sequential_access=false
827size=1048576
828tag_latency=12
829
830[system.cpu0.toL2Bus]
831type=CoherentXBar
832children=snoop_filter
833clk_domain=system.cpu_clk_domain
834default_p_state=UNDEFINED
835eventq_index=0
836forward_latency=0
--- 30 unchanged lines hidden (view full) ---
867LQEntries=16
868LSQCheckLoads=true
869LSQDepCheckShift=0
870SQEntries=16
871SSITSize=1024
872activity=0
873backComSize=5
874branchPred=system.cpu1.branchPred
875cacheStorePorts=200
876checker=Null
877clk_domain=system.cpu_clk_domain
878commitToDecodeDelay=1
879commitToFetchDelay=1
880commitToIEWDelay=1
881commitToRenameDelay=1
882commitWidth=8
883cpu_id=1
--- 59 unchanged lines hidden (view full) ---
943smtLSQThreshold=100
944smtNumFetchingThreads=1
945smtROBPolicy=Partitioned
946smtROBThreshold=100
947socket_id=0
948squashWidth=8
949store_set_clear_period=250000
950switched_out=false
951syscallRetryLatency=10000
952system=system
953tracer=system.cpu1.tracer
954trapLatency=13
955wbWidth=8
956workload=
957dcache_port=system.cpu1.dcache.cpu_side
958icache_port=system.cpu1.icache.cpu_side
959
--- 19 unchanged lines hidden (view full) ---
979
980[system.cpu1.dcache]
981type=Cache
982children=tags
983addr_ranges=0:18446744073709551615:0:0:0:0
984assoc=2
985clk_domain=system.cpu_clk_domain
986clusivity=mostly_incl
987data_latency=2
988default_p_state=UNDEFINED
989demand_mshr_reserve=1
990eventq_index=0
991is_read_only=false
992max_miss_count=0
993mshrs=6
994p_state_clk_gate_bins=20
995p_state_clk_gate_max=1000000000000
996p_state_clk_gate_min=1000
997power_model=Null
998prefetch_on_access=false
999prefetcher=Null
1000response_latency=2
1001sequential_access=false
1002size=32768
1003system=system
1004tag_latency=2
1005tags=system.cpu1.dcache.tags
1006tgts_per_mshr=8
1007write_buffers=16
1008writeback_clean=true
1009cpu_side=system.cpu1.dcache_port
1010mem_side=system.cpu1.toL2Bus.slave[1]
1011
1012[system.cpu1.dcache.tags]
1013type=LRU
1014assoc=2
1015block_size=64
1016clk_domain=system.cpu_clk_domain
1017data_latency=2
1018default_p_state=UNDEFINED
1019eventq_index=0
1020p_state_clk_gate_bins=20
1021p_state_clk_gate_max=1000000000000
1022p_state_clk_gate_min=1000
1023power_model=Null
1024sequential_access=false
1025size=32768
1026tag_latency=2
1027
1028[system.cpu1.dstage2_mmu]
1029type=ArmStage2MMU
1030children=stage2_tlb
1031eventq_index=0
1032stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
1033sys=system
1034tlb=system.cpu1.dtb
--- 86 unchanged lines hidden (view full) ---
1121type=OpDesc
1122eventq_index=0
1123opClass=IprAccess
1124opLat=3
1125pipelined=true
1126
1127[system.cpu1.fuPool.FUList2]
1128type=FUDesc
1129children=opList0 opList1
1130count=1
1131eventq_index=0
1132opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1
1133
1134[system.cpu1.fuPool.FUList2.opList0]
1135type=OpDesc
1136eventq_index=0
1137opClass=MemRead
1138opLat=2
1139pipelined=true
1140
1141[system.cpu1.fuPool.FUList2.opList1]
1142type=OpDesc
1143eventq_index=0
1144opClass=FloatMemRead
1145opLat=2
1146pipelined=true
1147
1148[system.cpu1.fuPool.FUList3]
1149type=FUDesc
1150children=opList0 opList1
1151count=1
1152eventq_index=0
1153opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1
1154
1155[system.cpu1.fuPool.FUList3.opList0]
1156type=OpDesc
1157eventq_index=0
1158opClass=MemWrite
1159opLat=2
1160pipelined=true
1161
1162[system.cpu1.fuPool.FUList3.opList1]
1163type=OpDesc
1164eventq_index=0
1165opClass=FloatMemWrite
1166opLat=2
1167pipelined=true
1168
1169[system.cpu1.fuPool.FUList4]
1170type=FUDesc
1171children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
1172count=2
1173eventq_index=0
1174opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 system.cpu1.fuPool.FUList4.opList02 system.cpu1.fuPool.FUList4.opList03 system.cpu1.fuPool.FUList4.opList04 system.cpu1.fuPool.FUList4.opList05 system.cpu1.fuPool.FUList4.opList06 system.cpu1.fuPool.FUList4.opList07 system.cpu1.fuPool.FUList4.opList08 system.cpu1.fuPool.FUList4.opList09 system.cpu1.fuPool.FUList4.opList10 system.cpu1.fuPool.FUList4.opList11 system.cpu1.fuPool.FUList4.opList12 system.cpu1.fuPool.FUList4.opList13 system.cpu1.fuPool.FUList4.opList14 system.cpu1.fuPool.FUList4.opList15 system.cpu1.fuPool.FUList4.opList16 system.cpu1.fuPool.FUList4.opList17 system.cpu1.fuPool.FUList4.opList18 system.cpu1.fuPool.FUList4.opList19 system.cpu1.fuPool.FUList4.opList20 system.cpu1.fuPool.FUList4.opList21 system.cpu1.fuPool.FUList4.opList22 system.cpu1.fuPool.FUList4.opList23 system.cpu1.fuPool.FUList4.opList24 system.cpu1.fuPool.FUList4.opList25 system.cpu1.fuPool.FUList4.opList26 system.cpu1.fuPool.FUList4.opList27
1175
1176[system.cpu1.fuPool.FUList4.opList00]
1177type=OpDesc
1178eventq_index=0
1179opClass=SimdAdd
1180opLat=4
1181pipelined=true
1182
--- 115 unchanged lines hidden (view full) ---
1298opClass=SimdFloatMult
1299opLat=3
1300pipelined=true
1301
1302[system.cpu1.fuPool.FUList4.opList18]
1303type=OpDesc
1304eventq_index=0
1305opClass=SimdFloatMultAcc
1306opLat=5
1307pipelined=true
1308
1309[system.cpu1.fuPool.FUList4.opList19]
1310type=OpDesc
1311eventq_index=0
1312opClass=SimdFloatSqrt
1313opLat=9
1314pipelined=true
--- 35 unchanged lines hidden (view full) ---
1350
1351[system.cpu1.fuPool.FUList4.opList25]
1352type=OpDesc
1353eventq_index=0
1354opClass=FloatMult
1355opLat=4
1356pipelined=true
1357
1358[system.cpu1.fuPool.FUList4.opList26]
1359type=OpDesc
1360eventq_index=0
1361opClass=FloatMultAcc
1362opLat=5
1363pipelined=true
1364
1365[system.cpu1.fuPool.FUList4.opList27]
1366type=OpDesc
1367eventq_index=0
1368opClass=FloatMisc
1369opLat=3
1370pipelined=true
1371
1372[system.cpu1.icache]
1373type=Cache
1374children=tags
1375addr_ranges=0:18446744073709551615:0:0:0:0
1376assoc=2
1377clk_domain=system.cpu_clk_domain
1378clusivity=mostly_incl
1379data_latency=1
1380default_p_state=UNDEFINED
1381demand_mshr_reserve=1
1382eventq_index=0
1383is_read_only=true
1384max_miss_count=0
1385mshrs=2
1386p_state_clk_gate_bins=20
1387p_state_clk_gate_max=1000000000000
1388p_state_clk_gate_min=1000
1389power_model=Null
1390prefetch_on_access=false
1391prefetcher=Null
1392response_latency=1
1393sequential_access=false
1394size=32768
1395system=system
1396tag_latency=1
1397tags=system.cpu1.icache.tags
1398tgts_per_mshr=8
1399write_buffers=8
1400writeback_clean=true
1401cpu_side=system.cpu1.icache_port
1402mem_side=system.cpu1.toL2Bus.slave[0]
1403
1404[system.cpu1.icache.tags]
1405type=LRU
1406assoc=2
1407block_size=64
1408clk_domain=system.cpu_clk_domain
1409data_latency=1
1410default_p_state=UNDEFINED
1411eventq_index=0
1412p_state_clk_gate_bins=20
1413p_state_clk_gate_max=1000000000000
1414p_state_clk_gate_min=1000
1415power_model=Null
1416sequential_access=false
1417size=32768
1418tag_latency=1
1419
1420[system.cpu1.interrupts]
1421type=ArmInterrupts
1422eventq_index=0
1423
1424[system.cpu1.isa]
1425type=ArmISA
1426decoderFlavour=Generic
1427eventq_index=0
1428fpsid=1090793632
1429id_aa64afr0_el1=0
1430id_aa64afr1_el1=0
1431id_aa64dfr0_el1=1052678
1432id_aa64dfr1_el1=0
1433id_aa64isar0_el1=0
1434id_aa64isar1_el1=0
1435id_aa64mmfr0_el1=15728642
1436id_aa64mmfr1_el1=0
1437id_isar0=34607377
1438id_isar1=34677009
1439id_isar2=555950401
1440id_isar3=17899825
1441id_isar4=268501314
1442id_isar5=0
1443id_mmfr0=270536963
1444id_mmfr1=0
1445id_mmfr2=19070976
1446id_mmfr3=34611729
1447midr=1091551472
1448pmu=Null
1449system=system
1450
1451[system.cpu1.istage2_mmu]
1452type=ArmStage2MMU
1453children=stage2_tlb
1454eventq_index=0
--- 46 unchanged lines hidden (view full) ---
1501
1502[system.cpu1.l2cache]
1503type=Cache
1504children=prefetcher tags
1505addr_ranges=0:18446744073709551615:0:0:0:0
1506assoc=16
1507clk_domain=system.cpu_clk_domain
1508clusivity=mostly_excl
1509data_latency=12
1510default_p_state=UNDEFINED
1511demand_mshr_reserve=1
1512eventq_index=0
1513is_read_only=false
1514max_miss_count=0
1515mshrs=16
1516p_state_clk_gate_bins=20
1517p_state_clk_gate_max=1000000000000
1518p_state_clk_gate_min=1000
1519power_model=Null
1520prefetch_on_access=true
1521prefetcher=system.cpu1.l2cache.prefetcher
1522response_latency=12
1523sequential_access=false
1524size=1048576
1525system=system
1526tag_latency=12
1527tags=system.cpu1.l2cache.tags
1528tgts_per_mshr=8
1529write_buffers=8
1530writeback_clean=false
1531cpu_side=system.cpu1.toL2Bus.master[0]
1532mem_side=system.toL2Bus.slave[1]
1533
1534[system.cpu1.l2cache.prefetcher]
--- 26 unchanged lines hidden (view full) ---
1561thresh_conf=4
1562use_master_id=true
1563
1564[system.cpu1.l2cache.tags]
1565type=RandomRepl
1566assoc=16
1567block_size=64
1568clk_domain=system.cpu_clk_domain
1569data_latency=12
1570default_p_state=UNDEFINED
1571eventq_index=0
1572p_state_clk_gate_bins=20
1573p_state_clk_gate_max=1000000000000
1574p_state_clk_gate_min=1000
1575power_model=Null
1576sequential_access=false
1577size=1048576
1578tag_latency=12
1579
1580[system.cpu1.toL2Bus]
1581type=CoherentXBar
1582children=snoop_filter
1583clk_domain=system.cpu_clk_domain
1584default_p_state=UNDEFINED
1585eventq_index=0
1586forward_latency=0
--- 63 unchanged lines hidden (view full) ---
1650
1651[system.iocache]
1652type=Cache
1653children=tags
1654addr_ranges=2147483648:2415919103:0:0:0:0
1655assoc=8
1656clk_domain=system.clk_domain
1657clusivity=mostly_incl
1658data_latency=50
1659default_p_state=UNDEFINED
1660demand_mshr_reserve=1
1661eventq_index=0
1662is_read_only=false
1663max_miss_count=0
1664mshrs=20
1665p_state_clk_gate_bins=20
1666p_state_clk_gate_max=1000000000000
1667p_state_clk_gate_min=1000
1668power_model=Null
1669prefetch_on_access=false
1670prefetcher=Null
1671response_latency=50
1672sequential_access=false
1673size=1024
1674system=system
1675tag_latency=50
1676tags=system.iocache.tags
1677tgts_per_mshr=12
1678write_buffers=8
1679writeback_clean=false
1680cpu_side=system.iobus.master[25]
1681mem_side=system.membus.slave[3]
1682
1683[system.iocache.tags]
1684type=LRU
1685assoc=8
1686block_size=64
1687clk_domain=system.clk_domain
1688data_latency=50
1689default_p_state=UNDEFINED
1690eventq_index=0
1691p_state_clk_gate_bins=20
1692p_state_clk_gate_max=1000000000000
1693p_state_clk_gate_min=1000
1694power_model=Null
1695sequential_access=false
1696size=1024
1697tag_latency=50
1698
1699[system.l2c]
1700type=Cache
1701children=tags
1702addr_ranges=0:18446744073709551615:0:0:0:0
1703assoc=8
1704clk_domain=system.cpu_clk_domain
1705clusivity=mostly_incl
1706data_latency=20
1707default_p_state=UNDEFINED
1708demand_mshr_reserve=1
1709eventq_index=0
1710is_read_only=false
1711max_miss_count=0
1712mshrs=20
1713p_state_clk_gate_bins=20
1714p_state_clk_gate_max=1000000000000
1715p_state_clk_gate_min=1000
1716power_model=Null
1717prefetch_on_access=false
1718prefetcher=Null
1719response_latency=20
1720sequential_access=false
1721size=4194304
1722system=system
1723tag_latency=20
1724tags=system.l2c.tags
1725tgts_per_mshr=12
1726write_buffers=8
1727writeback_clean=false
1728cpu_side=system.toL2Bus.master[0]
1729mem_side=system.membus.slave[2]
1730
1731[system.l2c.tags]
1732type=LRU
1733assoc=8
1734block_size=64
1735clk_domain=system.cpu_clk_domain
1736data_latency=20
1737default_p_state=UNDEFINED
1738eventq_index=0
1739p_state_clk_gate_bins=20
1740p_state_clk_gate_max=1000000000000
1741p_state_clk_gate_min=1000
1742power_model=Null
1743sequential_access=false
1744size=4194304
1745tag_latency=20
1746
1747[system.membus]
1748type=CoherentXBar
1749children=badaddr_responder snoop_filter
1750clk_domain=system.clk_domain
1751default_p_state=UNDEFINED
1752eventq_index=0
1753forward_latency=4
--- 1107 unchanged lines hidden ---