| config.ini (11570:4aac82f10951) | config.ini (11680:b4d943429dc6) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 11 unchanged lines hidden (view full) --- 20eventq_index=0 21exit_on_work_items=false 22init_param=0 23kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux 24kernel_addr_check=true 25load_addr_mask=1099511627775 26load_offset=0 27mem_mode=timing | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 11 unchanged lines hidden (view full) --- 20eventq_index=0 21exit_on_work_items=false 22init_param=0 23kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux 24kernel_addr_check=true 25load_addr_mask=1099511627775 26load_offset=0 27mem_mode=timing |
| 28mem_ranges=0:134217727 | 28mem_ranges=0:134217727:0:0:0:0 |
| 29memories=system.physmem 30mmap_using_noreserve=false 31multi_thread=false 32num_work_ids=16 33p_state_clk_gate_bins=20 34p_state_clk_gate_max=1000000000000 35p_state_clk_gate_min=1000 36pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal --- 18 unchanged lines hidden (view full) --- 55clk_domain=system.clk_domain 56default_p_state=UNDEFINED 57delay=50000 58eventq_index=0 59p_state_clk_gate_bins=20 60p_state_clk_gate_max=1000000000000 61p_state_clk_gate_min=1000 62power_model=Null | 29memories=system.physmem 30mmap_using_noreserve=false 31multi_thread=false 32num_work_ids=16 33p_state_clk_gate_bins=20 34p_state_clk_gate_max=1000000000000 35p_state_clk_gate_min=1000 36pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal --- 18 unchanged lines hidden (view full) --- 55clk_domain=system.clk_domain 56default_p_state=UNDEFINED 57delay=50000 58eventq_index=0 59p_state_clk_gate_bins=20 60p_state_clk_gate_max=1000000000000 61p_state_clk_gate_min=1000 62power_model=Null |
| 63ranges=8796093022208:18446744073709551615 | 63ranges=8796093022208:18446744073709551615:0:0:0:0 |
| 64req_size=16 65resp_size=16 66master=system.iobus.slave[0] 67slave=system.membus.master[0] 68 69[system.clk_domain] 70type=SrcClockDomain 71clock=1000 --- 117 unchanged lines hidden (view full) --- 189localHistoryTableSize=2048 190localPredictorSize=2048 191numThreads=1 192useIndirect=true 193 194[system.cpu.dcache] 195type=Cache 196children=tags | 64req_size=16 65resp_size=16 66master=system.iobus.slave[0] 67slave=system.membus.master[0] 68 69[system.clk_domain] 70type=SrcClockDomain 71clock=1000 --- 117 unchanged lines hidden (view full) --- 189localHistoryTableSize=2048 190localPredictorSize=2048 191numThreads=1 192useIndirect=true 193 194[system.cpu.dcache] 195type=Cache 196children=tags |
| 197addr_ranges=0:18446744073709551615 | 197addr_ranges=0:18446744073709551615:0:0:0:0 |
| 198assoc=4 199clk_domain=system.cpu_clk_domain 200clusivity=mostly_incl 201default_p_state=UNDEFINED 202demand_mshr_reserve=1 203eventq_index=0 204hit_latency=2 205is_read_only=false --- 341 unchanged lines hidden (view full) --- 547eventq_index=0 548opClass=IprAccess 549opLat=3 550pipelined=false 551 552[system.cpu.icache] 553type=Cache 554children=tags | 198assoc=4 199clk_domain=system.cpu_clk_domain 200clusivity=mostly_incl 201default_p_state=UNDEFINED 202demand_mshr_reserve=1 203eventq_index=0 204hit_latency=2 205is_read_only=false --- 341 unchanged lines hidden (view full) --- 547eventq_index=0 548opClass=IprAccess 549opLat=3 550pipelined=false 551 552[system.cpu.icache] 553type=Cache 554children=tags |
| 555addr_ranges=0:18446744073709551615 | 555addr_ranges=0:18446744073709551615:0:0:0:0 |
| 556assoc=1 557clk_domain=system.cpu_clk_domain 558clusivity=mostly_incl 559default_p_state=UNDEFINED 560demand_mshr_reserve=1 561eventq_index=0 562hit_latency=2 563is_read_only=true --- 43 unchanged lines hidden (view full) --- 607[system.cpu.itb] 608type=AlphaTLB 609eventq_index=0 610size=48 611 612[system.cpu.l2cache] 613type=Cache 614children=tags | 556assoc=1 557clk_domain=system.cpu_clk_domain 558clusivity=mostly_incl 559default_p_state=UNDEFINED 560demand_mshr_reserve=1 561eventq_index=0 562hit_latency=2 563is_read_only=true --- 43 unchanged lines hidden (view full) --- 607[system.cpu.itb] 608type=AlphaTLB 609eventq_index=0 610size=48 611 612[system.cpu.l2cache] 613type=Cache 614children=tags |
| 615addr_ranges=0:18446744073709551615 | 615addr_ranges=0:18446744073709551615:0:0:0:0 |
| 616assoc=8 617clk_domain=system.cpu_clk_domain 618clusivity=mostly_incl 619default_p_state=UNDEFINED 620demand_mshr_reserve=1 621eventq_index=0 622hit_latency=20 623is_read_only=false --- 146 unchanged lines hidden (view full) --- 770use_default_range=false 771width=16 772master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side 773slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 774 775[system.iocache] 776type=Cache 777children=tags | 616assoc=8 617clk_domain=system.cpu_clk_domain 618clusivity=mostly_incl 619default_p_state=UNDEFINED 620demand_mshr_reserve=1 621eventq_index=0 622hit_latency=20 623is_read_only=false --- 146 unchanged lines hidden (view full) --- 770use_default_range=false 771width=16 772master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side 773slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 774 775[system.iocache] 776type=Cache 777children=tags |
| 778addr_ranges=0:134217727 | 778addr_ranges=0:134217727:0:0:0:0 |
| 779assoc=8 780clk_domain=system.clk_domain 781clusivity=mostly_incl 782default_p_state=UNDEFINED 783demand_mshr_reserve=1 784eventq_index=0 785hit_latency=50 786is_read_only=false --- 28 unchanged lines hidden (view full) --- 815p_state_clk_gate_max=1000000000000 816p_state_clk_gate_min=1000 817power_model=Null 818sequential_access=false 819size=1024 820 821[system.membus] 822type=CoherentXBar | 779assoc=8 780clk_domain=system.clk_domain 781clusivity=mostly_incl 782default_p_state=UNDEFINED 783demand_mshr_reserve=1 784eventq_index=0 785hit_latency=50 786is_read_only=false --- 28 unchanged lines hidden (view full) --- 815p_state_clk_gate_max=1000000000000 816p_state_clk_gate_min=1000 817power_model=Null 818sequential_access=false 819size=1024 820 821[system.membus] 822type=CoherentXBar |
| 823children=badaddr_responder | 823children=badaddr_responder snoop_filter |
| 824clk_domain=system.clk_domain 825default_p_state=UNDEFINED 826eventq_index=0 827forward_latency=4 828frontend_latency=3 829p_state_clk_gate_bins=20 830p_state_clk_gate_max=1000000000000 831p_state_clk_gate_min=1000 832point_of_coherency=true 833power_model=Null 834response_latency=2 | 824clk_domain=system.clk_domain 825default_p_state=UNDEFINED 826eventq_index=0 827forward_latency=4 828frontend_latency=3 829p_state_clk_gate_bins=20 830p_state_clk_gate_max=1000000000000 831p_state_clk_gate_min=1000 832point_of_coherency=true 833power_model=Null 834response_latency=2 |
| 835snoop_filter=Null | 835snoop_filter=system.membus.snoop_filter |
| 836snoop_response_latency=4 837system=system 838use_default_range=false 839width=16 840default=system.membus.badaddr_responder.pio 841master=system.bridge.slave system.physmem.port 842slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 843 --- 15 unchanged lines hidden (view full) --- 859ret_data32=4294967295 860ret_data64=18446744073709551615 861ret_data8=255 862system=system 863update_data=false 864warn_access= 865pio=system.membus.default 866 | 836snoop_response_latency=4 837system=system 838use_default_range=false 839width=16 840default=system.membus.badaddr_responder.pio 841master=system.bridge.slave system.physmem.port 842slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 843 --- 15 unchanged lines hidden (view full) --- 859ret_data32=4294967295 860ret_data64=18446744073709551615 861ret_data8=255 862system=system 863update_data=false 864warn_access= 865pio=system.membus.default 866 |
| 867[system.membus.snoop_filter] 868type=SnoopFilter 869eventq_index=0 870lookup_latency=1 871max_capacity=8388608 872system=system 873 |
|
| 867[system.physmem] 868type=DRAMCtrl | 874[system.physmem] 875type=DRAMCtrl |
| 869IDD0=0.075000 | 876IDD0=0.055000 |
| 870IDD02=0.000000 | 877IDD02=0.000000 |
| 871IDD2N=0.050000 | 878IDD2N=0.032000 |
| 872IDD2N2=0.000000 873IDD2P0=0.000000 874IDD2P02=0.000000 | 879IDD2N2=0.000000 880IDD2P0=0.000000 881IDD2P02=0.000000 |
| 875IDD2P1=0.000000 | 882IDD2P1=0.032000 |
| 876IDD2P12=0.000000 | 883IDD2P12=0.000000 |
| 877IDD3N=0.057000 | 884IDD3N=0.038000 |
| 878IDD3N2=0.000000 879IDD3P0=0.000000 880IDD3P02=0.000000 | 885IDD3N2=0.000000 886IDD3P0=0.000000 887IDD3P02=0.000000 |
| 881IDD3P1=0.000000 | 888IDD3P1=0.038000 |
| 882IDD3P12=0.000000 | 889IDD3P12=0.000000 |
| 883IDD4R=0.187000 | 890IDD4R=0.157000 |
| 884IDD4R2=0.000000 | 891IDD4R2=0.000000 |
| 885IDD4W=0.165000 | 892IDD4W=0.125000 |
| 886IDD4W2=0.000000 | 893IDD4W2=0.000000 |
| 887IDD5=0.220000 | 894IDD5=0.235000 |
| 888IDD52=0.000000 | 895IDD52=0.000000 |
| 889IDD6=0.000000 | 896IDD6=0.020000 |
| 890IDD62=0.000000 891VDD=1.500000 892VDD2=0.000000 893activation_limit=4 894addr_mapping=RoRaBaCoCh 895bank_groups_per_rank=0 896banks_per_rank=8 897burst_length=8 898channels=1 899clk_domain=system.clk_domain 900conf_table_reported=true 901default_p_state=UNDEFINED 902device_bus_width=8 903device_rowbuffer_size=1024 904device_size=536870912 905devices_per_rank=8 906dll=true 907eventq_index=0 908in_addr_map=true | 897IDD62=0.000000 898VDD=1.500000 899VDD2=0.000000 900activation_limit=4 901addr_mapping=RoRaBaCoCh 902bank_groups_per_rank=0 903banks_per_rank=8 904burst_length=8 905channels=1 906clk_domain=system.clk_domain 907conf_table_reported=true 908default_p_state=UNDEFINED 909device_bus_width=8 910device_rowbuffer_size=1024 911device_size=536870912 912devices_per_rank=8 913dll=true 914eventq_index=0 915in_addr_map=true |
| 916kvm_map=true |
|
| 909max_accesses_per_row=16 910mem_sched_policy=frfcfs 911min_writes_per_switch=16 912null=false 913p_state_clk_gate_bins=20 914p_state_clk_gate_max=1000000000000 915p_state_clk_gate_min=1000 916page_policy=open_adaptive 917power_model=Null | 917max_accesses_per_row=16 918mem_sched_policy=frfcfs 919min_writes_per_switch=16 920null=false 921p_state_clk_gate_bins=20 922p_state_clk_gate_max=1000000000000 923p_state_clk_gate_min=1000 924page_policy=open_adaptive 925power_model=Null |
| 918range=0:134217727 | 926range=0:134217727:0:0:0:0 |
| 919ranks_per_channel=2 920read_buffer_size=32 921static_backend_latency=10000 922static_frontend_latency=10000 923tBURST=5000 924tCCD_L=0 925tCK=1250 926tCL=13750 --- 5 unchanged lines hidden (view full) --- 932tRP=13750 933tRRD=6000 934tRRD_L=0 935tRTP=7500 936tRTW=2500 937tWR=15000 938tWTR=7500 939tXAW=30000 | 927ranks_per_channel=2 928read_buffer_size=32 929static_backend_latency=10000 930static_frontend_latency=10000 931tBURST=5000 932tCCD_L=0 933tCK=1250 934tCL=13750 --- 5 unchanged lines hidden (view full) --- 940tRP=13750 941tRRD=6000 942tRRD_L=0 943tRTP=7500 944tRTW=2500 945tWR=15000 946tWTR=7500 947tXAW=30000 |
| 940tXP=0 | 948tXP=6000 |
| 941tXPDLL=0 | 949tXPDLL=0 |
| 942tXS=0 | 950tXS=270000 |
| 943tXSDLL=0 944write_buffer_size=64 945write_high_thresh_perc=85 946write_low_thresh_perc=50 947port=system.membus.master[1] 948 949[system.simple_disk] 950type=SimpleDisk --- 774 unchanged lines hidden --- | 951tXSDLL=0 952write_buffer_size=64 953write_high_thresh_perc=85 954write_low_thresh_perc=50 955port=system.membus.master[1] 956 957[system.simple_disk] 958type=SimpleDisk --- 774 unchanged lines hidden --- |