| config.ini (10513:ca4438b6e39a) | config.ini (10798:74e3c7359393) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxAlphaSystem 13children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain 14boot_cpu_frequency=500 15boot_osflags=root=/dev/hda1 console=ttyS0 16cache_line_size=64 17clk_domain=system.clk_domain | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxAlphaSystem 13children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain 14boot_cpu_frequency=500 15boot_osflags=root=/dev/hda1 console=ttyS0 16cache_line_size=64 17clk_domain=system.clk_domain |
| 18console=/dist/binaries/console | 18console=/home/stever/m5/m5_system_2.0b3/binaries/console |
| 19eventq_index=0 20init_param=0 | 19eventq_index=0 20init_param=0 |
| 21kernel=/dist/binaries/vmlinux | 21kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux |
| 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges=0:134217727 27memories=system.physmem | 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges=0:134217727 27memories=system.physmem |
| 28mmap_using_noreserve=false |
|
| 28num_work_ids=16 | 29num_work_ids=16 |
| 29pal=/dist/binaries/ts_osfpal 30readfile=/work/gem5.latest/tests/halt.sh | 30pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal 31readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh |
| 31symbolfile= 32system_rev=1024 33system_type=34 34work_begin_ckpt_count=0 35work_begin_cpu_id_exit=-1 36work_begin_exit_count=0 37work_cpus_ckpt_count=0 38work_end_ckpt_count=0 --- 105 unchanged lines hidden (view full) --- 144tracer=system.cpu.tracer 145trapLatency=13 146wbWidth=8 147workload= 148dcache_port=system.cpu.dcache.cpu_side 149icache_port=system.cpu.icache.cpu_side 150 151[system.cpu.branchPred] | 32symbolfile= 33system_rev=1024 34system_type=34 35work_begin_ckpt_count=0 36work_begin_cpu_id_exit=-1 37work_begin_exit_count=0 38work_cpus_ckpt_count=0 39work_end_ckpt_count=0 --- 105 unchanged lines hidden (view full) --- 145tracer=system.cpu.tracer 146trapLatency=13 147wbWidth=8 148workload= 149dcache_port=system.cpu.dcache.cpu_side 150icache_port=system.cpu.icache.cpu_side 151 152[system.cpu.branchPred] |
| 152type=BranchPredictor | 153type=TournamentBP |
| 153BTBEntries=4096 154BTBTagSize=16 155RASSize=16 156choiceCtrBits=2 157choicePredictorSize=8192 158eventq_index=0 159globalCtrBits=2 160globalPredictorSize=8192 161instShiftAmt=2 162localCtrBits=2 163localHistoryTableSize=2048 164localPredictorSize=2048 165numThreads=1 | 154BTBEntries=4096 155BTBTagSize=16 156RASSize=16 157choiceCtrBits=2 158choicePredictorSize=8192 159eventq_index=0 160globalCtrBits=2 161globalPredictorSize=8192 162instShiftAmt=2 163localCtrBits=2 164localHistoryTableSize=2048 165localPredictorSize=2048 166numThreads=1 |
| 166predType=tournament | |
| 167 168[system.cpu.dcache] 169type=BaseCache 170children=tags 171addr_ranges=0:18446744073709551615 172assoc=4 173clk_domain=system.cpu_clk_domain | 167 168[system.cpu.dcache] 169type=BaseCache 170children=tags 171addr_ranges=0:18446744073709551615 172assoc=4 173clk_domain=system.cpu_clk_domain |
| 174demand_mshr_reserve=1 |
|
| 174eventq_index=0 175forward_snoops=true 176hit_latency=2 177is_top_level=true 178max_miss_count=0 179mshrs=4 180prefetch_on_access=false 181prefetcher=Null --- 331 unchanged lines hidden (view full) --- 513opLat=3 514 515[system.cpu.icache] 516type=BaseCache 517children=tags 518addr_ranges=0:18446744073709551615 519assoc=1 520clk_domain=system.cpu_clk_domain | 175eventq_index=0 176forward_snoops=true 177hit_latency=2 178is_top_level=true 179max_miss_count=0 180mshrs=4 181prefetch_on_access=false 182prefetcher=Null --- 331 unchanged lines hidden (view full) --- 514opLat=3 515 516[system.cpu.icache] 517type=BaseCache 518children=tags 519addr_ranges=0:18446744073709551615 520assoc=1 521clk_domain=system.cpu_clk_domain |
| 522demand_mshr_reserve=1 |
|
| 521eventq_index=0 522forward_snoops=true 523hit_latency=2 524is_top_level=true 525max_miss_count=0 526mshrs=4 527prefetch_on_access=false 528prefetcher=Null --- 33 unchanged lines hidden (view full) --- 562size=48 563 564[system.cpu.l2cache] 565type=BaseCache 566children=tags 567addr_ranges=0:18446744073709551615 568assoc=8 569clk_domain=system.cpu_clk_domain | 523eventq_index=0 524forward_snoops=true 525hit_latency=2 526is_top_level=true 527max_miss_count=0 528mshrs=4 529prefetch_on_access=false 530prefetcher=Null --- 33 unchanged lines hidden (view full) --- 564size=48 565 566[system.cpu.l2cache] 567type=BaseCache 568children=tags 569addr_ranges=0:18446744073709551615 570assoc=8 571clk_domain=system.cpu_clk_domain |
| 572demand_mshr_reserve=1 |
|
| 570eventq_index=0 571forward_snoops=true 572hit_latency=20 573is_top_level=false 574max_miss_count=0 575mshrs=20 576prefetch_on_access=false 577prefetcher=Null --- 17 unchanged lines hidden (view full) --- 595hit_latency=20 596sequential_access=false 597size=4194304 598 599[system.cpu.toL2Bus] 600type=CoherentXBar 601clk_domain=system.cpu_clk_domain 602eventq_index=0 | 573eventq_index=0 574forward_snoops=true 575hit_latency=20 576is_top_level=false 577max_miss_count=0 578mshrs=20 579prefetch_on_access=false 580prefetcher=Null --- 17 unchanged lines hidden (view full) --- 598hit_latency=20 599sequential_access=false 600size=4194304 601 602[system.cpu.toL2Bus] 603type=CoherentXBar 604clk_domain=system.cpu_clk_domain 605eventq_index=0 |
| 603header_cycles=1 | 606forward_latency=0 607frontend_latency=1 608response_latency=1 |
| 604snoop_filter=Null | 609snoop_filter=Null |
| 610snoop_response_latency=1 |
|
| 605system=system 606use_default_range=false 607width=32 608master=system.cpu.l2cache.cpu_side 609slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 610 611[system.cpu.tracer] 612type=ExeTracer --- 22 unchanged lines hidden (view full) --- 635eventq_index=0 636image_file= 637read_only=false 638table_size=65536 639 640[system.disk0.image.child] 641type=RawDiskImage 642eventq_index=0 | 611system=system 612use_default_range=false 613width=32 614master=system.cpu.l2cache.cpu_side 615slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 616 617[system.cpu.tracer] 618type=ExeTracer --- 22 unchanged lines hidden (view full) --- 641eventq_index=0 642image_file= 643read_only=false 644table_size=65536 645 646[system.disk0.image.child] 647type=RawDiskImage 648eventq_index=0 |
| 643image_file=/dist/disks/linux-latest.img | 649image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img |
| 644read_only=true 645 646[system.disk2] 647type=IdeDisk 648children=image 649delay=1000000 650driveID=master 651eventq_index=0 --- 6 unchanged lines hidden (view full) --- 658eventq_index=0 659image_file= 660read_only=false 661table_size=65536 662 663[system.disk2.image.child] 664type=RawDiskImage 665eventq_index=0 | 650read_only=true 651 652[system.disk2] 653type=IdeDisk 654children=image 655delay=1000000 656driveID=master 657eventq_index=0 --- 6 unchanged lines hidden (view full) --- 664eventq_index=0 665image_file= 666read_only=false 667table_size=65536 668 669[system.disk2.image.child] 670type=RawDiskImage 671eventq_index=0 |
| 666image_file=/dist/disks/linux-bigswap2.img | 672image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img |
| 667read_only=true 668 669[system.dvfs_handler] 670type=DVFSHandler 671domains= 672enable=false 673eventq_index=0 674sys_clk_domain=system.clk_domain 675transition_latency=100000000 676 677[system.intrctrl] 678type=IntrControl 679eventq_index=0 680sys=system 681 682[system.iobus] 683type=NoncoherentXBar 684clk_domain=system.clk_domain 685eventq_index=0 | 673read_only=true 674 675[system.dvfs_handler] 676type=DVFSHandler 677domains= 678enable=false 679eventq_index=0 680sys_clk_domain=system.clk_domain 681transition_latency=100000000 682 683[system.intrctrl] 684type=IntrControl 685eventq_index=0 686sys=system 687 688[system.iobus] 689type=NoncoherentXBar 690clk_domain=system.clk_domain 691eventq_index=0 |
| 686header_cycles=1 | 692forward_latency=1 693frontend_latency=2 694response_latency=2 |
| 687use_default_range=true | 695use_default_range=true |
| 688width=8 | 696width=16 |
| 689default=system.tsunami.pciconfig.pio 690master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 691slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 692 693[system.iocache] 694type=BaseCache 695children=tags 696addr_ranges=0:134217727 697assoc=8 698clk_domain=system.clk_domain | 697default=system.tsunami.pciconfig.pio 698master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 699slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 700 701[system.iocache] 702type=BaseCache 703children=tags 704addr_ranges=0:134217727 705assoc=8 706clk_domain=system.clk_domain |
| 707demand_mshr_reserve=1 |
|
| 699eventq_index=0 700forward_snoops=false 701hit_latency=50 702is_top_level=true 703max_miss_count=0 704mshrs=20 705prefetch_on_access=false 706prefetcher=Null --- 18 unchanged lines hidden (view full) --- 725sequential_access=false 726size=1024 727 728[system.membus] 729type=CoherentXBar 730children=badaddr_responder 731clk_domain=system.clk_domain 732eventq_index=0 | 708eventq_index=0 709forward_snoops=false 710hit_latency=50 711is_top_level=true 712max_miss_count=0 713mshrs=20 714prefetch_on_access=false 715prefetcher=Null --- 18 unchanged lines hidden (view full) --- 734sequential_access=false 735size=1024 736 737[system.membus] 738type=CoherentXBar 739children=badaddr_responder 740clk_domain=system.clk_domain 741eventq_index=0 |
| 733header_cycles=1 | 742forward_latency=4 743frontend_latency=3 744response_latency=2 |
| 734snoop_filter=Null | 745snoop_filter=Null |
| 746snoop_response_latency=4 |
|
| 735system=system 736use_default_range=false | 747system=system 748use_default_range=false |
| 737width=8 | 749width=16 |
| 738default=system.membus.badaddr_responder.pio 739master=system.bridge.slave system.physmem.port 740slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 741 742[system.membus.badaddr_responder] 743type=IsaFake 744clk_domain=system.clk_domain 745eventq_index=0 --- 33 unchanged lines hidden (view full) --- 779IDD4W2=0.000000 780IDD5=0.220000 781IDD52=0.000000 782IDD6=0.000000 783IDD62=0.000000 784VDD=1.500000 785VDD2=0.000000 786activation_limit=4 | 750default=system.membus.badaddr_responder.pio 751master=system.bridge.slave system.physmem.port 752slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 753 754[system.membus.badaddr_responder] 755type=IsaFake 756clk_domain=system.clk_domain 757eventq_index=0 --- 33 unchanged lines hidden (view full) --- 791IDD4W2=0.000000 792IDD5=0.220000 793IDD52=0.000000 794IDD6=0.000000 795IDD62=0.000000 796VDD=1.500000 797VDD2=0.000000 798activation_limit=4 |
| 787addr_mapping=RoRaBaChCo | 799addr_mapping=RoRaBaCoCh |
| 788bank_groups_per_rank=0 789banks_per_rank=8 790burst_length=8 791channels=1 792clk_domain=system.clk_domain 793conf_table_reported=true 794device_bus_width=8 795device_rowbuffer_size=1024 --- 43 unchanged lines hidden (view full) --- 839children=disk 840disk=system.simple_disk.disk 841eventq_index=0 842system=system 843 844[system.simple_disk.disk] 845type=RawDiskImage 846eventq_index=0 | 800bank_groups_per_rank=0 801banks_per_rank=8 802burst_length=8 803channels=1 804clk_domain=system.clk_domain 805conf_table_reported=true 806device_bus_width=8 807device_rowbuffer_size=1024 --- 43 unchanged lines hidden (view full) --- 851children=disk 852disk=system.simple_disk.disk 853eventq_index=0 854system=system 855 856[system.simple_disk.disk] 857type=RawDiskImage 858eventq_index=0 |
| 847image_file=/dist/disks/linux-latest.img | 859image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img |
| 848read_only=true 849 850[system.terminal] 851type=Terminal 852eventq_index=0 853intr_control=system.intrctrl 854number=0 855output=true --- 629 unchanged lines hidden --- | 860read_only=true 861 862[system.terminal] 863type=Terminal 864eventq_index=0 865intr_control=system.intrctrl 866number=0 867output=true --- 629 unchanged lines hidden --- |