Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini

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config.ini (9348:44d31345e360)	config.ini (9449:56610ab73040)
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxAlphaSystem 11children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami 12boot_cpu_frequency=500 13boot_osflags=root=/dev/hda1 console=ttyS0 14clock=1000	1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxAlphaSystem 11children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami 12boot_cpu_frequency=500 13boot_osflags=root=/dev/hda1 console=ttyS0 14clock=1000
15console=/projects/pd/randd/dist/binaries/console	15console=/gem5/dist/binaries/console
16init_param=0	16init_param=0
17kernel=/projects/pd/randd/dist/binaries/vmlinux	17kernel=/gem5/dist/binaries/vmlinux
18load_addr_mask=1099511627775 19mem_mode=timing	18load_addr_mask=1099511627775 19mem_mode=timing
	20mem_ranges=0:134217727
20memories=system.physmem 21num_work_ids=16	21memories=system.physmem 22num_work_ids=16
22pal=/projects/pd/randd/dist/binaries/ts_osfpal	23pal=/gem5/dist/binaries/ts_osfpal
23readfile=tests/halt.sh 24symbolfile= 25system_rev=1024 26system_type=34 27work_begin_ckpt_count=0 28work_begin_cpu_id_exit=-1 29work_begin_exit_count=0 30work_cpus_ckpt_count=0 31work_end_ckpt_count=0 32work_end_exit_count=0 33work_item_id=-1 34system_port=system.membus.slave[0] 35 36[system.bridge] 37type=Bridge 38clock=1000 39delay=50000 40ranges=8796093022208:18446744073709551615 41req_size=16 42resp_size=16 43master=system.iobus.slave[0] 44slave=system.membus.master[0] 45 46[system.cpu] 47type=DerivO3CPU 48children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer 49BTBEntries=4096 50BTBTagSize=16 51LFSTSize=1024 52LQEntries=32 53LSQCheckLoads=true 54LSQDepCheckShift=4 55RASSize=16 56SQEntries=32 57SSITSize=1024 58activity=0 59backComSize=5 60cachePorts=200 61checker=Null 62choiceCtrBits=2 63choicePredictorSize=8192 64clock=500 65commitToDecodeDelay=1 66commitToFetchDelay=1 67commitToIEWDelay=1 68commitToRenameDelay=1 69commitWidth=8 70cpu_id=0 71decodeToFetchDelay=1 72decodeToRenameDelay=1 73decodeWidth=8	24readfile=tests/halt.sh 25symbolfile= 26system_rev=1024 27system_type=34 28work_begin_ckpt_count=0 29work_begin_cpu_id_exit=-1 30work_begin_exit_count=0 31work_cpus_ckpt_count=0 32work_end_ckpt_count=0 33work_end_exit_count=0 34work_item_id=-1 35system_port=system.membus.slave[0] 36 37[system.bridge] 38type=Bridge 39clock=1000 40delay=50000 41ranges=8796093022208:18446744073709551615 42req_size=16 43resp_size=16 44master=system.iobus.slave[0] 45slave=system.membus.master[0] 46 47[system.cpu] 48type=DerivO3CPU 49children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer 50BTBEntries=4096 51BTBTagSize=16 52LFSTSize=1024 53LQEntries=32 54LSQCheckLoads=true 55LSQDepCheckShift=4 56RASSize=16 57SQEntries=32 58SSITSize=1024 59activity=0 60backComSize=5 61cachePorts=200 62checker=Null 63choiceCtrBits=2 64choicePredictorSize=8192 65clock=500 66commitToDecodeDelay=1 67commitToFetchDelay=1 68commitToIEWDelay=1 69commitToRenameDelay=1 70commitWidth=8 71cpu_id=0 72decodeToFetchDelay=1 73decodeToRenameDelay=1 74decodeWidth=8
74defer_registration=false
75dispatchWidth=8 76do_checkpoint_insts=true 77do_quiesce=true 78do_statistics_insts=true 79dtb=system.cpu.dtb 80fetchToDecodeDelay=1 81fetchTrapLatency=1 82fetchWidth=8 83forwardComSize=5 84fuPool=system.cpu.fuPool 85function_trace=false 86function_trace_start=0 87globalCtrBits=2 88globalHistoryBits=13 89globalPredictorSize=8192 90iewToCommitDelay=1 91iewToDecodeDelay=1 92iewToFetchDelay=1 93iewToRenameDelay=1 94instShiftAmt=2 95interrupts=system.cpu.interrupts 96isa=system.cpu.isa 97issueToExecuteDelay=1 98issueWidth=8 99itb=system.cpu.itb 100localCtrBits=2 101localHistoryBits=11 102localHistoryTableSize=2048 103localPredictorSize=2048 104max_insts_all_threads=0 105max_insts_any_thread=0 106max_loads_all_threads=0 107max_loads_any_thread=0 108needsTSO=false 109numIQEntries=64 110numPhysFloatRegs=256 111numPhysIntRegs=256 112numROBEntries=192 113numRobs=1 114numThreads=1 115predType=tournament 116profile=0 117progress_interval=0 118renameToDecodeDelay=1 119renameToFetchDelay=1 120renameToIEWDelay=2 121renameToROBDelay=1 122renameWidth=8 123smtCommitPolicy=RoundRobin 124smtFetchPolicy=SingleThread 125smtIQPolicy=Partitioned 126smtIQThreshold=100 127smtLSQPolicy=Partitioned 128smtLSQThreshold=100 129smtNumFetchingThreads=1 130smtROBPolicy=Partitioned 131smtROBThreshold=100 132squashWidth=8 133store_set_clear_period=250000	75dispatchWidth=8 76do_checkpoint_insts=true 77do_quiesce=true 78do_statistics_insts=true 79dtb=system.cpu.dtb 80fetchToDecodeDelay=1 81fetchTrapLatency=1 82fetchWidth=8 83forwardComSize=5 84fuPool=system.cpu.fuPool 85function_trace=false 86function_trace_start=0 87globalCtrBits=2 88globalHistoryBits=13 89globalPredictorSize=8192 90iewToCommitDelay=1 91iewToDecodeDelay=1 92iewToFetchDelay=1 93iewToRenameDelay=1 94instShiftAmt=2 95interrupts=system.cpu.interrupts 96isa=system.cpu.isa 97issueToExecuteDelay=1 98issueWidth=8 99itb=system.cpu.itb 100localCtrBits=2 101localHistoryBits=11 102localHistoryTableSize=2048 103localPredictorSize=2048 104max_insts_all_threads=0 105max_insts_any_thread=0 106max_loads_all_threads=0 107max_loads_any_thread=0 108needsTSO=false 109numIQEntries=64 110numPhysFloatRegs=256 111numPhysIntRegs=256 112numROBEntries=192 113numRobs=1 114numThreads=1 115predType=tournament 116profile=0 117progress_interval=0 118renameToDecodeDelay=1 119renameToFetchDelay=1 120renameToIEWDelay=2 121renameToROBDelay=1 122renameWidth=8 123smtCommitPolicy=RoundRobin 124smtFetchPolicy=SingleThread 125smtIQPolicy=Partitioned 126smtIQThreshold=100 127smtLSQPolicy=Partitioned 128smtLSQThreshold=100 129smtNumFetchingThreads=1 130smtROBPolicy=Partitioned 131smtROBThreshold=100 132squashWidth=8 133store_set_clear_period=250000
	134switched_out=false
134system=system 135tracer=system.cpu.tracer 136trapLatency=13 137wbDepth=1 138wbWidth=8 139workload= 140dcache_port=system.cpu.dcache.cpu_side 141icache_port=system.cpu.icache.cpu_side 142 143[system.cpu.dcache] 144type=BaseCache 145addr_ranges=0:18446744073709551615 146assoc=4 147block_size=64 148clock=500 149forward_snoops=true	135system=system 136tracer=system.cpu.tracer 137trapLatency=13 138wbDepth=1 139wbWidth=8 140workload= 141dcache_port=system.cpu.dcache.cpu_side 142icache_port=system.cpu.icache.cpu_side 143 144[system.cpu.dcache] 145type=BaseCache 146addr_ranges=0:18446744073709551615 147assoc=4 148block_size=64 149clock=500 150forward_snoops=true
150hash_delay=1
151hit_latency=2 152is_top_level=true 153max_miss_count=0 154mshrs=4 155prefetch_on_access=false 156prefetcher=Null	151hit_latency=2 152is_top_level=true 153max_miss_count=0 154mshrs=4 155prefetch_on_access=false 156prefetcher=Null
157prioritizeRequests=false 158repl=Null
159response_latency=2 160size=32768	157response_latency=2 158size=32768
161subblock_size=0
162system=system 163tgts_per_mshr=20	159system=system 160tgts_per_mshr=20
164trace_addr=0
165two_queue=false 166write_buffers=8 167cpu_side=system.cpu.dcache_port 168mem_side=system.cpu.toL2Bus.slave[1] 169 170[system.cpu.dtb] 171type=AlphaTLB 172size=64 173 174[system.cpu.fuPool] 175type=FUPool 176children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 177FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 178 179[system.cpu.fuPool.FUList0] 180type=FUDesc 181children=opList 182count=6 183opList=system.cpu.fuPool.FUList0.opList 184 185[system.cpu.fuPool.FUList0.opList] 186type=OpDesc 187issueLat=1 188opClass=IntAlu 189opLat=1 190 191[system.cpu.fuPool.FUList1] 192type=FUDesc 193children=opList0 opList1 194count=2 195opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 196 197[system.cpu.fuPool.FUList1.opList0] 198type=OpDesc 199issueLat=1 200opClass=IntMult 201opLat=3 202 203[system.cpu.fuPool.FUList1.opList1] 204type=OpDesc 205issueLat=19 206opClass=IntDiv 207opLat=20 208 209[system.cpu.fuPool.FUList2] 210type=FUDesc 211children=opList0 opList1 opList2 212count=4 213opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 214 215[system.cpu.fuPool.FUList2.opList0] 216type=OpDesc 217issueLat=1 218opClass=FloatAdd 219opLat=2 220 221[system.cpu.fuPool.FUList2.opList1] 222type=OpDesc 223issueLat=1 224opClass=FloatCmp 225opLat=2 226 227[system.cpu.fuPool.FUList2.opList2] 228type=OpDesc 229issueLat=1 230opClass=FloatCvt 231opLat=2 232 233[system.cpu.fuPool.FUList3] 234type=FUDesc 235children=opList0 opList1 opList2 236count=2 237opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 238 239[system.cpu.fuPool.FUList3.opList0] 240type=OpDesc 241issueLat=1 242opClass=FloatMult 243opLat=4 244 245[system.cpu.fuPool.FUList3.opList1] 246type=OpDesc 247issueLat=12 248opClass=FloatDiv 249opLat=12 250 251[system.cpu.fuPool.FUList3.opList2] 252type=OpDesc 253issueLat=24 254opClass=FloatSqrt 255opLat=24 256 257[system.cpu.fuPool.FUList4] 258type=FUDesc 259children=opList 260count=0 261opList=system.cpu.fuPool.FUList4.opList 262 263[system.cpu.fuPool.FUList4.opList] 264type=OpDesc 265issueLat=1 266opClass=MemRead 267opLat=1 268 269[system.cpu.fuPool.FUList5] 270type=FUDesc 271children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 272count=4 273opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 274 275[system.cpu.fuPool.FUList5.opList00] 276type=OpDesc 277issueLat=1 278opClass=SimdAdd 279opLat=1 280 281[system.cpu.fuPool.FUList5.opList01] 282type=OpDesc 283issueLat=1 284opClass=SimdAddAcc 285opLat=1 286 287[system.cpu.fuPool.FUList5.opList02] 288type=OpDesc 289issueLat=1 290opClass=SimdAlu 291opLat=1 292 293[system.cpu.fuPool.FUList5.opList03] 294type=OpDesc 295issueLat=1 296opClass=SimdCmp 297opLat=1 298 299[system.cpu.fuPool.FUList5.opList04] 300type=OpDesc 301issueLat=1 302opClass=SimdCvt 303opLat=1 304 305[system.cpu.fuPool.FUList5.opList05] 306type=OpDesc 307issueLat=1 308opClass=SimdMisc 309opLat=1 310 311[system.cpu.fuPool.FUList5.opList06] 312type=OpDesc 313issueLat=1 314opClass=SimdMult 315opLat=1 316 317[system.cpu.fuPool.FUList5.opList07] 318type=OpDesc 319issueLat=1 320opClass=SimdMultAcc 321opLat=1 322 323[system.cpu.fuPool.FUList5.opList08] 324type=OpDesc 325issueLat=1 326opClass=SimdShift 327opLat=1 328 329[system.cpu.fuPool.FUList5.opList09] 330type=OpDesc 331issueLat=1 332opClass=SimdShiftAcc 333opLat=1 334 335[system.cpu.fuPool.FUList5.opList10] 336type=OpDesc 337issueLat=1 338opClass=SimdSqrt 339opLat=1 340 341[system.cpu.fuPool.FUList5.opList11] 342type=OpDesc 343issueLat=1 344opClass=SimdFloatAdd 345opLat=1 346 347[system.cpu.fuPool.FUList5.opList12] 348type=OpDesc 349issueLat=1 350opClass=SimdFloatAlu 351opLat=1 352 353[system.cpu.fuPool.FUList5.opList13] 354type=OpDesc 355issueLat=1 356opClass=SimdFloatCmp 357opLat=1 358 359[system.cpu.fuPool.FUList5.opList14] 360type=OpDesc 361issueLat=1 362opClass=SimdFloatCvt 363opLat=1 364 365[system.cpu.fuPool.FUList5.opList15] 366type=OpDesc 367issueLat=1 368opClass=SimdFloatDiv 369opLat=1 370 371[system.cpu.fuPool.FUList5.opList16] 372type=OpDesc 373issueLat=1 374opClass=SimdFloatMisc 375opLat=1 376 377[system.cpu.fuPool.FUList5.opList17] 378type=OpDesc 379issueLat=1 380opClass=SimdFloatMult 381opLat=1 382 383[system.cpu.fuPool.FUList5.opList18] 384type=OpDesc 385issueLat=1 386opClass=SimdFloatMultAcc 387opLat=1 388 389[system.cpu.fuPool.FUList5.opList19] 390type=OpDesc 391issueLat=1 392opClass=SimdFloatSqrt 393opLat=1 394 395[system.cpu.fuPool.FUList6] 396type=FUDesc 397children=opList 398count=0 399opList=system.cpu.fuPool.FUList6.opList 400 401[system.cpu.fuPool.FUList6.opList] 402type=OpDesc 403issueLat=1 404opClass=MemWrite 405opLat=1 406 407[system.cpu.fuPool.FUList7] 408type=FUDesc 409children=opList0 opList1 410count=4 411opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 412 413[system.cpu.fuPool.FUList7.opList0] 414type=OpDesc 415issueLat=1 416opClass=MemRead 417opLat=1 418 419[system.cpu.fuPool.FUList7.opList1] 420type=OpDesc 421issueLat=1 422opClass=MemWrite 423opLat=1 424 425[system.cpu.fuPool.FUList8] 426type=FUDesc 427children=opList 428count=1 429opList=system.cpu.fuPool.FUList8.opList 430 431[system.cpu.fuPool.FUList8.opList] 432type=OpDesc 433issueLat=3 434opClass=IprAccess 435opLat=3 436 437[system.cpu.icache] 438type=BaseCache 439addr_ranges=0:18446744073709551615 440assoc=1 441block_size=64 442clock=500 443forward_snoops=true	161two_queue=false 162write_buffers=8 163cpu_side=system.cpu.dcache_port 164mem_side=system.cpu.toL2Bus.slave[1] 165 166[system.cpu.dtb] 167type=AlphaTLB 168size=64 169 170[system.cpu.fuPool] 171type=FUPool 172children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 173FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 174 175[system.cpu.fuPool.FUList0] 176type=FUDesc 177children=opList 178count=6 179opList=system.cpu.fuPool.FUList0.opList 180 181[system.cpu.fuPool.FUList0.opList] 182type=OpDesc 183issueLat=1 184opClass=IntAlu 185opLat=1 186 187[system.cpu.fuPool.FUList1] 188type=FUDesc 189children=opList0 opList1 190count=2 191opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 192 193[system.cpu.fuPool.FUList1.opList0] 194type=OpDesc 195issueLat=1 196opClass=IntMult 197opLat=3 198 199[system.cpu.fuPool.FUList1.opList1] 200type=OpDesc 201issueLat=19 202opClass=IntDiv 203opLat=20 204 205[system.cpu.fuPool.FUList2] 206type=FUDesc 207children=opList0 opList1 opList2 208count=4 209opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 210 211[system.cpu.fuPool.FUList2.opList0] 212type=OpDesc 213issueLat=1 214opClass=FloatAdd 215opLat=2 216 217[system.cpu.fuPool.FUList2.opList1] 218type=OpDesc 219issueLat=1 220opClass=FloatCmp 221opLat=2 222 223[system.cpu.fuPool.FUList2.opList2] 224type=OpDesc 225issueLat=1 226opClass=FloatCvt 227opLat=2 228 229[system.cpu.fuPool.FUList3] 230type=FUDesc 231children=opList0 opList1 opList2 232count=2 233opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 234 235[system.cpu.fuPool.FUList3.opList0] 236type=OpDesc 237issueLat=1 238opClass=FloatMult 239opLat=4 240 241[system.cpu.fuPool.FUList3.opList1] 242type=OpDesc 243issueLat=12 244opClass=FloatDiv 245opLat=12 246 247[system.cpu.fuPool.FUList3.opList2] 248type=OpDesc 249issueLat=24 250opClass=FloatSqrt 251opLat=24 252 253[system.cpu.fuPool.FUList4] 254type=FUDesc 255children=opList 256count=0 257opList=system.cpu.fuPool.FUList4.opList 258 259[system.cpu.fuPool.FUList4.opList] 260type=OpDesc 261issueLat=1 262opClass=MemRead 263opLat=1 264 265[system.cpu.fuPool.FUList5] 266type=FUDesc 267children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 268count=4 269opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 270 271[system.cpu.fuPool.FUList5.opList00] 272type=OpDesc 273issueLat=1 274opClass=SimdAdd 275opLat=1 276 277[system.cpu.fuPool.FUList5.opList01] 278type=OpDesc 279issueLat=1 280opClass=SimdAddAcc 281opLat=1 282 283[system.cpu.fuPool.FUList5.opList02] 284type=OpDesc 285issueLat=1 286opClass=SimdAlu 287opLat=1 288 289[system.cpu.fuPool.FUList5.opList03] 290type=OpDesc 291issueLat=1 292opClass=SimdCmp 293opLat=1 294 295[system.cpu.fuPool.FUList5.opList04] 296type=OpDesc 297issueLat=1 298opClass=SimdCvt 299opLat=1 300 301[system.cpu.fuPool.FUList5.opList05] 302type=OpDesc 303issueLat=1 304opClass=SimdMisc 305opLat=1 306 307[system.cpu.fuPool.FUList5.opList06] 308type=OpDesc 309issueLat=1 310opClass=SimdMult 311opLat=1 312 313[system.cpu.fuPool.FUList5.opList07] 314type=OpDesc 315issueLat=1 316opClass=SimdMultAcc 317opLat=1 318 319[system.cpu.fuPool.FUList5.opList08] 320type=OpDesc 321issueLat=1 322opClass=SimdShift 323opLat=1 324 325[system.cpu.fuPool.FUList5.opList09] 326type=OpDesc 327issueLat=1 328opClass=SimdShiftAcc 329opLat=1 330 331[system.cpu.fuPool.FUList5.opList10] 332type=OpDesc 333issueLat=1 334opClass=SimdSqrt 335opLat=1 336 337[system.cpu.fuPool.FUList5.opList11] 338type=OpDesc 339issueLat=1 340opClass=SimdFloatAdd 341opLat=1 342 343[system.cpu.fuPool.FUList5.opList12] 344type=OpDesc 345issueLat=1 346opClass=SimdFloatAlu 347opLat=1 348 349[system.cpu.fuPool.FUList5.opList13] 350type=OpDesc 351issueLat=1 352opClass=SimdFloatCmp 353opLat=1 354 355[system.cpu.fuPool.FUList5.opList14] 356type=OpDesc 357issueLat=1 358opClass=SimdFloatCvt 359opLat=1 360 361[system.cpu.fuPool.FUList5.opList15] 362type=OpDesc 363issueLat=1 364opClass=SimdFloatDiv 365opLat=1 366 367[system.cpu.fuPool.FUList5.opList16] 368type=OpDesc 369issueLat=1 370opClass=SimdFloatMisc 371opLat=1 372 373[system.cpu.fuPool.FUList5.opList17] 374type=OpDesc 375issueLat=1 376opClass=SimdFloatMult 377opLat=1 378 379[system.cpu.fuPool.FUList5.opList18] 380type=OpDesc 381issueLat=1 382opClass=SimdFloatMultAcc 383opLat=1 384 385[system.cpu.fuPool.FUList5.opList19] 386type=OpDesc 387issueLat=1 388opClass=SimdFloatSqrt 389opLat=1 390 391[system.cpu.fuPool.FUList6] 392type=FUDesc 393children=opList 394count=0 395opList=system.cpu.fuPool.FUList6.opList 396 397[system.cpu.fuPool.FUList6.opList] 398type=OpDesc 399issueLat=1 400opClass=MemWrite 401opLat=1 402 403[system.cpu.fuPool.FUList7] 404type=FUDesc 405children=opList0 opList1 406count=4 407opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 408 409[system.cpu.fuPool.FUList7.opList0] 410type=OpDesc 411issueLat=1 412opClass=MemRead 413opLat=1 414 415[system.cpu.fuPool.FUList7.opList1] 416type=OpDesc 417issueLat=1 418opClass=MemWrite 419opLat=1 420 421[system.cpu.fuPool.FUList8] 422type=FUDesc 423children=opList 424count=1 425opList=system.cpu.fuPool.FUList8.opList 426 427[system.cpu.fuPool.FUList8.opList] 428type=OpDesc 429issueLat=3 430opClass=IprAccess 431opLat=3 432 433[system.cpu.icache] 434type=BaseCache 435addr_ranges=0:18446744073709551615 436assoc=1 437block_size=64 438clock=500 439forward_snoops=true
444hash_delay=1
445hit_latency=2 446is_top_level=true 447max_miss_count=0 448mshrs=4 449prefetch_on_access=false 450prefetcher=Null	440hit_latency=2 441is_top_level=true 442max_miss_count=0 443mshrs=4 444prefetch_on_access=false 445prefetcher=Null
451prioritizeRequests=false 452repl=Null
453response_latency=2 454size=32768	446response_latency=2 447size=32768
455subblock_size=0
456system=system 457tgts_per_mshr=20	448system=system 449tgts_per_mshr=20
458trace_addr=0
459two_queue=false 460write_buffers=8 461cpu_side=system.cpu.icache_port 462mem_side=system.cpu.toL2Bus.slave[0] 463 464[system.cpu.interrupts] 465type=AlphaInterrupts 466 467[system.cpu.isa] 468type=AlphaISA 469 470[system.cpu.itb] 471type=AlphaTLB 472size=48 473 474[system.cpu.l2cache] 475type=BaseCache 476addr_ranges=0:18446744073709551615 477assoc=8 478block_size=64 479clock=500 480forward_snoops=true	450two_queue=false 451write_buffers=8 452cpu_side=system.cpu.icache_port 453mem_side=system.cpu.toL2Bus.slave[0] 454 455[system.cpu.interrupts] 456type=AlphaInterrupts 457 458[system.cpu.isa] 459type=AlphaISA 460 461[system.cpu.itb] 462type=AlphaTLB 463size=48 464 465[system.cpu.l2cache] 466type=BaseCache 467addr_ranges=0:18446744073709551615 468assoc=8 469block_size=64 470clock=500 471forward_snoops=true
481hash_delay=1
482hit_latency=20 483is_top_level=false 484max_miss_count=0 485mshrs=20 486prefetch_on_access=false 487prefetcher=Null	472hit_latency=20 473is_top_level=false 474max_miss_count=0 475mshrs=20 476prefetch_on_access=false 477prefetcher=Null
488prioritizeRequests=false 489repl=Null
490response_latency=20 491size=4194304	478response_latency=20 479size=4194304
492subblock_size=0
493system=system 494tgts_per_mshr=12	480system=system 481tgts_per_mshr=12
495trace_addr=0
496two_queue=false 497write_buffers=8 498cpu_side=system.cpu.toL2Bus.master[0]	482two_queue=false 483write_buffers=8 484cpu_side=system.cpu.toL2Bus.master[0]
499mem_side=system.membus.slave[2]	485mem_side=system.membus.slave[1]
500 501[system.cpu.toL2Bus] 502type=CoherentBus 503block_size=64 504clock=500 505header_cycles=1 506use_default_range=false 507width=32 508master=system.cpu.l2cache.cpu_side 509slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 510 511[system.cpu.tracer] 512type=ExeTracer 513 514[system.disk0] 515type=IdeDisk 516children=image 517delay=1000000 518driveID=master 519image=system.disk0.image 520 521[system.disk0.image] 522type=CowDiskImage 523children=child 524child=system.disk0.image.child 525image_file= 526read_only=false 527table_size=65536 528 529[system.disk0.image.child] 530type=RawDiskImage	486 487[system.cpu.toL2Bus] 488type=CoherentBus 489block_size=64 490clock=500 491header_cycles=1 492use_default_range=false 493width=32 494master=system.cpu.l2cache.cpu_side 495slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 496 497[system.cpu.tracer] 498type=ExeTracer 499 500[system.disk0] 501type=IdeDisk 502children=image 503delay=1000000 504driveID=master 505image=system.disk0.image 506 507[system.disk0.image] 508type=CowDiskImage 509children=child 510child=system.disk0.image.child 511image_file= 512read_only=false 513table_size=65536 514 515[system.disk0.image.child] 516type=RawDiskImage
531image_file=/projects/pd/randd/dist/disks/linux-latest.img	517image_file=/gem5/dist/disks/linux-latest.img
532read_only=true 533 534[system.disk2] 535type=IdeDisk 536children=image 537delay=1000000 538driveID=master 539image=system.disk2.image 540 541[system.disk2.image] 542type=CowDiskImage 543children=child 544child=system.disk2.image.child 545image_file= 546read_only=false 547table_size=65536 548 549[system.disk2.image.child] 550type=RawDiskImage	518read_only=true 519 520[system.disk2] 521type=IdeDisk 522children=image 523delay=1000000 524driveID=master 525image=system.disk2.image 526 527[system.disk2.image] 528type=CowDiskImage 529children=child 530child=system.disk2.image.child 531image_file= 532read_only=false 533table_size=65536 534 535[system.disk2.image.child] 536type=RawDiskImage
551image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img	537image_file=/gem5/dist/disks/linux-bigswap2.img
552read_only=true 553 554[system.intrctrl] 555type=IntrControl 556sys=system 557 558[system.iobus] 559type=NoncoherentBus 560block_size=64 561clock=1000 562header_cycles=1 563use_default_range=true 564width=8 565default=system.tsunami.pciconfig.pio 566master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 567slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 568 569[system.iocache] 570type=BaseCache	538read_only=true 539 540[system.intrctrl] 541type=IntrControl 542sys=system 543 544[system.iobus] 545type=NoncoherentBus 546block_size=64 547clock=1000 548header_cycles=1 549use_default_range=true 550width=8 551default=system.tsunami.pciconfig.pio 552master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 553slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 554 555[system.iocache] 556type=BaseCache
571addr_ranges=0:8589934591	557addr_ranges=0:134217727
572assoc=8 573block_size=64 574clock=1000 575forward_snoops=false	558assoc=8 559block_size=64 560clock=1000 561forward_snoops=false
576hash_delay=1
577hit_latency=50 578is_top_level=true 579max_miss_count=0 580mshrs=20 581prefetch_on_access=false 582prefetcher=Null	562hit_latency=50 563is_top_level=true 564max_miss_count=0 565mshrs=20 566prefetch_on_access=false 567prefetcher=Null
583prioritizeRequests=false 584repl=Null
585response_latency=50 586size=1024	568response_latency=50 569size=1024
587subblock_size=0
588system=system 589tgts_per_mshr=12	570system=system 571tgts_per_mshr=12
590trace_addr=0
591two_queue=false 592write_buffers=8 593cpu_side=system.iobus.master[29]	572two_queue=false 573write_buffers=8 574cpu_side=system.iobus.master[29]
594mem_side=system.membus.slave[1]	575mem_side=system.membus.slave[2]
595 596[system.membus] 597type=CoherentBus 598children=badaddr_responder 599block_size=64 600clock=1000 601header_cycles=1 602use_default_range=false 603width=8 604default=system.membus.badaddr_responder.pio 605master=system.bridge.slave system.physmem.port	576 577[system.membus] 578type=CoherentBus 579children=badaddr_responder 580block_size=64 581clock=1000 582header_cycles=1 583use_default_range=false 584width=8 585default=system.membus.badaddr_responder.pio 586master=system.bridge.slave system.physmem.port
606slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side	587slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
607 608[system.membus.badaddr_responder] 609type=IsaFake 610clock=1000 611fake_mem=false 612pio_addr=0 613pio_latency=100000 614pio_size=8 615ret_bad_addr=true 616ret_data16=65535 617ret_data32=4294967295 618ret_data64=18446744073709551615 619ret_data8=255 620system=system 621update_data=false 622warn_access= 623pio=system.membus.default 624 625[system.physmem] 626type=SimpleDRAM 627addr_mapping=openmap 628banks_per_rank=8 629clock=1000 630conf_table_reported=false 631in_addr_map=true 632lines_per_rowbuffer=64 633mem_sched_policy=fcfs 634null=false 635page_policy=open 636range=0:134217727 637ranks_per_channel=2 638read_buffer_size=32 639tBURST=4000 640tCL=14000 641tRCD=14000 642tREFI=7800000 643tRFC=300000 644tRP=14000 645tWTR=1000 646write_buffer_size=32 647write_thresh_perc=70 648zero=false 649port=system.membus.master[1] 650 651[system.simple_disk] 652type=SimpleDisk 653children=disk 654disk=system.simple_disk.disk 655system=system 656 657[system.simple_disk.disk] 658type=RawDiskImage	588 589[system.membus.badaddr_responder] 590type=IsaFake 591clock=1000 592fake_mem=false 593pio_addr=0 594pio_latency=100000 595pio_size=8 596ret_bad_addr=true 597ret_data16=65535 598ret_data32=4294967295 599ret_data64=18446744073709551615 600ret_data8=255 601system=system 602update_data=false 603warn_access= 604pio=system.membus.default 605 606[system.physmem] 607type=SimpleDRAM 608addr_mapping=openmap 609banks_per_rank=8 610clock=1000 611conf_table_reported=false 612in_addr_map=true 613lines_per_rowbuffer=64 614mem_sched_policy=fcfs 615null=false 616page_policy=open 617range=0:134217727 618ranks_per_channel=2 619read_buffer_size=32 620tBURST=4000 621tCL=14000 622tRCD=14000 623tREFI=7800000 624tRFC=300000 625tRP=14000 626tWTR=1000 627write_buffer_size=32 628write_thresh_perc=70 629zero=false 630port=system.membus.master[1] 631 632[system.simple_disk] 633type=SimpleDisk 634children=disk 635disk=system.simple_disk.disk 636system=system 637 638[system.simple_disk.disk] 639type=RawDiskImage
659image_file=/projects/pd/randd/dist/disks/linux-latest.img	640image_file=/gem5/dist/disks/linux-latest.img
660read_only=true 661 662[system.terminal] 663type=Terminal 664intr_control=system.intrctrl 665number=0 666output=true 667port=3456 668 669[system.tsunami] 670type=Tsunami 671children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart 672intrctrl=system.intrctrl 673system=system 674 675[system.tsunami.backdoor] 676type=AlphaBackdoor 677clock=1000 678cpu=system.cpu 679disk=system.simple_disk 680pio_addr=8804682956800 681pio_latency=100000 682platform=system.tsunami 683system=system 684terminal=system.terminal 685pio=system.iobus.master[24] 686 687[system.tsunami.cchip] 688type=TsunamiCChip 689clock=1000 690pio_addr=8803072344064 691pio_latency=100000 692system=system 693tsunami=system.tsunami 694pio=system.iobus.master[0] 695 696[system.tsunami.ethernet] 697type=NSGigE 698BAR0=1 699BAR0LegacyIO=false 700BAR0Size=256 701BAR1=0 702BAR1LegacyIO=false 703BAR1Size=4096 704BAR2=0 705BAR2LegacyIO=false 706BAR2Size=0 707BAR3=0 708BAR3LegacyIO=false 709BAR3Size=0 710BAR4=0 711BAR4LegacyIO=false 712BAR4Size=0 713BAR5=0 714BAR5LegacyIO=false 715BAR5Size=0 716BIST=0 717CacheLineSize=0 718CardbusCIS=0 719ClassCode=2 720Command=0 721DeviceID=34 722ExpansionROM=0 723HeaderType=0 724InterruptLine=30 725InterruptPin=1 726LatencyTimer=0 727MaximumLatency=52 728MinimumGrant=176 729ProgIF=0 730Revision=0 731Status=656 732SubClassCode=0 733SubsystemID=0 734SubsystemVendorID=0 735VendorID=4107	641read_only=true 642 643[system.terminal] 644type=Terminal 645intr_control=system.intrctrl 646number=0 647output=true 648port=3456 649 650[system.tsunami] 651type=Tsunami 652children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart 653intrctrl=system.intrctrl 654system=system 655 656[system.tsunami.backdoor] 657type=AlphaBackdoor 658clock=1000 659cpu=system.cpu 660disk=system.simple_disk 661pio_addr=8804682956800 662pio_latency=100000 663platform=system.tsunami 664system=system 665terminal=system.terminal 666pio=system.iobus.master[24] 667 668[system.tsunami.cchip] 669type=TsunamiCChip 670clock=1000 671pio_addr=8803072344064 672pio_latency=100000 673system=system 674tsunami=system.tsunami 675pio=system.iobus.master[0] 676 677[system.tsunami.ethernet] 678type=NSGigE 679BAR0=1 680BAR0LegacyIO=false 681BAR0Size=256 682BAR1=0 683BAR1LegacyIO=false 684BAR1Size=4096 685BAR2=0 686BAR2LegacyIO=false 687BAR2Size=0 688BAR3=0 689BAR3LegacyIO=false 690BAR3Size=0 691BAR4=0 692BAR4LegacyIO=false 693BAR4Size=0 694BAR5=0 695BAR5LegacyIO=false 696BAR5Size=0 697BIST=0 698CacheLineSize=0 699CardbusCIS=0 700ClassCode=2 701Command=0 702DeviceID=34 703ExpansionROM=0 704HeaderType=0 705InterruptLine=30 706InterruptPin=1 707LatencyTimer=0 708MaximumLatency=52 709MinimumGrant=176 710ProgIF=0 711Revision=0 712Status=656 713SubClassCode=0 714SubsystemID=0 715SubsystemVendorID=0 716VendorID=4107
736clock=0	717clock=2000
737config_latency=20000 738dma_data_free=false 739dma_desc_free=false 740dma_no_allocate=true 741dma_read_delay=0 742dma_read_factor=0 743dma_write_delay=0 744dma_write_factor=0 745hardware_address=00:90:00:00:00:01 746intr_delay=10000000 747pci_bus=0 748pci_dev=1 749pci_func=0 750pio_latency=30000 751platform=system.tsunami 752rss=false 753rx_delay=1000000 754rx_fifo_size=524288 755rx_filter=true 756rx_thread=false 757system=system 758tx_delay=1000000 759tx_fifo_size=524288 760tx_thread=false 761config=system.iobus.master[28] 762dma=system.iobus.slave[2] 763pio=system.iobus.master[27] 764 765[system.tsunami.fake_OROM] 766type=IsaFake 767clock=1000 768fake_mem=false 769pio_addr=8796093677568 770pio_latency=100000 771pio_size=393216 772ret_bad_addr=false 773ret_data16=65535 774ret_data32=4294967295 775ret_data64=18446744073709551615 776ret_data8=255 777system=system 778update_data=false 779warn_access= 780pio=system.iobus.master[8] 781 782[system.tsunami.fake_ata0] 783type=IsaFake 784clock=1000 785fake_mem=false 786pio_addr=8804615848432 787pio_latency=100000 788pio_size=8 789ret_bad_addr=false 790ret_data16=65535 791ret_data32=4294967295 792ret_data64=18446744073709551615 793ret_data8=255 794system=system 795update_data=false 796warn_access= 797pio=system.iobus.master[19] 798 799[system.tsunami.fake_ata1] 800type=IsaFake 801clock=1000 802fake_mem=false 803pio_addr=8804615848304 804pio_latency=100000 805pio_size=8 806ret_bad_addr=false 807ret_data16=65535 808ret_data32=4294967295 809ret_data64=18446744073709551615 810ret_data8=255 811system=system 812update_data=false 813warn_access= 814pio=system.iobus.master[20] 815 816[system.tsunami.fake_pnp_addr] 817type=IsaFake 818clock=1000 819fake_mem=false 820pio_addr=8804615848569 821pio_latency=100000 822pio_size=8 823ret_bad_addr=false 824ret_data16=65535 825ret_data32=4294967295 826ret_data64=18446744073709551615 827ret_data8=255 828system=system 829update_data=false 830warn_access= 831pio=system.iobus.master[9] 832 833[system.tsunami.fake_pnp_read0] 834type=IsaFake 835clock=1000 836fake_mem=false 837pio_addr=8804615848451 838pio_latency=100000 839pio_size=8 840ret_bad_addr=false 841ret_data16=65535 842ret_data32=4294967295 843ret_data64=18446744073709551615 844ret_data8=255 845system=system 846update_data=false 847warn_access= 848pio=system.iobus.master[11] 849 850[system.tsunami.fake_pnp_read1] 851type=IsaFake 852clock=1000 853fake_mem=false 854pio_addr=8804615848515 855pio_latency=100000 856pio_size=8 857ret_bad_addr=false 858ret_data16=65535 859ret_data32=4294967295 860ret_data64=18446744073709551615 861ret_data8=255 862system=system 863update_data=false 864warn_access= 865pio=system.iobus.master[12] 866 867[system.tsunami.fake_pnp_read2] 868type=IsaFake 869clock=1000 870fake_mem=false 871pio_addr=8804615848579 872pio_latency=100000 873pio_size=8 874ret_bad_addr=false 875ret_data16=65535 876ret_data32=4294967295 877ret_data64=18446744073709551615 878ret_data8=255 879system=system 880update_data=false 881warn_access= 882pio=system.iobus.master[13] 883 884[system.tsunami.fake_pnp_read3] 885type=IsaFake 886clock=1000 887fake_mem=false 888pio_addr=8804615848643 889pio_latency=100000 890pio_size=8 891ret_bad_addr=false 892ret_data16=65535 893ret_data32=4294967295 894ret_data64=18446744073709551615 895ret_data8=255 896system=system 897update_data=false 898warn_access= 899pio=system.iobus.master[14] 900 901[system.tsunami.fake_pnp_read4] 902type=IsaFake 903clock=1000 904fake_mem=false 905pio_addr=8804615848707 906pio_latency=100000 907pio_size=8 908ret_bad_addr=false 909ret_data16=65535 910ret_data32=4294967295 911ret_data64=18446744073709551615 912ret_data8=255 913system=system 914update_data=false 915warn_access= 916pio=system.iobus.master[15] 917 918[system.tsunami.fake_pnp_read5] 919type=IsaFake 920clock=1000 921fake_mem=false 922pio_addr=8804615848771 923pio_latency=100000 924pio_size=8 925ret_bad_addr=false 926ret_data16=65535 927ret_data32=4294967295 928ret_data64=18446744073709551615 929ret_data8=255 930system=system 931update_data=false 932warn_access= 933pio=system.iobus.master[16] 934 935[system.tsunami.fake_pnp_read6] 936type=IsaFake 937clock=1000 938fake_mem=false 939pio_addr=8804615848835 940pio_latency=100000 941pio_size=8 942ret_bad_addr=false 943ret_data16=65535 944ret_data32=4294967295 945ret_data64=18446744073709551615 946ret_data8=255 947system=system 948update_data=false 949warn_access= 950pio=system.iobus.master[17] 951 952[system.tsunami.fake_pnp_read7] 953type=IsaFake 954clock=1000 955fake_mem=false 956pio_addr=8804615848899 957pio_latency=100000 958pio_size=8 959ret_bad_addr=false 960ret_data16=65535 961ret_data32=4294967295 962ret_data64=18446744073709551615 963ret_data8=255 964system=system 965update_data=false 966warn_access= 967pio=system.iobus.master[18] 968 969[system.tsunami.fake_pnp_write] 970type=IsaFake 971clock=1000 972fake_mem=false 973pio_addr=8804615850617 974pio_latency=100000 975pio_size=8 976ret_bad_addr=false 977ret_data16=65535 978ret_data32=4294967295 979ret_data64=18446744073709551615 980ret_data8=255 981system=system 982update_data=false 983warn_access= 984pio=system.iobus.master[10] 985 986[system.tsunami.fake_ppc] 987type=IsaFake 988clock=1000 989fake_mem=false 990pio_addr=8804615848891 991pio_latency=100000 992pio_size=8 993ret_bad_addr=false 994ret_data16=65535 995ret_data32=4294967295 996ret_data64=18446744073709551615 997ret_data8=255 998system=system 999update_data=false 1000warn_access= 1001pio=system.iobus.master[7] 1002 1003[system.tsunami.fake_sm_chip] 1004type=IsaFake 1005clock=1000 1006fake_mem=false 1007pio_addr=8804615848816 1008pio_latency=100000 1009pio_size=8 1010ret_bad_addr=false 1011ret_data16=65535 1012ret_data32=4294967295 1013ret_data64=18446744073709551615 1014ret_data8=255 1015system=system 1016update_data=false 1017warn_access= 1018pio=system.iobus.master[2] 1019 1020[system.tsunami.fake_uart1] 1021type=IsaFake 1022clock=1000 1023fake_mem=false 1024pio_addr=8804615848696 1025pio_latency=100000 1026pio_size=8 1027ret_bad_addr=false 1028ret_data16=65535 1029ret_data32=4294967295 1030ret_data64=18446744073709551615 1031ret_data8=255 1032system=system 1033update_data=false 1034warn_access= 1035pio=system.iobus.master[3] 1036 1037[system.tsunami.fake_uart2] 1038type=IsaFake 1039clock=1000 1040fake_mem=false 1041pio_addr=8804615848936 1042pio_latency=100000 1043pio_size=8 1044ret_bad_addr=false 1045ret_data16=65535 1046ret_data32=4294967295 1047ret_data64=18446744073709551615 1048ret_data8=255 1049system=system 1050update_data=false 1051warn_access= 1052pio=system.iobus.master[4] 1053 1054[system.tsunami.fake_uart3] 1055type=IsaFake 1056clock=1000 1057fake_mem=false 1058pio_addr=8804615848680 1059pio_latency=100000 1060pio_size=8 1061ret_bad_addr=false 1062ret_data16=65535 1063ret_data32=4294967295 1064ret_data64=18446744073709551615 1065ret_data8=255 1066system=system 1067update_data=false 1068warn_access= 1069pio=system.iobus.master[5] 1070 1071[system.tsunami.fake_uart4] 1072type=IsaFake 1073clock=1000 1074fake_mem=false 1075pio_addr=8804615848944 1076pio_latency=100000 1077pio_size=8 1078ret_bad_addr=false 1079ret_data16=65535 1080ret_data32=4294967295 1081ret_data64=18446744073709551615 1082ret_data8=255 1083system=system 1084update_data=false 1085warn_access= 1086pio=system.iobus.master[6] 1087 1088[system.tsunami.fb] 1089type=BadDevice 1090clock=1000 1091devicename=FrameBuffer 1092pio_addr=8804615848912 1093pio_latency=100000 1094system=system 1095pio=system.iobus.master[21] 1096 1097[system.tsunami.ide] 1098type=IdeController 1099BAR0=1 1100BAR0LegacyIO=false 1101BAR0Size=8 1102BAR1=1 1103BAR1LegacyIO=false 1104BAR1Size=4 1105BAR2=1 1106BAR2LegacyIO=false 1107BAR2Size=8 1108BAR3=1 1109BAR3LegacyIO=false 1110BAR3Size=4 1111BAR4=1 1112BAR4LegacyIO=false 1113BAR4Size=16 1114BAR5=1 1115BAR5LegacyIO=false 1116BAR5Size=0 1117BIST=0 1118CacheLineSize=0 1119CardbusCIS=0 1120ClassCode=1 1121Command=0 1122DeviceID=28945 1123ExpansionROM=0 1124HeaderType=0 1125InterruptLine=31 1126InterruptPin=1 1127LatencyTimer=0 1128MaximumLatency=0 1129MinimumGrant=0 1130ProgIF=133 1131Revision=0 1132Status=640 1133SubClassCode=1 1134SubsystemID=0 1135SubsystemVendorID=0 1136VendorID=32902 1137clock=1000 1138config_latency=20000 1139ctrl_offset=0 1140disks=system.disk0 system.disk2 1141io_shift=0 1142pci_bus=0 1143pci_dev=0 1144pci_func=0 1145pio_latency=30000 1146platform=system.tsunami 1147system=system 1148config=system.iobus.master[26] 1149dma=system.iobus.slave[1] 1150pio=system.iobus.master[25] 1151 1152[system.tsunami.io] 1153type=TsunamiIO 1154clock=1000 1155frequency=976562500 1156pio_addr=8804615847936 1157pio_latency=100000 1158system=system 1159time=Thu Jan 1 00:00:00 2009 1160tsunami=system.tsunami 1161year_is_bcd=false 1162pio=system.iobus.master[22] 1163 1164[system.tsunami.pchip] 1165type=TsunamiPChip 1166clock=1000 1167pio_addr=8802535473152 1168pio_latency=100000 1169system=system 1170tsunami=system.tsunami 1171pio=system.iobus.master[1] 1172 1173[system.tsunami.pciconfig] 1174type=PciConfigAll 1175bus=0 1176clock=1000 1177pio_latency=30000 1178platform=system.tsunami 1179size=16777216 1180system=system 1181pio=system.iobus.default 1182 1183[system.tsunami.uart] 1184type=Uart8250 1185clock=1000 1186pio_addr=8804615848952 1187pio_latency=100000 1188platform=system.tsunami 1189system=system 1190terminal=system.terminal 1191pio=system.iobus.master[23] 1192	718config_latency=20000 719dma_data_free=false 720dma_desc_free=false 721dma_no_allocate=true 722dma_read_delay=0 723dma_read_factor=0 724dma_write_delay=0 725dma_write_factor=0 726hardware_address=00:90:00:00:00:01 727intr_delay=10000000 728pci_bus=0 729pci_dev=1 730pci_func=0 731pio_latency=30000 732platform=system.tsunami 733rss=false 734rx_delay=1000000 735rx_fifo_size=524288 736rx_filter=true 737rx_thread=false 738system=system 739tx_delay=1000000 740tx_fifo_size=524288 741tx_thread=false 742config=system.iobus.master[28] 743dma=system.iobus.slave[2] 744pio=system.iobus.master[27] 745 746[system.tsunami.fake_OROM] 747type=IsaFake 748clock=1000 749fake_mem=false 750pio_addr=8796093677568 751pio_latency=100000 752pio_size=393216 753ret_bad_addr=false 754ret_data16=65535 755ret_data32=4294967295 756ret_data64=18446744073709551615 757ret_data8=255 758system=system 759update_data=false 760warn_access= 761pio=system.iobus.master[8] 762 763[system.tsunami.fake_ata0] 764type=IsaFake 765clock=1000 766fake_mem=false 767pio_addr=8804615848432 768pio_latency=100000 769pio_size=8 770ret_bad_addr=false 771ret_data16=65535 772ret_data32=4294967295 773ret_data64=18446744073709551615 774ret_data8=255 775system=system 776update_data=false 777warn_access= 778pio=system.iobus.master[19] 779 780[system.tsunami.fake_ata1] 781type=IsaFake 782clock=1000 783fake_mem=false 784pio_addr=8804615848304 785pio_latency=100000 786pio_size=8 787ret_bad_addr=false 788ret_data16=65535 789ret_data32=4294967295 790ret_data64=18446744073709551615 791ret_data8=255 792system=system 793update_data=false 794warn_access= 795pio=system.iobus.master[20] 796 797[system.tsunami.fake_pnp_addr] 798type=IsaFake 799clock=1000 800fake_mem=false 801pio_addr=8804615848569 802pio_latency=100000 803pio_size=8 804ret_bad_addr=false 805ret_data16=65535 806ret_data32=4294967295 807ret_data64=18446744073709551615 808ret_data8=255 809system=system 810update_data=false 811warn_access= 812pio=system.iobus.master[9] 813 814[system.tsunami.fake_pnp_read0] 815type=IsaFake 816clock=1000 817fake_mem=false 818pio_addr=8804615848451 819pio_latency=100000 820pio_size=8 821ret_bad_addr=false 822ret_data16=65535 823ret_data32=4294967295 824ret_data64=18446744073709551615 825ret_data8=255 826system=system 827update_data=false 828warn_access= 829pio=system.iobus.master[11] 830 831[system.tsunami.fake_pnp_read1] 832type=IsaFake 833clock=1000 834fake_mem=false 835pio_addr=8804615848515 836pio_latency=100000 837pio_size=8 838ret_bad_addr=false 839ret_data16=65535 840ret_data32=4294967295 841ret_data64=18446744073709551615 842ret_data8=255 843system=system 844update_data=false 845warn_access= 846pio=system.iobus.master[12] 847 848[system.tsunami.fake_pnp_read2] 849type=IsaFake 850clock=1000 851fake_mem=false 852pio_addr=8804615848579 853pio_latency=100000 854pio_size=8 855ret_bad_addr=false 856ret_data16=65535 857ret_data32=4294967295 858ret_data64=18446744073709551615 859ret_data8=255 860system=system 861update_data=false 862warn_access= 863pio=system.iobus.master[13] 864 865[system.tsunami.fake_pnp_read3] 866type=IsaFake 867clock=1000 868fake_mem=false 869pio_addr=8804615848643 870pio_latency=100000 871pio_size=8 872ret_bad_addr=false 873ret_data16=65535 874ret_data32=4294967295 875ret_data64=18446744073709551615 876ret_data8=255 877system=system 878update_data=false 879warn_access= 880pio=system.iobus.master[14] 881 882[system.tsunami.fake_pnp_read4] 883type=IsaFake 884clock=1000 885fake_mem=false 886pio_addr=8804615848707 887pio_latency=100000 888pio_size=8 889ret_bad_addr=false 890ret_data16=65535 891ret_data32=4294967295 892ret_data64=18446744073709551615 893ret_data8=255 894system=system 895update_data=false 896warn_access= 897pio=system.iobus.master[15] 898 899[system.tsunami.fake_pnp_read5] 900type=IsaFake 901clock=1000 902fake_mem=false 903pio_addr=8804615848771 904pio_latency=100000 905pio_size=8 906ret_bad_addr=false 907ret_data16=65535 908ret_data32=4294967295 909ret_data64=18446744073709551615 910ret_data8=255 911system=system 912update_data=false 913warn_access= 914pio=system.iobus.master[16] 915 916[system.tsunami.fake_pnp_read6] 917type=IsaFake 918clock=1000 919fake_mem=false 920pio_addr=8804615848835 921pio_latency=100000 922pio_size=8 923ret_bad_addr=false 924ret_data16=65535 925ret_data32=4294967295 926ret_data64=18446744073709551615 927ret_data8=255 928system=system 929update_data=false 930warn_access= 931pio=system.iobus.master[17] 932 933[system.tsunami.fake_pnp_read7] 934type=IsaFake 935clock=1000 936fake_mem=false 937pio_addr=8804615848899 938pio_latency=100000 939pio_size=8 940ret_bad_addr=false 941ret_data16=65535 942ret_data32=4294967295 943ret_data64=18446744073709551615 944ret_data8=255 945system=system 946update_data=false 947warn_access= 948pio=system.iobus.master[18] 949 950[system.tsunami.fake_pnp_write] 951type=IsaFake 952clock=1000 953fake_mem=false 954pio_addr=8804615850617 955pio_latency=100000 956pio_size=8 957ret_bad_addr=false 958ret_data16=65535 959ret_data32=4294967295 960ret_data64=18446744073709551615 961ret_data8=255 962system=system 963update_data=false 964warn_access= 965pio=system.iobus.master[10] 966 967[system.tsunami.fake_ppc] 968type=IsaFake 969clock=1000 970fake_mem=false 971pio_addr=8804615848891 972pio_latency=100000 973pio_size=8 974ret_bad_addr=false 975ret_data16=65535 976ret_data32=4294967295 977ret_data64=18446744073709551615 978ret_data8=255 979system=system 980update_data=false 981warn_access= 982pio=system.iobus.master[7] 983 984[system.tsunami.fake_sm_chip] 985type=IsaFake 986clock=1000 987fake_mem=false 988pio_addr=8804615848816 989pio_latency=100000 990pio_size=8 991ret_bad_addr=false 992ret_data16=65535 993ret_data32=4294967295 994ret_data64=18446744073709551615 995ret_data8=255 996system=system 997update_data=false 998warn_access= 999pio=system.iobus.master[2] 1000 1001[system.tsunami.fake_uart1] 1002type=IsaFake 1003clock=1000 1004fake_mem=false 1005pio_addr=8804615848696 1006pio_latency=100000 1007pio_size=8 1008ret_bad_addr=false 1009ret_data16=65535 1010ret_data32=4294967295 1011ret_data64=18446744073709551615 1012ret_data8=255 1013system=system 1014update_data=false 1015warn_access= 1016pio=system.iobus.master[3] 1017 1018[system.tsunami.fake_uart2] 1019type=IsaFake 1020clock=1000 1021fake_mem=false 1022pio_addr=8804615848936 1023pio_latency=100000 1024pio_size=8 1025ret_bad_addr=false 1026ret_data16=65535 1027ret_data32=4294967295 1028ret_data64=18446744073709551615 1029ret_data8=255 1030system=system 1031update_data=false 1032warn_access= 1033pio=system.iobus.master[4] 1034 1035[system.tsunami.fake_uart3] 1036type=IsaFake 1037clock=1000 1038fake_mem=false 1039pio_addr=8804615848680 1040pio_latency=100000 1041pio_size=8 1042ret_bad_addr=false 1043ret_data16=65535 1044ret_data32=4294967295 1045ret_data64=18446744073709551615 1046ret_data8=255 1047system=system 1048update_data=false 1049warn_access= 1050pio=system.iobus.master[5] 1051 1052[system.tsunami.fake_uart4] 1053type=IsaFake 1054clock=1000 1055fake_mem=false 1056pio_addr=8804615848944 1057pio_latency=100000 1058pio_size=8 1059ret_bad_addr=false 1060ret_data16=65535 1061ret_data32=4294967295 1062ret_data64=18446744073709551615 1063ret_data8=255 1064system=system 1065update_data=false 1066warn_access= 1067pio=system.iobus.master[6] 1068 1069[system.tsunami.fb] 1070type=BadDevice 1071clock=1000 1072devicename=FrameBuffer 1073pio_addr=8804615848912 1074pio_latency=100000 1075system=system 1076pio=system.iobus.master[21] 1077 1078[system.tsunami.ide] 1079type=IdeController 1080BAR0=1 1081BAR0LegacyIO=false 1082BAR0Size=8 1083BAR1=1 1084BAR1LegacyIO=false 1085BAR1Size=4 1086BAR2=1 1087BAR2LegacyIO=false 1088BAR2Size=8 1089BAR3=1 1090BAR3LegacyIO=false 1091BAR3Size=4 1092BAR4=1 1093BAR4LegacyIO=false 1094BAR4Size=16 1095BAR5=1 1096BAR5LegacyIO=false 1097BAR5Size=0 1098BIST=0 1099CacheLineSize=0 1100CardbusCIS=0 1101ClassCode=1 1102Command=0 1103DeviceID=28945 1104ExpansionROM=0 1105HeaderType=0 1106InterruptLine=31 1107InterruptPin=1 1108LatencyTimer=0 1109MaximumLatency=0 1110MinimumGrant=0 1111ProgIF=133 1112Revision=0 1113Status=640 1114SubClassCode=1 1115SubsystemID=0 1116SubsystemVendorID=0 1117VendorID=32902 1118clock=1000 1119config_latency=20000 1120ctrl_offset=0 1121disks=system.disk0 system.disk2 1122io_shift=0 1123pci_bus=0 1124pci_dev=0 1125pci_func=0 1126pio_latency=30000 1127platform=system.tsunami 1128system=system 1129config=system.iobus.master[26] 1130dma=system.iobus.slave[1] 1131pio=system.iobus.master[25] 1132 1133[system.tsunami.io] 1134type=TsunamiIO 1135clock=1000 1136frequency=976562500 1137pio_addr=8804615847936 1138pio_latency=100000 1139system=system 1140time=Thu Jan 1 00:00:00 2009 1141tsunami=system.tsunami 1142year_is_bcd=false 1143pio=system.iobus.master[22] 1144 1145[system.tsunami.pchip] 1146type=TsunamiPChip 1147clock=1000 1148pio_addr=8802535473152 1149pio_latency=100000 1150system=system 1151tsunami=system.tsunami 1152pio=system.iobus.master[1] 1153 1154[system.tsunami.pciconfig] 1155type=PciConfigAll 1156bus=0 1157clock=1000 1158pio_latency=30000 1159platform=system.tsunami 1160size=16777216 1161system=system 1162pio=system.iobus.default 1163 1164[system.tsunami.uart] 1165type=Uart8250 1166clock=1000 1167pio_addr=8804615848952 1168pio_latency=100000 1169platform=system.tsunami 1170system=system 1171terminal=system.terminal 1172pio=system.iobus.master[23] 1173