1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxAlphaSystem
| 1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxAlphaSystem
|
11children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
| 11children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami
|
12boot_cpu_frequency=500 13boot_osflags=root=/dev/hda1 console=ttyS0
| 12boot_cpu_frequency=500 13boot_osflags=root=/dev/hda1 console=ttyS0
|
14console=/dist/m5/system/binaries/console
| 14clock=1000 15console=/projects/pd/randd/dist/binaries/console
|
15init_param=0
| 16init_param=0
|
16kernel=/dist/m5/system/binaries/vmlinux
| 17kernel=/projects/pd/randd/dist/binaries/vmlinux
|
17load_addr_mask=1099511627775 18mem_mode=timing 19memories=system.physmem 20num_work_ids=16
| 18load_addr_mask=1099511627775 19mem_mode=timing 20memories=system.physmem 21num_work_ids=16
|
21pal=/dist/m5/system/binaries/ts_osfpal
| 22pal=/projects/pd/randd/dist/binaries/ts_osfpal
|
22readfile=tests/halt.sh 23symbolfile= 24system_rev=1024 25system_type=34 26work_begin_ckpt_count=0 27work_begin_cpu_id_exit=-1 28work_begin_exit_count=0 29work_cpus_ckpt_count=0 30work_end_ckpt_count=0 31work_end_exit_count=0 32work_item_id=-1 33system_port=system.membus.slave[0] 34 35[system.bridge] 36type=Bridge
| 23readfile=tests/halt.sh 24symbolfile= 25system_rev=1024 26system_type=34 27work_begin_ckpt_count=0 28work_begin_cpu_id_exit=-1 29work_begin_exit_count=0 30work_cpus_ckpt_count=0 31work_end_ckpt_count=0 32work_end_exit_count=0 33work_item_id=-1 34system_port=system.membus.slave[0] 35 36[system.bridge] 37type=Bridge
|
| 38clock=1000
|
37delay=50000
| 39delay=50000
|
38nack_delay=4000
| |
39ranges=8796093022208:18446744073709551615 40req_size=16 41resp_size=16
| 40ranges=8796093022208:18446744073709551615 41req_size=16 42resp_size=16
|
42write_ack=false
| |
43master=system.iobus.slave[0] 44slave=system.membus.master[0] 45 46[system.cpu] 47type=DerivO3CPU
| 43master=system.iobus.slave[0] 44slave=system.membus.master[0] 45 46[system.cpu] 47type=DerivO3CPU
|
48children=dcache dtb fuPool icache interrupts itb tracer
| 48children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
|
49BTBEntries=4096 50BTBTagSize=16 51LFSTSize=1024 52LQEntries=32 53LSQCheckLoads=true 54LSQDepCheckShift=4 55RASSize=16 56SQEntries=32 57SSITSize=1024 58activity=0 59backComSize=5 60cachePorts=200 61checker=Null 62choiceCtrBits=2 63choicePredictorSize=8192 64clock=500 65commitToDecodeDelay=1 66commitToFetchDelay=1 67commitToIEWDelay=1 68commitToRenameDelay=1 69commitWidth=8 70cpu_id=0 71decodeToFetchDelay=1 72decodeToRenameDelay=1 73decodeWidth=8 74defer_registration=false 75dispatchWidth=8 76do_checkpoint_insts=true 77do_quiesce=true 78do_statistics_insts=true 79dtb=system.cpu.dtb 80fetchToDecodeDelay=1 81fetchTrapLatency=1 82fetchWidth=8 83forwardComSize=5 84fuPool=system.cpu.fuPool 85function_trace=false 86function_trace_start=0 87globalCtrBits=2 88globalHistoryBits=13 89globalPredictorSize=8192 90iewToCommitDelay=1 91iewToDecodeDelay=1 92iewToFetchDelay=1 93iewToRenameDelay=1 94instShiftAmt=2 95interrupts=system.cpu.interrupts
| 49BTBEntries=4096 50BTBTagSize=16 51LFSTSize=1024 52LQEntries=32 53LSQCheckLoads=true 54LSQDepCheckShift=4 55RASSize=16 56SQEntries=32 57SSITSize=1024 58activity=0 59backComSize=5 60cachePorts=200 61checker=Null 62choiceCtrBits=2 63choicePredictorSize=8192 64clock=500 65commitToDecodeDelay=1 66commitToFetchDelay=1 67commitToIEWDelay=1 68commitToRenameDelay=1 69commitWidth=8 70cpu_id=0 71decodeToFetchDelay=1 72decodeToRenameDelay=1 73decodeWidth=8 74defer_registration=false 75dispatchWidth=8 76do_checkpoint_insts=true 77do_quiesce=true 78do_statistics_insts=true 79dtb=system.cpu.dtb 80fetchToDecodeDelay=1 81fetchTrapLatency=1 82fetchWidth=8 83forwardComSize=5 84fuPool=system.cpu.fuPool 85function_trace=false 86function_trace_start=0 87globalCtrBits=2 88globalHistoryBits=13 89globalPredictorSize=8192 90iewToCommitDelay=1 91iewToDecodeDelay=1 92iewToFetchDelay=1 93iewToRenameDelay=1 94instShiftAmt=2 95interrupts=system.cpu.interrupts
|
| 96isa=system.cpu.isa
|
96issueToExecuteDelay=1 97issueWidth=8 98itb=system.cpu.itb 99localCtrBits=2 100localHistoryBits=11 101localHistoryTableSize=2048 102localPredictorSize=2048 103max_insts_all_threads=0 104max_insts_any_thread=0 105max_loads_all_threads=0 106max_loads_any_thread=0 107needsTSO=false 108numIQEntries=64 109numPhysFloatRegs=256 110numPhysIntRegs=256 111numROBEntries=192 112numRobs=1 113numThreads=1
| 97issueToExecuteDelay=1 98issueWidth=8 99itb=system.cpu.itb 100localCtrBits=2 101localHistoryBits=11 102localHistoryTableSize=2048 103localPredictorSize=2048 104max_insts_all_threads=0 105max_insts_any_thread=0 106max_loads_all_threads=0 107max_loads_any_thread=0 108needsTSO=false 109numIQEntries=64 110numPhysFloatRegs=256 111numPhysIntRegs=256 112numROBEntries=192 113numRobs=1 114numThreads=1
|
114phase=0
| |
115predType=tournament 116profile=0 117progress_interval=0 118renameToDecodeDelay=1 119renameToFetchDelay=1 120renameToIEWDelay=2 121renameToROBDelay=1 122renameWidth=8 123smtCommitPolicy=RoundRobin 124smtFetchPolicy=SingleThread 125smtIQPolicy=Partitioned 126smtIQThreshold=100 127smtLSQPolicy=Partitioned 128smtLSQThreshold=100 129smtNumFetchingThreads=1 130smtROBPolicy=Partitioned 131smtROBThreshold=100 132squashWidth=8 133store_set_clear_period=250000 134system=system 135tracer=system.cpu.tracer 136trapLatency=13 137wbDepth=1 138wbWidth=8 139workload= 140dcache_port=system.cpu.dcache.cpu_side 141icache_port=system.cpu.icache.cpu_side 142 143[system.cpu.dcache] 144type=BaseCache 145addr_ranges=0:18446744073709551615 146assoc=4 147block_size=64
| 115predType=tournament 116profile=0 117progress_interval=0 118renameToDecodeDelay=1 119renameToFetchDelay=1 120renameToIEWDelay=2 121renameToROBDelay=1 122renameWidth=8 123smtCommitPolicy=RoundRobin 124smtFetchPolicy=SingleThread 125smtIQPolicy=Partitioned 126smtIQThreshold=100 127smtLSQPolicy=Partitioned 128smtLSQThreshold=100 129smtNumFetchingThreads=1 130smtROBPolicy=Partitioned 131smtROBThreshold=100 132squashWidth=8 133store_set_clear_period=250000 134system=system 135tracer=system.cpu.tracer 136trapLatency=13 137wbDepth=1 138wbWidth=8 139workload= 140dcache_port=system.cpu.dcache.cpu_side 141icache_port=system.cpu.icache.cpu_side 142 143[system.cpu.dcache] 144type=BaseCache 145addr_ranges=0:18446744073709551615 146assoc=4 147block_size=64
|
| 148clock=500
|
148forward_snoops=true 149hash_delay=1
| 149forward_snoops=true 150hash_delay=1
|
| 151hit_latency=2
|
150is_top_level=true
| 152is_top_level=true
|
151latency=1000
| |
152max_miss_count=0 153mshrs=4 154prefetch_on_access=false 155prefetcher=Null 156prioritizeRequests=false 157repl=Null
| 153max_miss_count=0 154mshrs=4 155prefetch_on_access=false 156prefetcher=Null 157prioritizeRequests=false 158repl=Null
|
| 159response_latency=2
|
158size=32768 159subblock_size=0 160system=system 161tgts_per_mshr=20 162trace_addr=0 163two_queue=false 164write_buffers=8 165cpu_side=system.cpu.dcache_port
| 160size=32768 161subblock_size=0 162system=system 163tgts_per_mshr=20 164trace_addr=0 165two_queue=false 166write_buffers=8 167cpu_side=system.cpu.dcache_port
|
166mem_side=system.toL2Bus.slave[1]
| 168mem_side=system.cpu.toL2Bus.slave[1]
|
167 168[system.cpu.dtb] 169type=AlphaTLB 170size=64 171 172[system.cpu.fuPool] 173type=FUPool 174children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 175FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 176 177[system.cpu.fuPool.FUList0] 178type=FUDesc 179children=opList 180count=6 181opList=system.cpu.fuPool.FUList0.opList 182 183[system.cpu.fuPool.FUList0.opList] 184type=OpDesc 185issueLat=1 186opClass=IntAlu 187opLat=1 188 189[system.cpu.fuPool.FUList1] 190type=FUDesc 191children=opList0 opList1 192count=2 193opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 194 195[system.cpu.fuPool.FUList1.opList0] 196type=OpDesc 197issueLat=1 198opClass=IntMult 199opLat=3 200 201[system.cpu.fuPool.FUList1.opList1] 202type=OpDesc 203issueLat=19 204opClass=IntDiv 205opLat=20 206 207[system.cpu.fuPool.FUList2] 208type=FUDesc 209children=opList0 opList1 opList2 210count=4 211opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 212 213[system.cpu.fuPool.FUList2.opList0] 214type=OpDesc 215issueLat=1 216opClass=FloatAdd 217opLat=2 218 219[system.cpu.fuPool.FUList2.opList1] 220type=OpDesc 221issueLat=1 222opClass=FloatCmp 223opLat=2 224 225[system.cpu.fuPool.FUList2.opList2] 226type=OpDesc 227issueLat=1 228opClass=FloatCvt 229opLat=2 230 231[system.cpu.fuPool.FUList3] 232type=FUDesc 233children=opList0 opList1 opList2 234count=2 235opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 236 237[system.cpu.fuPool.FUList3.opList0] 238type=OpDesc 239issueLat=1 240opClass=FloatMult 241opLat=4 242 243[system.cpu.fuPool.FUList3.opList1] 244type=OpDesc 245issueLat=12 246opClass=FloatDiv 247opLat=12 248 249[system.cpu.fuPool.FUList3.opList2] 250type=OpDesc 251issueLat=24 252opClass=FloatSqrt 253opLat=24 254 255[system.cpu.fuPool.FUList4] 256type=FUDesc 257children=opList 258count=0 259opList=system.cpu.fuPool.FUList4.opList 260 261[system.cpu.fuPool.FUList4.opList] 262type=OpDesc 263issueLat=1 264opClass=MemRead 265opLat=1 266 267[system.cpu.fuPool.FUList5] 268type=FUDesc 269children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 270count=4 271opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 272 273[system.cpu.fuPool.FUList5.opList00] 274type=OpDesc 275issueLat=1 276opClass=SimdAdd 277opLat=1 278 279[system.cpu.fuPool.FUList5.opList01] 280type=OpDesc 281issueLat=1 282opClass=SimdAddAcc 283opLat=1 284 285[system.cpu.fuPool.FUList5.opList02] 286type=OpDesc 287issueLat=1 288opClass=SimdAlu 289opLat=1 290 291[system.cpu.fuPool.FUList5.opList03] 292type=OpDesc 293issueLat=1 294opClass=SimdCmp 295opLat=1 296 297[system.cpu.fuPool.FUList5.opList04] 298type=OpDesc 299issueLat=1 300opClass=SimdCvt 301opLat=1 302 303[system.cpu.fuPool.FUList5.opList05] 304type=OpDesc 305issueLat=1 306opClass=SimdMisc 307opLat=1 308 309[system.cpu.fuPool.FUList5.opList06] 310type=OpDesc 311issueLat=1 312opClass=SimdMult 313opLat=1 314 315[system.cpu.fuPool.FUList5.opList07] 316type=OpDesc 317issueLat=1 318opClass=SimdMultAcc 319opLat=1 320 321[system.cpu.fuPool.FUList5.opList08] 322type=OpDesc 323issueLat=1 324opClass=SimdShift 325opLat=1 326 327[system.cpu.fuPool.FUList5.opList09] 328type=OpDesc 329issueLat=1 330opClass=SimdShiftAcc 331opLat=1 332 333[system.cpu.fuPool.FUList5.opList10] 334type=OpDesc 335issueLat=1 336opClass=SimdSqrt 337opLat=1 338 339[system.cpu.fuPool.FUList5.opList11] 340type=OpDesc 341issueLat=1 342opClass=SimdFloatAdd 343opLat=1 344 345[system.cpu.fuPool.FUList5.opList12] 346type=OpDesc 347issueLat=1 348opClass=SimdFloatAlu 349opLat=1 350 351[system.cpu.fuPool.FUList5.opList13] 352type=OpDesc 353issueLat=1 354opClass=SimdFloatCmp 355opLat=1 356 357[system.cpu.fuPool.FUList5.opList14] 358type=OpDesc 359issueLat=1 360opClass=SimdFloatCvt 361opLat=1 362 363[system.cpu.fuPool.FUList5.opList15] 364type=OpDesc 365issueLat=1 366opClass=SimdFloatDiv 367opLat=1 368 369[system.cpu.fuPool.FUList5.opList16] 370type=OpDesc 371issueLat=1 372opClass=SimdFloatMisc 373opLat=1 374 375[system.cpu.fuPool.FUList5.opList17] 376type=OpDesc 377issueLat=1 378opClass=SimdFloatMult 379opLat=1 380 381[system.cpu.fuPool.FUList5.opList18] 382type=OpDesc 383issueLat=1 384opClass=SimdFloatMultAcc 385opLat=1 386 387[system.cpu.fuPool.FUList5.opList19] 388type=OpDesc 389issueLat=1 390opClass=SimdFloatSqrt 391opLat=1 392 393[system.cpu.fuPool.FUList6] 394type=FUDesc 395children=opList 396count=0 397opList=system.cpu.fuPool.FUList6.opList 398 399[system.cpu.fuPool.FUList6.opList] 400type=OpDesc 401issueLat=1 402opClass=MemWrite 403opLat=1 404 405[system.cpu.fuPool.FUList7] 406type=FUDesc 407children=opList0 opList1 408count=4 409opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 410 411[system.cpu.fuPool.FUList7.opList0] 412type=OpDesc 413issueLat=1 414opClass=MemRead 415opLat=1 416 417[system.cpu.fuPool.FUList7.opList1] 418type=OpDesc 419issueLat=1 420opClass=MemWrite 421opLat=1 422 423[system.cpu.fuPool.FUList8] 424type=FUDesc 425children=opList 426count=1 427opList=system.cpu.fuPool.FUList8.opList 428 429[system.cpu.fuPool.FUList8.opList] 430type=OpDesc 431issueLat=3 432opClass=IprAccess 433opLat=3 434 435[system.cpu.icache] 436type=BaseCache 437addr_ranges=0:18446744073709551615 438assoc=1 439block_size=64
| 169 170[system.cpu.dtb] 171type=AlphaTLB 172size=64 173 174[system.cpu.fuPool] 175type=FUPool 176children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 177FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 178 179[system.cpu.fuPool.FUList0] 180type=FUDesc 181children=opList 182count=6 183opList=system.cpu.fuPool.FUList0.opList 184 185[system.cpu.fuPool.FUList0.opList] 186type=OpDesc 187issueLat=1 188opClass=IntAlu 189opLat=1 190 191[system.cpu.fuPool.FUList1] 192type=FUDesc 193children=opList0 opList1 194count=2 195opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 196 197[system.cpu.fuPool.FUList1.opList0] 198type=OpDesc 199issueLat=1 200opClass=IntMult 201opLat=3 202 203[system.cpu.fuPool.FUList1.opList1] 204type=OpDesc 205issueLat=19 206opClass=IntDiv 207opLat=20 208 209[system.cpu.fuPool.FUList2] 210type=FUDesc 211children=opList0 opList1 opList2 212count=4 213opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 214 215[system.cpu.fuPool.FUList2.opList0] 216type=OpDesc 217issueLat=1 218opClass=FloatAdd 219opLat=2 220 221[system.cpu.fuPool.FUList2.opList1] 222type=OpDesc 223issueLat=1 224opClass=FloatCmp 225opLat=2 226 227[system.cpu.fuPool.FUList2.opList2] 228type=OpDesc 229issueLat=1 230opClass=FloatCvt 231opLat=2 232 233[system.cpu.fuPool.FUList3] 234type=FUDesc 235children=opList0 opList1 opList2 236count=2 237opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 238 239[system.cpu.fuPool.FUList3.opList0] 240type=OpDesc 241issueLat=1 242opClass=FloatMult 243opLat=4 244 245[system.cpu.fuPool.FUList3.opList1] 246type=OpDesc 247issueLat=12 248opClass=FloatDiv 249opLat=12 250 251[system.cpu.fuPool.FUList3.opList2] 252type=OpDesc 253issueLat=24 254opClass=FloatSqrt 255opLat=24 256 257[system.cpu.fuPool.FUList4] 258type=FUDesc 259children=opList 260count=0 261opList=system.cpu.fuPool.FUList4.opList 262 263[system.cpu.fuPool.FUList4.opList] 264type=OpDesc 265issueLat=1 266opClass=MemRead 267opLat=1 268 269[system.cpu.fuPool.FUList5] 270type=FUDesc 271children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 272count=4 273opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 274 275[system.cpu.fuPool.FUList5.opList00] 276type=OpDesc 277issueLat=1 278opClass=SimdAdd 279opLat=1 280 281[system.cpu.fuPool.FUList5.opList01] 282type=OpDesc 283issueLat=1 284opClass=SimdAddAcc 285opLat=1 286 287[system.cpu.fuPool.FUList5.opList02] 288type=OpDesc 289issueLat=1 290opClass=SimdAlu 291opLat=1 292 293[system.cpu.fuPool.FUList5.opList03] 294type=OpDesc 295issueLat=1 296opClass=SimdCmp 297opLat=1 298 299[system.cpu.fuPool.FUList5.opList04] 300type=OpDesc 301issueLat=1 302opClass=SimdCvt 303opLat=1 304 305[system.cpu.fuPool.FUList5.opList05] 306type=OpDesc 307issueLat=1 308opClass=SimdMisc 309opLat=1 310 311[system.cpu.fuPool.FUList5.opList06] 312type=OpDesc 313issueLat=1 314opClass=SimdMult 315opLat=1 316 317[system.cpu.fuPool.FUList5.opList07] 318type=OpDesc 319issueLat=1 320opClass=SimdMultAcc 321opLat=1 322 323[system.cpu.fuPool.FUList5.opList08] 324type=OpDesc 325issueLat=1 326opClass=SimdShift 327opLat=1 328 329[system.cpu.fuPool.FUList5.opList09] 330type=OpDesc 331issueLat=1 332opClass=SimdShiftAcc 333opLat=1 334 335[system.cpu.fuPool.FUList5.opList10] 336type=OpDesc 337issueLat=1 338opClass=SimdSqrt 339opLat=1 340 341[system.cpu.fuPool.FUList5.opList11] 342type=OpDesc 343issueLat=1 344opClass=SimdFloatAdd 345opLat=1 346 347[system.cpu.fuPool.FUList5.opList12] 348type=OpDesc 349issueLat=1 350opClass=SimdFloatAlu 351opLat=1 352 353[system.cpu.fuPool.FUList5.opList13] 354type=OpDesc 355issueLat=1 356opClass=SimdFloatCmp 357opLat=1 358 359[system.cpu.fuPool.FUList5.opList14] 360type=OpDesc 361issueLat=1 362opClass=SimdFloatCvt 363opLat=1 364 365[system.cpu.fuPool.FUList5.opList15] 366type=OpDesc 367issueLat=1 368opClass=SimdFloatDiv 369opLat=1 370 371[system.cpu.fuPool.FUList5.opList16] 372type=OpDesc 373issueLat=1 374opClass=SimdFloatMisc 375opLat=1 376 377[system.cpu.fuPool.FUList5.opList17] 378type=OpDesc 379issueLat=1 380opClass=SimdFloatMult 381opLat=1 382 383[system.cpu.fuPool.FUList5.opList18] 384type=OpDesc 385issueLat=1 386opClass=SimdFloatMultAcc 387opLat=1 388 389[system.cpu.fuPool.FUList5.opList19] 390type=OpDesc 391issueLat=1 392opClass=SimdFloatSqrt 393opLat=1 394 395[system.cpu.fuPool.FUList6] 396type=FUDesc 397children=opList 398count=0 399opList=system.cpu.fuPool.FUList6.opList 400 401[system.cpu.fuPool.FUList6.opList] 402type=OpDesc 403issueLat=1 404opClass=MemWrite 405opLat=1 406 407[system.cpu.fuPool.FUList7] 408type=FUDesc 409children=opList0 opList1 410count=4 411opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 412 413[system.cpu.fuPool.FUList7.opList0] 414type=OpDesc 415issueLat=1 416opClass=MemRead 417opLat=1 418 419[system.cpu.fuPool.FUList7.opList1] 420type=OpDesc 421issueLat=1 422opClass=MemWrite 423opLat=1 424 425[system.cpu.fuPool.FUList8] 426type=FUDesc 427children=opList 428count=1 429opList=system.cpu.fuPool.FUList8.opList 430 431[system.cpu.fuPool.FUList8.opList] 432type=OpDesc 433issueLat=3 434opClass=IprAccess 435opLat=3 436 437[system.cpu.icache] 438type=BaseCache 439addr_ranges=0:18446744073709551615 440assoc=1 441block_size=64
|
| 442clock=500
|
440forward_snoops=true 441hash_delay=1
| 443forward_snoops=true 444hash_delay=1
|
| 445hit_latency=2
|
442is_top_level=true
| 446is_top_level=true
|
443latency=1000
| |
444max_miss_count=0 445mshrs=4 446prefetch_on_access=false 447prefetcher=Null 448prioritizeRequests=false 449repl=Null
| 447max_miss_count=0 448mshrs=4 449prefetch_on_access=false 450prefetcher=Null 451prioritizeRequests=false 452repl=Null
|
| 453response_latency=2
|
450size=32768 451subblock_size=0 452system=system 453tgts_per_mshr=20 454trace_addr=0 455two_queue=false 456write_buffers=8 457cpu_side=system.cpu.icache_port
| 454size=32768 455subblock_size=0 456system=system 457tgts_per_mshr=20 458trace_addr=0 459two_queue=false 460write_buffers=8 461cpu_side=system.cpu.icache_port
|
458mem_side=system.toL2Bus.slave[0]
| 462mem_side=system.cpu.toL2Bus.slave[0]
|
459 460[system.cpu.interrupts] 461type=AlphaInterrupts 462
| 463 464[system.cpu.interrupts] 465type=AlphaInterrupts 466
|
| 467[system.cpu.isa] 468type=AlphaISA 469
|
463[system.cpu.itb] 464type=AlphaTLB 465size=48 466
| 470[system.cpu.itb] 471type=AlphaTLB 472size=48 473
|
| 474[system.cpu.l2cache] 475type=BaseCache 476addr_ranges=0:18446744073709551615 477assoc=8 478block_size=64 479clock=500 480forward_snoops=true 481hash_delay=1 482hit_latency=20 483is_top_level=false 484max_miss_count=0 485mshrs=20 486prefetch_on_access=false 487prefetcher=Null 488prioritizeRequests=false 489repl=Null 490response_latency=20 491size=4194304 492subblock_size=0 493system=system 494tgts_per_mshr=12 495trace_addr=0 496two_queue=false 497write_buffers=8 498cpu_side=system.cpu.toL2Bus.master[0] 499mem_side=system.membus.slave[2] 500 501[system.cpu.toL2Bus] 502type=CoherentBus 503block_size=64 504clock=500 505header_cycles=1 506use_default_range=false 507width=32 508master=system.cpu.l2cache.cpu_side 509slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 510
|
467[system.cpu.tracer] 468type=ExeTracer 469 470[system.disk0] 471type=IdeDisk 472children=image 473delay=1000000 474driveID=master 475image=system.disk0.image 476 477[system.disk0.image] 478type=CowDiskImage 479children=child 480child=system.disk0.image.child 481image_file= 482read_only=false 483table_size=65536 484 485[system.disk0.image.child] 486type=RawDiskImage
| 511[system.cpu.tracer] 512type=ExeTracer 513 514[system.disk0] 515type=IdeDisk 516children=image 517delay=1000000 518driveID=master 519image=system.disk0.image 520 521[system.disk0.image] 522type=CowDiskImage 523children=child 524child=system.disk0.image.child 525image_file= 526read_only=false 527table_size=65536 528 529[system.disk0.image.child] 530type=RawDiskImage
|
487image_file=/dist/m5/system/disks/linux-latest.img
| 531image_file=/projects/pd/randd/dist/disks/linux-latest.img
|
488read_only=true 489 490[system.disk2] 491type=IdeDisk 492children=image 493delay=1000000 494driveID=master 495image=system.disk2.image 496 497[system.disk2.image] 498type=CowDiskImage 499children=child 500child=system.disk2.image.child 501image_file= 502read_only=false 503table_size=65536 504 505[system.disk2.image.child] 506type=RawDiskImage
| 532read_only=true 533 534[system.disk2] 535type=IdeDisk 536children=image 537delay=1000000 538driveID=master 539image=system.disk2.image 540 541[system.disk2.image] 542type=CowDiskImage 543children=child 544child=system.disk2.image.child 545image_file= 546read_only=false 547table_size=65536 548 549[system.disk2.image.child] 550type=RawDiskImage
|
507image_file=/dist/m5/system/disks/linux-bigswap2.img
| 551image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
|
508read_only=true 509 510[system.intrctrl] 511type=IntrControl 512sys=system 513 514[system.iobus] 515type=NoncoherentBus 516block_size=64 517clock=1000 518header_cycles=1 519use_default_range=true 520width=8 521default=system.tsunami.pciconfig.pio 522master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 523slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 524 525[system.iocache] 526type=BaseCache 527addr_ranges=0:8589934591 528assoc=8 529block_size=64
| 552read_only=true 553 554[system.intrctrl] 555type=IntrControl 556sys=system 557 558[system.iobus] 559type=NoncoherentBus 560block_size=64 561clock=1000 562header_cycles=1 563use_default_range=true 564width=8 565default=system.tsunami.pciconfig.pio 566master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 567slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 568 569[system.iocache] 570type=BaseCache 571addr_ranges=0:8589934591 572assoc=8 573block_size=64
|
| 574clock=1000
|
530forward_snoops=false 531hash_delay=1
| 575forward_snoops=false 576hash_delay=1
|
| 577hit_latency=50
|
532is_top_level=true
| 578is_top_level=true
|
533latency=50000
| |
534max_miss_count=0 535mshrs=20 536prefetch_on_access=false 537prefetcher=Null 538prioritizeRequests=false 539repl=Null
| 579max_miss_count=0 580mshrs=20 581prefetch_on_access=false 582prefetcher=Null 583prioritizeRequests=false 584repl=Null
|
| 585response_latency=50
|
540size=1024 541subblock_size=0 542system=system 543tgts_per_mshr=12 544trace_addr=0 545two_queue=false 546write_buffers=8 547cpu_side=system.iobus.master[29] 548mem_side=system.membus.slave[1] 549
| 586size=1024 587subblock_size=0 588system=system 589tgts_per_mshr=12 590trace_addr=0 591two_queue=false 592write_buffers=8 593cpu_side=system.iobus.master[29] 594mem_side=system.membus.slave[1] 595
|
550[system.l2c] 551type=BaseCache 552addr_ranges=0:18446744073709551615 553assoc=8 554block_size=64 555forward_snoops=true 556hash_delay=1 557is_top_level=false 558latency=10000 559max_miss_count=0 560mshrs=92 561prefetch_on_access=false 562prefetcher=Null 563prioritizeRequests=false 564repl=Null 565size=4194304 566subblock_size=0 567system=system 568tgts_per_mshr=16 569trace_addr=0 570two_queue=false 571write_buffers=8 572cpu_side=system.toL2Bus.master[0] 573mem_side=system.membus.slave[2] 574
| |
575[system.membus] 576type=CoherentBus 577children=badaddr_responder 578block_size=64 579clock=1000 580header_cycles=1 581use_default_range=false 582width=8 583default=system.membus.badaddr_responder.pio 584master=system.bridge.slave system.physmem.port
| 596[system.membus] 597type=CoherentBus 598children=badaddr_responder 599block_size=64 600clock=1000 601header_cycles=1 602use_default_range=false 603width=8 604default=system.membus.badaddr_responder.pio 605master=system.bridge.slave system.physmem.port
|
585slave=system.system_port system.iocache.mem_side system.l2c.mem_side
| 606slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side
|
586 587[system.membus.badaddr_responder] 588type=IsaFake
| 607 608[system.membus.badaddr_responder] 609type=IsaFake
|
| 610clock=1000
|
589fake_mem=false 590pio_addr=0
| 611fake_mem=false 612pio_addr=0
|
591pio_latency=1000
| 613pio_latency=100000
|
592pio_size=8 593ret_bad_addr=true 594ret_data16=65535 595ret_data32=4294967295 596ret_data64=18446744073709551615 597ret_data8=255 598system=system 599update_data=false 600warn_access= 601pio=system.membus.default 602 603[system.physmem]
| 614pio_size=8 615ret_bad_addr=true 616ret_data16=65535 617ret_data32=4294967295 618ret_data64=18446744073709551615 619ret_data8=255 620system=system 621update_data=false 622warn_access= 623pio=system.membus.default 624 625[system.physmem]
|
604type=SimpleMemory
| 626type=SimpleDRAM 627addr_mapping=openmap 628banks_per_rank=8 629clock=1000
|
605conf_table_reported=false
| 630conf_table_reported=false
|
606file=
| |
607in_addr_map=true
| 631in_addr_map=true
|
608latency=30000 609latency_var=0
| 632lines_per_rowbuffer=64 633mem_sched_policy=fcfs
|
610null=false
| 634null=false
|
| 635page_policy=open
|
611range=0:134217727
| 636range=0:134217727
|
| 637ranks_per_channel=2 638read_buffer_size=32 639tBURST=4000 640tCL=14000 641tRCD=14000 642tREFI=7800000 643tRFC=300000 644tRP=14000 645tWTR=1000 646write_buffer_size=32 647write_thresh_perc=70
|
612zero=false 613port=system.membus.master[1] 614 615[system.simple_disk] 616type=SimpleDisk 617children=disk 618disk=system.simple_disk.disk 619system=system 620 621[system.simple_disk.disk] 622type=RawDiskImage
| 648zero=false 649port=system.membus.master[1] 650 651[system.simple_disk] 652type=SimpleDisk 653children=disk 654disk=system.simple_disk.disk 655system=system 656 657[system.simple_disk.disk] 658type=RawDiskImage
|
623image_file=/dist/m5/system/disks/linux-latest.img
| 659image_file=/projects/pd/randd/dist/disks/linux-latest.img
|
624read_only=true 625 626[system.terminal] 627type=Terminal 628intr_control=system.intrctrl 629number=0 630output=true 631port=3456 632
| 660read_only=true 661 662[system.terminal] 663type=Terminal 664intr_control=system.intrctrl 665number=0 666output=true 667port=3456 668
|
633[system.toL2Bus] 634type=CoherentBus 635block_size=64 636clock=1000 637header_cycles=1 638use_default_range=false 639width=8 640master=system.l2c.cpu_side 641slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 642
| |
643[system.tsunami] 644type=Tsunami 645children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart 646intrctrl=system.intrctrl 647system=system 648 649[system.tsunami.backdoor] 650type=AlphaBackdoor
| 669[system.tsunami] 670type=Tsunami 671children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart 672intrctrl=system.intrctrl 673system=system 674 675[system.tsunami.backdoor] 676type=AlphaBackdoor
|
| 677clock=1000
|
651cpu=system.cpu 652disk=system.simple_disk 653pio_addr=8804682956800
| 678cpu=system.cpu 679disk=system.simple_disk 680pio_addr=8804682956800
|
654pio_latency=1000
| 681pio_latency=100000
|
655platform=system.tsunami 656system=system 657terminal=system.terminal 658pio=system.iobus.master[24] 659 660[system.tsunami.cchip] 661type=TsunamiCChip
| 682platform=system.tsunami 683system=system 684terminal=system.terminal 685pio=system.iobus.master[24] 686 687[system.tsunami.cchip] 688type=TsunamiCChip
|
| 689clock=1000
|
662pio_addr=8803072344064
| 690pio_addr=8803072344064
|
663pio_latency=1000
| 691pio_latency=100000
|
664system=system 665tsunami=system.tsunami 666pio=system.iobus.master[0] 667 668[system.tsunami.ethernet] 669type=NSGigE 670BAR0=1 671BAR0LegacyIO=false 672BAR0Size=256 673BAR1=0 674BAR1LegacyIO=false 675BAR1Size=4096 676BAR2=0 677BAR2LegacyIO=false 678BAR2Size=0 679BAR3=0 680BAR3LegacyIO=false 681BAR3Size=0 682BAR4=0 683BAR4LegacyIO=false 684BAR4Size=0 685BAR5=0 686BAR5LegacyIO=false 687BAR5Size=0 688BIST=0 689CacheLineSize=0 690CardbusCIS=0 691ClassCode=2 692Command=0 693DeviceID=34 694ExpansionROM=0 695HeaderType=0 696InterruptLine=30 697InterruptPin=1 698LatencyTimer=0 699MaximumLatency=52 700MinimumGrant=176 701ProgIF=0 702Revision=0 703Status=656 704SubClassCode=0 705SubsystemID=0 706SubsystemVendorID=0 707VendorID=4107 708clock=0 709config_latency=20000 710dma_data_free=false 711dma_desc_free=false 712dma_no_allocate=true 713dma_read_delay=0 714dma_read_factor=0 715dma_write_delay=0 716dma_write_factor=0 717hardware_address=00:90:00:00:00:01 718intr_delay=10000000
| 692system=system 693tsunami=system.tsunami 694pio=system.iobus.master[0] 695 696[system.tsunami.ethernet] 697type=NSGigE 698BAR0=1 699BAR0LegacyIO=false 700BAR0Size=256 701BAR1=0 702BAR1LegacyIO=false 703BAR1Size=4096 704BAR2=0 705BAR2LegacyIO=false 706BAR2Size=0 707BAR3=0 708BAR3LegacyIO=false 709BAR3Size=0 710BAR4=0 711BAR4LegacyIO=false 712BAR4Size=0 713BAR5=0 714BAR5LegacyIO=false 715BAR5Size=0 716BIST=0 717CacheLineSize=0 718CardbusCIS=0 719ClassCode=2 720Command=0 721DeviceID=34 722ExpansionROM=0 723HeaderType=0 724InterruptLine=30 725InterruptPin=1 726LatencyTimer=0 727MaximumLatency=52 728MinimumGrant=176 729ProgIF=0 730Revision=0 731Status=656 732SubClassCode=0 733SubsystemID=0 734SubsystemVendorID=0 735VendorID=4107 736clock=0 737config_latency=20000 738dma_data_free=false 739dma_desc_free=false 740dma_no_allocate=true 741dma_read_delay=0 742dma_read_factor=0 743dma_write_delay=0 744dma_write_factor=0 745hardware_address=00:90:00:00:00:01 746intr_delay=10000000
|
719max_backoff_delay=10000000 720min_backoff_delay=4000
| |
721pci_bus=0 722pci_dev=1 723pci_func=0
| 747pci_bus=0 748pci_dev=1 749pci_func=0
|
724pio_latency=1000
| 750pio_latency=30000
|
725platform=system.tsunami 726rss=false 727rx_delay=1000000 728rx_fifo_size=524288 729rx_filter=true 730rx_thread=false 731system=system 732tx_delay=1000000 733tx_fifo_size=524288 734tx_thread=false 735config=system.iobus.master[28] 736dma=system.iobus.slave[2] 737pio=system.iobus.master[27] 738 739[system.tsunami.fake_OROM] 740type=IsaFake
| 751platform=system.tsunami 752rss=false 753rx_delay=1000000 754rx_fifo_size=524288 755rx_filter=true 756rx_thread=false 757system=system 758tx_delay=1000000 759tx_fifo_size=524288 760tx_thread=false 761config=system.iobus.master[28] 762dma=system.iobus.slave[2] 763pio=system.iobus.master[27] 764 765[system.tsunami.fake_OROM] 766type=IsaFake
|
| 767clock=1000
|
741fake_mem=false 742pio_addr=8796093677568
| 768fake_mem=false 769pio_addr=8796093677568
|
743pio_latency=1000
| 770pio_latency=100000
|
744pio_size=393216 745ret_bad_addr=false 746ret_data16=65535 747ret_data32=4294967295 748ret_data64=18446744073709551615 749ret_data8=255 750system=system 751update_data=false 752warn_access= 753pio=system.iobus.master[8] 754 755[system.tsunami.fake_ata0] 756type=IsaFake
| 771pio_size=393216 772ret_bad_addr=false 773ret_data16=65535 774ret_data32=4294967295 775ret_data64=18446744073709551615 776ret_data8=255 777system=system 778update_data=false 779warn_access= 780pio=system.iobus.master[8] 781 782[system.tsunami.fake_ata0] 783type=IsaFake
|
| 784clock=1000
|
757fake_mem=false 758pio_addr=8804615848432
| 785fake_mem=false 786pio_addr=8804615848432
|
759pio_latency=1000
| 787pio_latency=100000
|
760pio_size=8 761ret_bad_addr=false 762ret_data16=65535 763ret_data32=4294967295 764ret_data64=18446744073709551615 765ret_data8=255 766system=system 767update_data=false 768warn_access= 769pio=system.iobus.master[19] 770 771[system.tsunami.fake_ata1] 772type=IsaFake
| 788pio_size=8 789ret_bad_addr=false 790ret_data16=65535 791ret_data32=4294967295 792ret_data64=18446744073709551615 793ret_data8=255 794system=system 795update_data=false 796warn_access= 797pio=system.iobus.master[19] 798 799[system.tsunami.fake_ata1] 800type=IsaFake
|
| 801clock=1000
|
773fake_mem=false 774pio_addr=8804615848304
| 802fake_mem=false 803pio_addr=8804615848304
|
775pio_latency=1000
| 804pio_latency=100000
|
776pio_size=8 777ret_bad_addr=false 778ret_data16=65535 779ret_data32=4294967295 780ret_data64=18446744073709551615 781ret_data8=255 782system=system 783update_data=false 784warn_access= 785pio=system.iobus.master[20] 786 787[system.tsunami.fake_pnp_addr] 788type=IsaFake
| 805pio_size=8 806ret_bad_addr=false 807ret_data16=65535 808ret_data32=4294967295 809ret_data64=18446744073709551615 810ret_data8=255 811system=system 812update_data=false 813warn_access= 814pio=system.iobus.master[20] 815 816[system.tsunami.fake_pnp_addr] 817type=IsaFake
|
| 818clock=1000
|
789fake_mem=false 790pio_addr=8804615848569
| 819fake_mem=false 820pio_addr=8804615848569
|
791pio_latency=1000
| 821pio_latency=100000
|
792pio_size=8 793ret_bad_addr=false 794ret_data16=65535 795ret_data32=4294967295 796ret_data64=18446744073709551615 797ret_data8=255 798system=system 799update_data=false 800warn_access= 801pio=system.iobus.master[9] 802 803[system.tsunami.fake_pnp_read0] 804type=IsaFake
| 822pio_size=8 823ret_bad_addr=false 824ret_data16=65535 825ret_data32=4294967295 826ret_data64=18446744073709551615 827ret_data8=255 828system=system 829update_data=false 830warn_access= 831pio=system.iobus.master[9] 832 833[system.tsunami.fake_pnp_read0] 834type=IsaFake
|
| 835clock=1000
|
805fake_mem=false 806pio_addr=8804615848451
| 836fake_mem=false 837pio_addr=8804615848451
|
807pio_latency=1000
| 838pio_latency=100000
|
808pio_size=8 809ret_bad_addr=false 810ret_data16=65535 811ret_data32=4294967295 812ret_data64=18446744073709551615 813ret_data8=255 814system=system 815update_data=false 816warn_access= 817pio=system.iobus.master[11] 818 819[system.tsunami.fake_pnp_read1] 820type=IsaFake
| 839pio_size=8 840ret_bad_addr=false 841ret_data16=65535 842ret_data32=4294967295 843ret_data64=18446744073709551615 844ret_data8=255 845system=system 846update_data=false 847warn_access= 848pio=system.iobus.master[11] 849 850[system.tsunami.fake_pnp_read1] 851type=IsaFake
|
| 852clock=1000
|
821fake_mem=false 822pio_addr=8804615848515
| 853fake_mem=false 854pio_addr=8804615848515
|
823pio_latency=1000
| 855pio_latency=100000
|
824pio_size=8 825ret_bad_addr=false 826ret_data16=65535 827ret_data32=4294967295 828ret_data64=18446744073709551615 829ret_data8=255 830system=system 831update_data=false 832warn_access= 833pio=system.iobus.master[12] 834 835[system.tsunami.fake_pnp_read2] 836type=IsaFake
| 856pio_size=8 857ret_bad_addr=false 858ret_data16=65535 859ret_data32=4294967295 860ret_data64=18446744073709551615 861ret_data8=255 862system=system 863update_data=false 864warn_access= 865pio=system.iobus.master[12] 866 867[system.tsunami.fake_pnp_read2] 868type=IsaFake
|
| 869clock=1000
|
837fake_mem=false 838pio_addr=8804615848579
| 870fake_mem=false 871pio_addr=8804615848579
|
839pio_latency=1000
| 872pio_latency=100000
|
840pio_size=8 841ret_bad_addr=false 842ret_data16=65535 843ret_data32=4294967295 844ret_data64=18446744073709551615 845ret_data8=255 846system=system 847update_data=false 848warn_access= 849pio=system.iobus.master[13] 850 851[system.tsunami.fake_pnp_read3] 852type=IsaFake
| 873pio_size=8 874ret_bad_addr=false 875ret_data16=65535 876ret_data32=4294967295 877ret_data64=18446744073709551615 878ret_data8=255 879system=system 880update_data=false 881warn_access= 882pio=system.iobus.master[13] 883 884[system.tsunami.fake_pnp_read3] 885type=IsaFake
|
| 886clock=1000
|
853fake_mem=false 854pio_addr=8804615848643
| 887fake_mem=false 888pio_addr=8804615848643
|
855pio_latency=1000
| 889pio_latency=100000
|
856pio_size=8 857ret_bad_addr=false 858ret_data16=65535 859ret_data32=4294967295 860ret_data64=18446744073709551615 861ret_data8=255 862system=system 863update_data=false 864warn_access= 865pio=system.iobus.master[14] 866 867[system.tsunami.fake_pnp_read4] 868type=IsaFake
| 890pio_size=8 891ret_bad_addr=false 892ret_data16=65535 893ret_data32=4294967295 894ret_data64=18446744073709551615 895ret_data8=255 896system=system 897update_data=false 898warn_access= 899pio=system.iobus.master[14] 900 901[system.tsunami.fake_pnp_read4] 902type=IsaFake
|
| 903clock=1000
|
869fake_mem=false 870pio_addr=8804615848707
| 904fake_mem=false 905pio_addr=8804615848707
|
871pio_latency=1000
| 906pio_latency=100000
|
872pio_size=8 873ret_bad_addr=false 874ret_data16=65535 875ret_data32=4294967295 876ret_data64=18446744073709551615 877ret_data8=255 878system=system 879update_data=false 880warn_access= 881pio=system.iobus.master[15] 882 883[system.tsunami.fake_pnp_read5] 884type=IsaFake
| 907pio_size=8 908ret_bad_addr=false 909ret_data16=65535 910ret_data32=4294967295 911ret_data64=18446744073709551615 912ret_data8=255 913system=system 914update_data=false 915warn_access= 916pio=system.iobus.master[15] 917 918[system.tsunami.fake_pnp_read5] 919type=IsaFake
|
| 920clock=1000
|
885fake_mem=false 886pio_addr=8804615848771
| 921fake_mem=false 922pio_addr=8804615848771
|
887pio_latency=1000
| 923pio_latency=100000
|
888pio_size=8 889ret_bad_addr=false 890ret_data16=65535 891ret_data32=4294967295 892ret_data64=18446744073709551615 893ret_data8=255 894system=system 895update_data=false 896warn_access= 897pio=system.iobus.master[16] 898 899[system.tsunami.fake_pnp_read6] 900type=IsaFake
| 924pio_size=8 925ret_bad_addr=false 926ret_data16=65535 927ret_data32=4294967295 928ret_data64=18446744073709551615 929ret_data8=255 930system=system 931update_data=false 932warn_access= 933pio=system.iobus.master[16] 934 935[system.tsunami.fake_pnp_read6] 936type=IsaFake
|
| 937clock=1000
|
901fake_mem=false 902pio_addr=8804615848835
| 938fake_mem=false 939pio_addr=8804615848835
|
903pio_latency=1000
| 940pio_latency=100000
|
904pio_size=8 905ret_bad_addr=false 906ret_data16=65535 907ret_data32=4294967295 908ret_data64=18446744073709551615 909ret_data8=255 910system=system 911update_data=false 912warn_access= 913pio=system.iobus.master[17] 914 915[system.tsunami.fake_pnp_read7] 916type=IsaFake
| 941pio_size=8 942ret_bad_addr=false 943ret_data16=65535 944ret_data32=4294967295 945ret_data64=18446744073709551615 946ret_data8=255 947system=system 948update_data=false 949warn_access= 950pio=system.iobus.master[17] 951 952[system.tsunami.fake_pnp_read7] 953type=IsaFake
|
| 954clock=1000
|
917fake_mem=false 918pio_addr=8804615848899
| 955fake_mem=false 956pio_addr=8804615848899
|
919pio_latency=1000
| 957pio_latency=100000
|
920pio_size=8 921ret_bad_addr=false 922ret_data16=65535 923ret_data32=4294967295 924ret_data64=18446744073709551615 925ret_data8=255 926system=system 927update_data=false 928warn_access= 929pio=system.iobus.master[18] 930 931[system.tsunami.fake_pnp_write] 932type=IsaFake
| 958pio_size=8 959ret_bad_addr=false 960ret_data16=65535 961ret_data32=4294967295 962ret_data64=18446744073709551615 963ret_data8=255 964system=system 965update_data=false 966warn_access= 967pio=system.iobus.master[18] 968 969[system.tsunami.fake_pnp_write] 970type=IsaFake
|
| 971clock=1000
|
933fake_mem=false 934pio_addr=8804615850617
| 972fake_mem=false 973pio_addr=8804615850617
|
935pio_latency=1000
| 974pio_latency=100000
|
936pio_size=8 937ret_bad_addr=false 938ret_data16=65535 939ret_data32=4294967295 940ret_data64=18446744073709551615 941ret_data8=255 942system=system 943update_data=false 944warn_access= 945pio=system.iobus.master[10] 946 947[system.tsunami.fake_ppc] 948type=IsaFake
| 975pio_size=8 976ret_bad_addr=false 977ret_data16=65535 978ret_data32=4294967295 979ret_data64=18446744073709551615 980ret_data8=255 981system=system 982update_data=false 983warn_access= 984pio=system.iobus.master[10] 985 986[system.tsunami.fake_ppc] 987type=IsaFake
|
| 988clock=1000
|
949fake_mem=false 950pio_addr=8804615848891
| 989fake_mem=false 990pio_addr=8804615848891
|
951pio_latency=1000
| 991pio_latency=100000
|
952pio_size=8 953ret_bad_addr=false 954ret_data16=65535 955ret_data32=4294967295 956ret_data64=18446744073709551615 957ret_data8=255 958system=system 959update_data=false 960warn_access= 961pio=system.iobus.master[7] 962 963[system.tsunami.fake_sm_chip] 964type=IsaFake
| 992pio_size=8 993ret_bad_addr=false 994ret_data16=65535 995ret_data32=4294967295 996ret_data64=18446744073709551615 997ret_data8=255 998system=system 999update_data=false 1000warn_access= 1001pio=system.iobus.master[7] 1002 1003[system.tsunami.fake_sm_chip] 1004type=IsaFake
|
| 1005clock=1000
|
965fake_mem=false 966pio_addr=8804615848816
| 1006fake_mem=false 1007pio_addr=8804615848816
|
967pio_latency=1000
| 1008pio_latency=100000
|
968pio_size=8 969ret_bad_addr=false 970ret_data16=65535 971ret_data32=4294967295 972ret_data64=18446744073709551615 973ret_data8=255 974system=system 975update_data=false 976warn_access= 977pio=system.iobus.master[2] 978 979[system.tsunami.fake_uart1] 980type=IsaFake
| 1009pio_size=8 1010ret_bad_addr=false 1011ret_data16=65535 1012ret_data32=4294967295 1013ret_data64=18446744073709551615 1014ret_data8=255 1015system=system 1016update_data=false 1017warn_access= 1018pio=system.iobus.master[2] 1019 1020[system.tsunami.fake_uart1] 1021type=IsaFake
|
| 1022clock=1000
|
981fake_mem=false 982pio_addr=8804615848696
| 1023fake_mem=false 1024pio_addr=8804615848696
|
983pio_latency=1000
| 1025pio_latency=100000
|
984pio_size=8 985ret_bad_addr=false 986ret_data16=65535 987ret_data32=4294967295 988ret_data64=18446744073709551615 989ret_data8=255 990system=system 991update_data=false 992warn_access= 993pio=system.iobus.master[3] 994 995[system.tsunami.fake_uart2] 996type=IsaFake
| 1026pio_size=8 1027ret_bad_addr=false 1028ret_data16=65535 1029ret_data32=4294967295 1030ret_data64=18446744073709551615 1031ret_data8=255 1032system=system 1033update_data=false 1034warn_access= 1035pio=system.iobus.master[3] 1036 1037[system.tsunami.fake_uart2] 1038type=IsaFake
|
| 1039clock=1000
|
997fake_mem=false 998pio_addr=8804615848936
| 1040fake_mem=false 1041pio_addr=8804615848936
|
999pio_latency=1000
| 1042pio_latency=100000
|
1000pio_size=8 1001ret_bad_addr=false 1002ret_data16=65535 1003ret_data32=4294967295 1004ret_data64=18446744073709551615 1005ret_data8=255 1006system=system 1007update_data=false 1008warn_access= 1009pio=system.iobus.master[4] 1010 1011[system.tsunami.fake_uart3] 1012type=IsaFake
| 1043pio_size=8 1044ret_bad_addr=false 1045ret_data16=65535 1046ret_data32=4294967295 1047ret_data64=18446744073709551615 1048ret_data8=255 1049system=system 1050update_data=false 1051warn_access= 1052pio=system.iobus.master[4] 1053 1054[system.tsunami.fake_uart3] 1055type=IsaFake
|
| 1056clock=1000
|
1013fake_mem=false 1014pio_addr=8804615848680
| 1057fake_mem=false 1058pio_addr=8804615848680
|
1015pio_latency=1000
| 1059pio_latency=100000
|
1016pio_size=8 1017ret_bad_addr=false 1018ret_data16=65535 1019ret_data32=4294967295 1020ret_data64=18446744073709551615 1021ret_data8=255 1022system=system 1023update_data=false 1024warn_access= 1025pio=system.iobus.master[5] 1026 1027[system.tsunami.fake_uart4] 1028type=IsaFake
| 1060pio_size=8 1061ret_bad_addr=false 1062ret_data16=65535 1063ret_data32=4294967295 1064ret_data64=18446744073709551615 1065ret_data8=255 1066system=system 1067update_data=false 1068warn_access= 1069pio=system.iobus.master[5] 1070 1071[system.tsunami.fake_uart4] 1072type=IsaFake
|
| 1073clock=1000
|
1029fake_mem=false 1030pio_addr=8804615848944
| 1074fake_mem=false 1075pio_addr=8804615848944
|
1031pio_latency=1000
| 1076pio_latency=100000
|
1032pio_size=8 1033ret_bad_addr=false 1034ret_data16=65535 1035ret_data32=4294967295 1036ret_data64=18446744073709551615 1037ret_data8=255 1038system=system 1039update_data=false 1040warn_access= 1041pio=system.iobus.master[6] 1042 1043[system.tsunami.fb] 1044type=BadDevice
| 1077pio_size=8 1078ret_bad_addr=false 1079ret_data16=65535 1080ret_data32=4294967295 1081ret_data64=18446744073709551615 1082ret_data8=255 1083system=system 1084update_data=false 1085warn_access= 1086pio=system.iobus.master[6] 1087 1088[system.tsunami.fb] 1089type=BadDevice
|
| 1090clock=1000
|
1045devicename=FrameBuffer 1046pio_addr=8804615848912
| 1091devicename=FrameBuffer 1092pio_addr=8804615848912
|
1047pio_latency=1000
| 1093pio_latency=100000
|
1048system=system 1049pio=system.iobus.master[21] 1050 1051[system.tsunami.ide] 1052type=IdeController 1053BAR0=1 1054BAR0LegacyIO=false 1055BAR0Size=8 1056BAR1=1 1057BAR1LegacyIO=false 1058BAR1Size=4 1059BAR2=1 1060BAR2LegacyIO=false 1061BAR2Size=8 1062BAR3=1 1063BAR3LegacyIO=false 1064BAR3Size=4 1065BAR4=1 1066BAR4LegacyIO=false 1067BAR4Size=16 1068BAR5=1 1069BAR5LegacyIO=false 1070BAR5Size=0 1071BIST=0 1072CacheLineSize=0 1073CardbusCIS=0 1074ClassCode=1 1075Command=0 1076DeviceID=28945 1077ExpansionROM=0 1078HeaderType=0 1079InterruptLine=31 1080InterruptPin=1 1081LatencyTimer=0 1082MaximumLatency=0 1083MinimumGrant=0 1084ProgIF=133 1085Revision=0 1086Status=640 1087SubClassCode=1 1088SubsystemID=0 1089SubsystemVendorID=0 1090VendorID=32902
| 1094system=system 1095pio=system.iobus.master[21] 1096 1097[system.tsunami.ide] 1098type=IdeController 1099BAR0=1 1100BAR0LegacyIO=false 1101BAR0Size=8 1102BAR1=1 1103BAR1LegacyIO=false 1104BAR1Size=4 1105BAR2=1 1106BAR2LegacyIO=false 1107BAR2Size=8 1108BAR3=1 1109BAR3LegacyIO=false 1110BAR3Size=4 1111BAR4=1 1112BAR4LegacyIO=false 1113BAR4Size=16 1114BAR5=1 1115BAR5LegacyIO=false 1116BAR5Size=0 1117BIST=0 1118CacheLineSize=0 1119CardbusCIS=0 1120ClassCode=1 1121Command=0 1122DeviceID=28945 1123ExpansionROM=0 1124HeaderType=0 1125InterruptLine=31 1126InterruptPin=1 1127LatencyTimer=0 1128MaximumLatency=0 1129MinimumGrant=0 1130ProgIF=133 1131Revision=0 1132Status=640 1133SubClassCode=1 1134SubsystemID=0 1135SubsystemVendorID=0 1136VendorID=32902
|
| 1137clock=1000
|
1091config_latency=20000 1092ctrl_offset=0 1093disks=system.disk0 system.disk2 1094io_shift=0
| 1138config_latency=20000 1139ctrl_offset=0 1140disks=system.disk0 system.disk2 1141io_shift=0
|
1095max_backoff_delay=10000000 1096min_backoff_delay=4000
| |
1097pci_bus=0 1098pci_dev=0 1099pci_func=0
| 1142pci_bus=0 1143pci_dev=0 1144pci_func=0
|
1100pio_latency=1000
| 1145pio_latency=30000
|
1101platform=system.tsunami 1102system=system 1103config=system.iobus.master[26] 1104dma=system.iobus.slave[1] 1105pio=system.iobus.master[25] 1106 1107[system.tsunami.io] 1108type=TsunamiIO
| 1146platform=system.tsunami 1147system=system 1148config=system.iobus.master[26] 1149dma=system.iobus.slave[1] 1150pio=system.iobus.master[25] 1151 1152[system.tsunami.io] 1153type=TsunamiIO
|
| 1154clock=1000
|
1109frequency=976562500 1110pio_addr=8804615847936
| 1155frequency=976562500 1156pio_addr=8804615847936
|
1111pio_latency=1000
| 1157pio_latency=100000
|
1112system=system 1113time=Thu Jan 1 00:00:00 2009 1114tsunami=system.tsunami 1115year_is_bcd=false 1116pio=system.iobus.master[22] 1117 1118[system.tsunami.pchip] 1119type=TsunamiPChip
| 1158system=system 1159time=Thu Jan 1 00:00:00 2009 1160tsunami=system.tsunami 1161year_is_bcd=false 1162pio=system.iobus.master[22] 1163 1164[system.tsunami.pchip] 1165type=TsunamiPChip
|
| 1166clock=1000
|
1120pio_addr=8802535473152
| 1167pio_addr=8802535473152
|
1121pio_latency=1000
| 1168pio_latency=100000
|
1122system=system 1123tsunami=system.tsunami 1124pio=system.iobus.master[1] 1125 1126[system.tsunami.pciconfig] 1127type=PciConfigAll 1128bus=0
| 1169system=system 1170tsunami=system.tsunami 1171pio=system.iobus.master[1] 1172 1173[system.tsunami.pciconfig] 1174type=PciConfigAll 1175bus=0
|
1129pio_latency=1
| 1176clock=1000 1177pio_latency=30000
|
1130platform=system.tsunami 1131size=16777216 1132system=system 1133pio=system.iobus.default 1134 1135[system.tsunami.uart] 1136type=Uart8250
| 1178platform=system.tsunami 1179size=16777216 1180system=system 1181pio=system.iobus.default 1182 1183[system.tsunami.uart] 1184type=Uart8250
|
| 1185clock=1000
|
1137pio_addr=8804615848952
| 1186pio_addr=8804615848952
|
1138pio_latency=1000
| 1187pio_latency=100000
|
1139platform=system.tsunami 1140system=system 1141terminal=system.terminal 1142pio=system.iobus.master[23] 1143
| 1188platform=system.tsunami 1189system=system 1190terminal=system.terminal 1191pio=system.iobus.master[23] 1192
|