config.ini (9924:31ef410b6843) | config.ini (9988:0b2e590c85be) |
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1[root] 2type=Root 3children=system | 1[root] 2type=Root 3children=system |
4eventq_index=0 |
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4full_system=true | 5full_system=true |
6sim_quantum=0 |
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5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxAlphaSystem 11children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain 12boot_cpu_frequency=500 13boot_osflags=root=/dev/hda1 console=ttyS0 14cache_line_size=64 15clk_domain=system.clk_domain | 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxAlphaSystem 13children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain 14boot_cpu_frequency=500 15boot_osflags=root=/dev/hda1 console=ttyS0 16cache_line_size=64 17clk_domain=system.clk_domain |
16console=/dist/m5/system/binaries/console | 18console=/scratch/nilay/GEM5/system/binaries/console 19eventq_index=0 |
17init_param=0 | 20init_param=0 |
18kernel=/dist/m5/system/binaries/vmlinux | 21kernel=/scratch/nilay/GEM5/system/binaries/vmlinux |
19load_addr_mask=1099511627775 20mem_mode=timing 21mem_ranges=0:134217727 22memories=system.physmem 23num_work_ids=16 | 22load_addr_mask=1099511627775 23mem_mode=timing 24mem_ranges=0:134217727 25memories=system.physmem 26num_work_ids=16 |
24pal=/dist/m5/system/binaries/ts_osfpal | 27pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal |
25readfile=tests/halt.sh 26symbolfile= 27system_rev=1024 28system_type=34 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[0] 37 38[system.bridge] 39type=Bridge 40clk_domain=system.clk_domain 41delay=50000 | 28readfile=tests/halt.sh 29symbolfile= 30system_rev=1024 31system_type=34 32work_begin_ckpt_count=0 33work_begin_cpu_id_exit=-1 34work_begin_exit_count=0 35work_cpus_ckpt_count=0 36work_end_ckpt_count=0 37work_end_exit_count=0 38work_item_id=-1 39system_port=system.membus.slave[0] 40 41[system.bridge] 42type=Bridge 43clk_domain=system.clk_domain 44delay=50000 |
45eventq_index=0 |
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42ranges=8796093022208:18446744073709551615 43req_size=16 44resp_size=16 45master=system.iobus.slave[0] 46slave=system.membus.master[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 | 46ranges=8796093022208:18446744073709551615 47req_size=16 48resp_size=16 49master=system.iobus.slave[0] 50slave=system.membus.master[0] 51 52[system.clk_domain] 53type=SrcClockDomain 54clock=1000 |
55eventq_index=0 |
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51voltage_domain=system.voltage_domain 52 53[system.cpu] 54type=DerivO3CPU 55children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer 56LFSTSize=1024 57LQEntries=32 58LSQCheckLoads=true --- 15 unchanged lines hidden (view full) --- 74decodeToFetchDelay=1 75decodeToRenameDelay=1 76decodeWidth=8 77dispatchWidth=8 78do_checkpoint_insts=true 79do_quiesce=true 80do_statistics_insts=true 81dtb=system.cpu.dtb | 56voltage_domain=system.voltage_domain 57 58[system.cpu] 59type=DerivO3CPU 60children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer 61LFSTSize=1024 62LQEntries=32 63LSQCheckLoads=true --- 15 unchanged lines hidden (view full) --- 79decodeToFetchDelay=1 80decodeToRenameDelay=1 81decodeWidth=8 82dispatchWidth=8 83do_checkpoint_insts=true 84do_quiesce=true 85do_statistics_insts=true 86dtb=system.cpu.dtb |
87eventq_index=0 88fetchBufferSize=64 |
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82fetchToDecodeDelay=1 83fetchTrapLatency=1 84fetchWidth=8 85forwardComSize=5 86fuPool=system.cpu.fuPool 87function_trace=false 88function_trace_start=0 89iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 138 139[system.cpu.branchPred] 140type=BranchPredictor 141BTBEntries=4096 142BTBTagSize=16 143RASSize=16 144choiceCtrBits=2 145choicePredictorSize=8192 | 89fetchToDecodeDelay=1 90fetchTrapLatency=1 91fetchWidth=8 92forwardComSize=5 93fuPool=system.cpu.fuPool 94function_trace=false 95function_trace_start=0 96iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 145 146[system.cpu.branchPred] 147type=BranchPredictor 148BTBEntries=4096 149BTBTagSize=16 150RASSize=16 151choiceCtrBits=2 152choicePredictorSize=8192 |
153eventq_index=0 |
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146globalCtrBits=2 147globalPredictorSize=8192 148instShiftAmt=2 149localCtrBits=2 150localHistoryTableSize=2048 151localPredictorSize=2048 152numThreads=1 153predType=tournament 154 155[system.cpu.dcache] 156type=BaseCache 157children=tags 158addr_ranges=0:18446744073709551615 159assoc=4 160clk_domain=system.cpu_clk_domain | 154globalCtrBits=2 155globalPredictorSize=8192 156instShiftAmt=2 157localCtrBits=2 158localHistoryTableSize=2048 159localPredictorSize=2048 160numThreads=1 161predType=tournament 162 163[system.cpu.dcache] 164type=BaseCache 165children=tags 166addr_ranges=0:18446744073709551615 167assoc=4 168clk_domain=system.cpu_clk_domain |
169eventq_index=0 |
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161forward_snoops=true 162hit_latency=2 163is_top_level=true 164max_miss_count=0 165mshrs=4 166prefetch_on_access=false 167prefetcher=Null 168response_latency=2 --- 6 unchanged lines hidden (view full) --- 175cpu_side=system.cpu.dcache_port 176mem_side=system.cpu.toL2Bus.slave[1] 177 178[system.cpu.dcache.tags] 179type=LRU 180assoc=4 181block_size=64 182clk_domain=system.cpu_clk_domain | 170forward_snoops=true 171hit_latency=2 172is_top_level=true 173max_miss_count=0 174mshrs=4 175prefetch_on_access=false 176prefetcher=Null 177response_latency=2 --- 6 unchanged lines hidden (view full) --- 184cpu_side=system.cpu.dcache_port 185mem_side=system.cpu.toL2Bus.slave[1] 186 187[system.cpu.dcache.tags] 188type=LRU 189assoc=4 190block_size=64 191clk_domain=system.cpu_clk_domain |
192eventq_index=0 |
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183hit_latency=2 184size=32768 185 186[system.cpu.dtb] 187type=AlphaTLB | 193hit_latency=2 194size=32768 195 196[system.cpu.dtb] 197type=AlphaTLB |
198eventq_index=0 |
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188size=64 189 190[system.cpu.fuPool] 191type=FUPool 192children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 193FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 | 199size=64 200 201[system.cpu.fuPool] 202type=FUPool 203children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 204FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 |
205eventq_index=0 |
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194 195[system.cpu.fuPool.FUList0] 196type=FUDesc 197children=opList 198count=6 | 206 207[system.cpu.fuPool.FUList0] 208type=FUDesc 209children=opList 210count=6 |
211eventq_index=0 |
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199opList=system.cpu.fuPool.FUList0.opList 200 201[system.cpu.fuPool.FUList0.opList] 202type=OpDesc | 212opList=system.cpu.fuPool.FUList0.opList 213 214[system.cpu.fuPool.FUList0.opList] 215type=OpDesc |
216eventq_index=0 |
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203issueLat=1 204opClass=IntAlu 205opLat=1 206 207[system.cpu.fuPool.FUList1] 208type=FUDesc 209children=opList0 opList1 210count=2 | 217issueLat=1 218opClass=IntAlu 219opLat=1 220 221[system.cpu.fuPool.FUList1] 222type=FUDesc 223children=opList0 opList1 224count=2 |
225eventq_index=0 |
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211opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 212 213[system.cpu.fuPool.FUList1.opList0] 214type=OpDesc | 226opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 227 228[system.cpu.fuPool.FUList1.opList0] 229type=OpDesc |
230eventq_index=0 |
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215issueLat=1 216opClass=IntMult 217opLat=3 218 219[system.cpu.fuPool.FUList1.opList1] 220type=OpDesc | 231issueLat=1 232opClass=IntMult 233opLat=3 234 235[system.cpu.fuPool.FUList1.opList1] 236type=OpDesc |
237eventq_index=0 |
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221issueLat=19 222opClass=IntDiv 223opLat=20 224 225[system.cpu.fuPool.FUList2] 226type=FUDesc 227children=opList0 opList1 opList2 228count=4 | 238issueLat=19 239opClass=IntDiv 240opLat=20 241 242[system.cpu.fuPool.FUList2] 243type=FUDesc 244children=opList0 opList1 opList2 245count=4 |
246eventq_index=0 |
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229opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 230 231[system.cpu.fuPool.FUList2.opList0] 232type=OpDesc | 247opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 248 249[system.cpu.fuPool.FUList2.opList0] 250type=OpDesc |
251eventq_index=0 |
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233issueLat=1 234opClass=FloatAdd 235opLat=2 236 237[system.cpu.fuPool.FUList2.opList1] 238type=OpDesc | 252issueLat=1 253opClass=FloatAdd 254opLat=2 255 256[system.cpu.fuPool.FUList2.opList1] 257type=OpDesc |
258eventq_index=0 |
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239issueLat=1 240opClass=FloatCmp 241opLat=2 242 243[system.cpu.fuPool.FUList2.opList2] 244type=OpDesc | 259issueLat=1 260opClass=FloatCmp 261opLat=2 262 263[system.cpu.fuPool.FUList2.opList2] 264type=OpDesc |
265eventq_index=0 |
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245issueLat=1 246opClass=FloatCvt 247opLat=2 248 249[system.cpu.fuPool.FUList3] 250type=FUDesc 251children=opList0 opList1 opList2 252count=2 | 266issueLat=1 267opClass=FloatCvt 268opLat=2 269 270[system.cpu.fuPool.FUList3] 271type=FUDesc 272children=opList0 opList1 opList2 273count=2 |
274eventq_index=0 |
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253opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 254 255[system.cpu.fuPool.FUList3.opList0] 256type=OpDesc | 275opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 276 277[system.cpu.fuPool.FUList3.opList0] 278type=OpDesc |
279eventq_index=0 |
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257issueLat=1 258opClass=FloatMult 259opLat=4 260 261[system.cpu.fuPool.FUList3.opList1] 262type=OpDesc | 280issueLat=1 281opClass=FloatMult 282opLat=4 283 284[system.cpu.fuPool.FUList3.opList1] 285type=OpDesc |
286eventq_index=0 |
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263issueLat=12 264opClass=FloatDiv 265opLat=12 266 267[system.cpu.fuPool.FUList3.opList2] 268type=OpDesc | 287issueLat=12 288opClass=FloatDiv 289opLat=12 290 291[system.cpu.fuPool.FUList3.opList2] 292type=OpDesc |
293eventq_index=0 |
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269issueLat=24 270opClass=FloatSqrt 271opLat=24 272 273[system.cpu.fuPool.FUList4] 274type=FUDesc 275children=opList 276count=0 | 294issueLat=24 295opClass=FloatSqrt 296opLat=24 297 298[system.cpu.fuPool.FUList4] 299type=FUDesc 300children=opList 301count=0 |
302eventq_index=0 |
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277opList=system.cpu.fuPool.FUList4.opList 278 279[system.cpu.fuPool.FUList4.opList] 280type=OpDesc | 303opList=system.cpu.fuPool.FUList4.opList 304 305[system.cpu.fuPool.FUList4.opList] 306type=OpDesc |
307eventq_index=0 |
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281issueLat=1 282opClass=MemRead 283opLat=1 284 285[system.cpu.fuPool.FUList5] 286type=FUDesc 287children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 288count=4 | 308issueLat=1 309opClass=MemRead 310opLat=1 311 312[system.cpu.fuPool.FUList5] 313type=FUDesc 314children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 315count=4 |
316eventq_index=0 |
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289opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 290 291[system.cpu.fuPool.FUList5.opList00] 292type=OpDesc | 317opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 318 319[system.cpu.fuPool.FUList5.opList00] 320type=OpDesc |
321eventq_index=0 |
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293issueLat=1 294opClass=SimdAdd 295opLat=1 296 297[system.cpu.fuPool.FUList5.opList01] 298type=OpDesc | 322issueLat=1 323opClass=SimdAdd 324opLat=1 325 326[system.cpu.fuPool.FUList5.opList01] 327type=OpDesc |
328eventq_index=0 |
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299issueLat=1 300opClass=SimdAddAcc 301opLat=1 302 303[system.cpu.fuPool.FUList5.opList02] 304type=OpDesc | 329issueLat=1 330opClass=SimdAddAcc 331opLat=1 332 333[system.cpu.fuPool.FUList5.opList02] 334type=OpDesc |
335eventq_index=0 |
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305issueLat=1 306opClass=SimdAlu 307opLat=1 308 309[system.cpu.fuPool.FUList5.opList03] 310type=OpDesc | 336issueLat=1 337opClass=SimdAlu 338opLat=1 339 340[system.cpu.fuPool.FUList5.opList03] 341type=OpDesc |
342eventq_index=0 |
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311issueLat=1 312opClass=SimdCmp 313opLat=1 314 315[system.cpu.fuPool.FUList5.opList04] 316type=OpDesc | 343issueLat=1 344opClass=SimdCmp 345opLat=1 346 347[system.cpu.fuPool.FUList5.opList04] 348type=OpDesc |
349eventq_index=0 |
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317issueLat=1 318opClass=SimdCvt 319opLat=1 320 321[system.cpu.fuPool.FUList5.opList05] 322type=OpDesc | 350issueLat=1 351opClass=SimdCvt 352opLat=1 353 354[system.cpu.fuPool.FUList5.opList05] 355type=OpDesc |
356eventq_index=0 |
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323issueLat=1 324opClass=SimdMisc 325opLat=1 326 327[system.cpu.fuPool.FUList5.opList06] 328type=OpDesc | 357issueLat=1 358opClass=SimdMisc 359opLat=1 360 361[system.cpu.fuPool.FUList5.opList06] 362type=OpDesc |
363eventq_index=0 |
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329issueLat=1 330opClass=SimdMult 331opLat=1 332 333[system.cpu.fuPool.FUList5.opList07] 334type=OpDesc | 364issueLat=1 365opClass=SimdMult 366opLat=1 367 368[system.cpu.fuPool.FUList5.opList07] 369type=OpDesc |
370eventq_index=0 |
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335issueLat=1 336opClass=SimdMultAcc 337opLat=1 338 339[system.cpu.fuPool.FUList5.opList08] 340type=OpDesc | 371issueLat=1 372opClass=SimdMultAcc 373opLat=1 374 375[system.cpu.fuPool.FUList5.opList08] 376type=OpDesc |
377eventq_index=0 |
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341issueLat=1 342opClass=SimdShift 343opLat=1 344 345[system.cpu.fuPool.FUList5.opList09] 346type=OpDesc | 378issueLat=1 379opClass=SimdShift 380opLat=1 381 382[system.cpu.fuPool.FUList5.opList09] 383type=OpDesc |
384eventq_index=0 |
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347issueLat=1 348opClass=SimdShiftAcc 349opLat=1 350 351[system.cpu.fuPool.FUList5.opList10] 352type=OpDesc | 385issueLat=1 386opClass=SimdShiftAcc 387opLat=1 388 389[system.cpu.fuPool.FUList5.opList10] 390type=OpDesc |
391eventq_index=0 |
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353issueLat=1 354opClass=SimdSqrt 355opLat=1 356 357[system.cpu.fuPool.FUList5.opList11] 358type=OpDesc | 392issueLat=1 393opClass=SimdSqrt 394opLat=1 395 396[system.cpu.fuPool.FUList5.opList11] 397type=OpDesc |
398eventq_index=0 |
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359issueLat=1 360opClass=SimdFloatAdd 361opLat=1 362 363[system.cpu.fuPool.FUList5.opList12] 364type=OpDesc | 399issueLat=1 400opClass=SimdFloatAdd 401opLat=1 402 403[system.cpu.fuPool.FUList5.opList12] 404type=OpDesc |
405eventq_index=0 |
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365issueLat=1 366opClass=SimdFloatAlu 367opLat=1 368 369[system.cpu.fuPool.FUList5.opList13] 370type=OpDesc | 406issueLat=1 407opClass=SimdFloatAlu 408opLat=1 409 410[system.cpu.fuPool.FUList5.opList13] 411type=OpDesc |
412eventq_index=0 |
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371issueLat=1 372opClass=SimdFloatCmp 373opLat=1 374 375[system.cpu.fuPool.FUList5.opList14] 376type=OpDesc | 413issueLat=1 414opClass=SimdFloatCmp 415opLat=1 416 417[system.cpu.fuPool.FUList5.opList14] 418type=OpDesc |
419eventq_index=0 |
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377issueLat=1 378opClass=SimdFloatCvt 379opLat=1 380 381[system.cpu.fuPool.FUList5.opList15] 382type=OpDesc | 420issueLat=1 421opClass=SimdFloatCvt 422opLat=1 423 424[system.cpu.fuPool.FUList5.opList15] 425type=OpDesc |
426eventq_index=0 |
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383issueLat=1 384opClass=SimdFloatDiv 385opLat=1 386 387[system.cpu.fuPool.FUList5.opList16] 388type=OpDesc | 427issueLat=1 428opClass=SimdFloatDiv 429opLat=1 430 431[system.cpu.fuPool.FUList5.opList16] 432type=OpDesc |
433eventq_index=0 |
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389issueLat=1 390opClass=SimdFloatMisc 391opLat=1 392 393[system.cpu.fuPool.FUList5.opList17] 394type=OpDesc | 434issueLat=1 435opClass=SimdFloatMisc 436opLat=1 437 438[system.cpu.fuPool.FUList5.opList17] 439type=OpDesc |
440eventq_index=0 |
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395issueLat=1 396opClass=SimdFloatMult 397opLat=1 398 399[system.cpu.fuPool.FUList5.opList18] 400type=OpDesc | 441issueLat=1 442opClass=SimdFloatMult 443opLat=1 444 445[system.cpu.fuPool.FUList5.opList18] 446type=OpDesc |
447eventq_index=0 |
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401issueLat=1 402opClass=SimdFloatMultAcc 403opLat=1 404 405[system.cpu.fuPool.FUList5.opList19] 406type=OpDesc | 448issueLat=1 449opClass=SimdFloatMultAcc 450opLat=1 451 452[system.cpu.fuPool.FUList5.opList19] 453type=OpDesc |
454eventq_index=0 |
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407issueLat=1 408opClass=SimdFloatSqrt 409opLat=1 410 411[system.cpu.fuPool.FUList6] 412type=FUDesc 413children=opList 414count=0 | 455issueLat=1 456opClass=SimdFloatSqrt 457opLat=1 458 459[system.cpu.fuPool.FUList6] 460type=FUDesc 461children=opList 462count=0 |
463eventq_index=0 |
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415opList=system.cpu.fuPool.FUList6.opList 416 417[system.cpu.fuPool.FUList6.opList] 418type=OpDesc | 464opList=system.cpu.fuPool.FUList6.opList 465 466[system.cpu.fuPool.FUList6.opList] 467type=OpDesc |
468eventq_index=0 |
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419issueLat=1 420opClass=MemWrite 421opLat=1 422 423[system.cpu.fuPool.FUList7] 424type=FUDesc 425children=opList0 opList1 426count=4 | 469issueLat=1 470opClass=MemWrite 471opLat=1 472 473[system.cpu.fuPool.FUList7] 474type=FUDesc 475children=opList0 opList1 476count=4 |
477eventq_index=0 |
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427opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 428 429[system.cpu.fuPool.FUList7.opList0] 430type=OpDesc | 478opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 479 480[system.cpu.fuPool.FUList7.opList0] 481type=OpDesc |
482eventq_index=0 |
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431issueLat=1 432opClass=MemRead 433opLat=1 434 435[system.cpu.fuPool.FUList7.opList1] 436type=OpDesc | 483issueLat=1 484opClass=MemRead 485opLat=1 486 487[system.cpu.fuPool.FUList7.opList1] 488type=OpDesc |
489eventq_index=0 |
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437issueLat=1 438opClass=MemWrite 439opLat=1 440 441[system.cpu.fuPool.FUList8] 442type=FUDesc 443children=opList 444count=1 | 490issueLat=1 491opClass=MemWrite 492opLat=1 493 494[system.cpu.fuPool.FUList8] 495type=FUDesc 496children=opList 497count=1 |
498eventq_index=0 |
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445opList=system.cpu.fuPool.FUList8.opList 446 447[system.cpu.fuPool.FUList8.opList] 448type=OpDesc | 499opList=system.cpu.fuPool.FUList8.opList 500 501[system.cpu.fuPool.FUList8.opList] 502type=OpDesc |
503eventq_index=0 |
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449issueLat=3 450opClass=IprAccess 451opLat=3 452 453[system.cpu.icache] 454type=BaseCache 455children=tags 456addr_ranges=0:18446744073709551615 457assoc=1 458clk_domain=system.cpu_clk_domain | 504issueLat=3 505opClass=IprAccess 506opLat=3 507 508[system.cpu.icache] 509type=BaseCache 510children=tags 511addr_ranges=0:18446744073709551615 512assoc=1 513clk_domain=system.cpu_clk_domain |
514eventq_index=0 |
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459forward_snoops=true 460hit_latency=2 461is_top_level=true 462max_miss_count=0 463mshrs=4 464prefetch_on_access=false 465prefetcher=Null 466response_latency=2 --- 6 unchanged lines hidden (view full) --- 473cpu_side=system.cpu.icache_port 474mem_side=system.cpu.toL2Bus.slave[0] 475 476[system.cpu.icache.tags] 477type=LRU 478assoc=1 479block_size=64 480clk_domain=system.cpu_clk_domain | 515forward_snoops=true 516hit_latency=2 517is_top_level=true 518max_miss_count=0 519mshrs=4 520prefetch_on_access=false 521prefetcher=Null 522response_latency=2 --- 6 unchanged lines hidden (view full) --- 529cpu_side=system.cpu.icache_port 530mem_side=system.cpu.toL2Bus.slave[0] 531 532[system.cpu.icache.tags] 533type=LRU 534assoc=1 535block_size=64 536clk_domain=system.cpu_clk_domain |
537eventq_index=0 |
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481hit_latency=2 482size=32768 483 484[system.cpu.interrupts] 485type=AlphaInterrupts | 538hit_latency=2 539size=32768 540 541[system.cpu.interrupts] 542type=AlphaInterrupts |
543eventq_index=0 |
|
486 487[system.cpu.isa] 488type=AlphaISA | 544 545[system.cpu.isa] 546type=AlphaISA |
547eventq_index=0 |
|
489 490[system.cpu.itb] 491type=AlphaTLB | 548 549[system.cpu.itb] 550type=AlphaTLB |
551eventq_index=0 |
|
492size=48 493 494[system.cpu.l2cache] 495type=BaseCache 496children=tags 497addr_ranges=0:18446744073709551615 498assoc=8 499clk_domain=system.cpu_clk_domain | 552size=48 553 554[system.cpu.l2cache] 555type=BaseCache 556children=tags 557addr_ranges=0:18446744073709551615 558assoc=8 559clk_domain=system.cpu_clk_domain |
560eventq_index=0 |
|
500forward_snoops=true 501hit_latency=20 502is_top_level=false 503max_miss_count=0 504mshrs=20 505prefetch_on_access=false 506prefetcher=Null 507response_latency=20 --- 6 unchanged lines hidden (view full) --- 514cpu_side=system.cpu.toL2Bus.master[0] 515mem_side=system.membus.slave[1] 516 517[system.cpu.l2cache.tags] 518type=LRU 519assoc=8 520block_size=64 521clk_domain=system.cpu_clk_domain | 561forward_snoops=true 562hit_latency=20 563is_top_level=false 564max_miss_count=0 565mshrs=20 566prefetch_on_access=false 567prefetcher=Null 568response_latency=20 --- 6 unchanged lines hidden (view full) --- 575cpu_side=system.cpu.toL2Bus.master[0] 576mem_side=system.membus.slave[1] 577 578[system.cpu.l2cache.tags] 579type=LRU 580assoc=8 581block_size=64 582clk_domain=system.cpu_clk_domain |
583eventq_index=0 |
|
522hit_latency=20 523size=4194304 524 525[system.cpu.toL2Bus] 526type=CoherentBus 527clk_domain=system.cpu_clk_domain | 584hit_latency=20 585size=4194304 586 587[system.cpu.toL2Bus] 588type=CoherentBus 589clk_domain=system.cpu_clk_domain |
590eventq_index=0 |
|
528header_cycles=1 529system=system 530use_default_range=false 531width=32 532master=system.cpu.l2cache.cpu_side 533slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 534 535[system.cpu.tracer] 536type=ExeTracer | 591header_cycles=1 592system=system 593use_default_range=false 594width=32 595master=system.cpu.l2cache.cpu_side 596slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 597 598[system.cpu.tracer] 599type=ExeTracer |
600eventq_index=0 |
|
537 538[system.cpu_clk_domain] 539type=SrcClockDomain 540clock=500 | 601 602[system.cpu_clk_domain] 603type=SrcClockDomain 604clock=500 |
605eventq_index=0 |
|
541voltage_domain=system.voltage_domain 542 543[system.disk0] 544type=IdeDisk 545children=image 546delay=1000000 547driveID=master | 606voltage_domain=system.voltage_domain 607 608[system.disk0] 609type=IdeDisk 610children=image 611delay=1000000 612driveID=master |
613eventq_index=0 |
|
548image=system.disk0.image 549 550[system.disk0.image] 551type=CowDiskImage 552children=child 553child=system.disk0.image.child | 614image=system.disk0.image 615 616[system.disk0.image] 617type=CowDiskImage 618children=child 619child=system.disk0.image.child |
620eventq_index=0 |
|
554image_file= 555read_only=false 556table_size=65536 557 558[system.disk0.image.child] 559type=RawDiskImage | 621image_file= 622read_only=false 623table_size=65536 624 625[system.disk0.image.child] 626type=RawDiskImage |
560image_file=/dist/m5/system/disks/linux-latest.img | 627eventq_index=0 628image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img |
561read_only=true 562 563[system.disk2] 564type=IdeDisk 565children=image 566delay=1000000 567driveID=master | 629read_only=true 630 631[system.disk2] 632type=IdeDisk 633children=image 634delay=1000000 635driveID=master |
636eventq_index=0 |
|
568image=system.disk2.image 569 570[system.disk2.image] 571type=CowDiskImage 572children=child 573child=system.disk2.image.child | 637image=system.disk2.image 638 639[system.disk2.image] 640type=CowDiskImage 641children=child 642child=system.disk2.image.child |
643eventq_index=0 |
|
574image_file= 575read_only=false 576table_size=65536 577 578[system.disk2.image.child] 579type=RawDiskImage | 644image_file= 645read_only=false 646table_size=65536 647 648[system.disk2.image.child] 649type=RawDiskImage |
580image_file=/dist/m5/system/disks/linux-bigswap2.img | 650eventq_index=0 651image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img |
581read_only=true 582 583[system.intrctrl] 584type=IntrControl | 652read_only=true 653 654[system.intrctrl] 655type=IntrControl |
656eventq_index=0 |
|
585sys=system 586 587[system.iobus] 588type=NoncoherentBus 589clk_domain=system.clk_domain | 657sys=system 658 659[system.iobus] 660type=NoncoherentBus 661clk_domain=system.clk_domain |
662eventq_index=0 |
|
590header_cycles=1 591use_default_range=true 592width=8 593default=system.tsunami.pciconfig.pio 594master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 595slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 596 597[system.iocache] 598type=BaseCache 599children=tags 600addr_ranges=0:134217727 601assoc=8 602clk_domain=system.clk_domain | 663header_cycles=1 664use_default_range=true 665width=8 666default=system.tsunami.pciconfig.pio 667master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 668slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 669 670[system.iocache] 671type=BaseCache 672children=tags 673addr_ranges=0:134217727 674assoc=8 675clk_domain=system.clk_domain |
676eventq_index=0 |
|
603forward_snoops=false 604hit_latency=50 605is_top_level=true 606max_miss_count=0 607mshrs=20 608prefetch_on_access=false 609prefetcher=Null 610response_latency=50 --- 6 unchanged lines hidden (view full) --- 617cpu_side=system.iobus.master[29] 618mem_side=system.membus.slave[2] 619 620[system.iocache.tags] 621type=LRU 622assoc=8 623block_size=64 624clk_domain=system.clk_domain | 677forward_snoops=false 678hit_latency=50 679is_top_level=true 680max_miss_count=0 681mshrs=20 682prefetch_on_access=false 683prefetcher=Null 684response_latency=50 --- 6 unchanged lines hidden (view full) --- 691cpu_side=system.iobus.master[29] 692mem_side=system.membus.slave[2] 693 694[system.iocache.tags] 695type=LRU 696assoc=8 697block_size=64 698clk_domain=system.clk_domain |
699eventq_index=0 |
|
625hit_latency=50 626size=1024 627 628[system.membus] 629type=CoherentBus 630children=badaddr_responder 631clk_domain=system.clk_domain | 700hit_latency=50 701size=1024 702 703[system.membus] 704type=CoherentBus 705children=badaddr_responder 706clk_domain=system.clk_domain |
707eventq_index=0 |
|
632header_cycles=1 633system=system 634use_default_range=false 635width=8 636default=system.membus.badaddr_responder.pio 637master=system.bridge.slave system.physmem.port 638slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 639 640[system.membus.badaddr_responder] 641type=IsaFake 642clk_domain=system.clk_domain | 708header_cycles=1 709system=system 710use_default_range=false 711width=8 712default=system.membus.badaddr_responder.pio 713master=system.bridge.slave system.physmem.port 714slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 715 716[system.membus.badaddr_responder] 717type=IsaFake 718clk_domain=system.clk_domain |
719eventq_index=0 |
|
643fake_mem=false 644pio_addr=0 645pio_latency=100000 646pio_size=8 647ret_bad_addr=true 648ret_data16=65535 649ret_data32=4294967295 650ret_data64=18446744073709551615 --- 10 unchanged lines hidden (view full) --- 661banks_per_rank=8 662burst_length=8 663channels=1 664clk_domain=system.clk_domain 665conf_table_reported=true 666device_bus_width=8 667device_rowbuffer_size=1024 668devices_per_rank=8 | 720fake_mem=false 721pio_addr=0 722pio_latency=100000 723pio_size=8 724ret_bad_addr=true 725ret_data16=65535 726ret_data32=4294967295 727ret_data64=18446744073709551615 --- 10 unchanged lines hidden (view full) --- 738banks_per_rank=8 739burst_length=8 740channels=1 741clk_domain=system.clk_domain 742conf_table_reported=true 743device_bus_width=8 744device_rowbuffer_size=1024 745devices_per_rank=8 |
746eventq_index=0 |
|
669in_addr_map=true 670mem_sched_policy=frfcfs 671null=false 672page_policy=open 673range=0:134217727 674ranks_per_channel=2 675read_buffer_size=32 676static_backend_latency=10000 677static_frontend_latency=10000 678tBURST=5000 679tCL=13750 | 747in_addr_map=true 748mem_sched_policy=frfcfs 749null=false 750page_policy=open 751range=0:134217727 752ranks_per_channel=2 753read_buffer_size=32 754static_backend_latency=10000 755static_frontend_latency=10000 756tBURST=5000 757tCL=13750 |
758tRAS=35000 |
|
680tRCD=13750 681tREFI=7800000 682tRFC=300000 683tRP=13750 | 759tRCD=13750 760tREFI=7800000 761tRFC=300000 762tRP=13750 |
763tRRD=6250 |
|
684tWTR=7500 685tXAW=40000 686write_buffer_size=32 | 764tWTR=7500 765tXAW=40000 766write_buffer_size=32 |
687write_thresh_perc=70 | 767write_high_thresh_perc=70 768write_low_thresh_perc=0 |
688port=system.membus.master[1] 689 690[system.simple_disk] 691type=SimpleDisk 692children=disk 693disk=system.simple_disk.disk | 769port=system.membus.master[1] 770 771[system.simple_disk] 772type=SimpleDisk 773children=disk 774disk=system.simple_disk.disk |
775eventq_index=0 |
|
694system=system 695 696[system.simple_disk.disk] 697type=RawDiskImage | 776system=system 777 778[system.simple_disk.disk] 779type=RawDiskImage |
698image_file=/dist/m5/system/disks/linux-latest.img | 780eventq_index=0 781image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img |
699read_only=true 700 701[system.terminal] 702type=Terminal | 782read_only=true 783 784[system.terminal] 785type=Terminal |
786eventq_index=0 |
|
703intr_control=system.intrctrl 704number=0 705output=true 706port=3456 707 708[system.tsunami] 709type=Tsunami 710children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart | 787intr_control=system.intrctrl 788number=0 789output=true 790port=3456 791 792[system.tsunami] 793type=Tsunami 794children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart |
795eventq_index=0 |
|
711intrctrl=system.intrctrl 712system=system 713 714[system.tsunami.backdoor] 715type=AlphaBackdoor 716clk_domain=system.clk_domain 717cpu=system.cpu 718disk=system.simple_disk | 796intrctrl=system.intrctrl 797system=system 798 799[system.tsunami.backdoor] 800type=AlphaBackdoor 801clk_domain=system.clk_domain 802cpu=system.cpu 803disk=system.simple_disk |
804eventq_index=0 |
|
719pio_addr=8804682956800 720pio_latency=100000 721platform=system.tsunami 722system=system 723terminal=system.terminal 724pio=system.iobus.master[24] 725 726[system.tsunami.cchip] 727type=TsunamiCChip 728clk_domain=system.clk_domain | 805pio_addr=8804682956800 806pio_latency=100000 807platform=system.tsunami 808system=system 809terminal=system.terminal 810pio=system.iobus.master[24] 811 812[system.tsunami.cchip] 813type=TsunamiCChip 814clk_domain=system.clk_domain |
815eventq_index=0 |
|
729pio_addr=8803072344064 730pio_latency=100000 731system=system 732tsunami=system.tsunami 733pio=system.iobus.master[0] 734 735[system.tsunami.ethernet] 736type=NSGigE --- 12 unchanged lines hidden (view full) --- 749BAR4=0 750BAR4LegacyIO=false 751BAR4Size=0 752BAR5=0 753BAR5LegacyIO=false 754BAR5Size=0 755BIST=0 756CacheLineSize=0 | 816pio_addr=8803072344064 817pio_latency=100000 818system=system 819tsunami=system.tsunami 820pio=system.iobus.master[0] 821 822[system.tsunami.ethernet] 823type=NSGigE --- 12 unchanged lines hidden (view full) --- 836BAR4=0 837BAR4LegacyIO=false 838BAR4Size=0 839BAR5=0 840BAR5LegacyIO=false 841BAR5Size=0 842BIST=0 843CacheLineSize=0 |
844CapabilityPtr=0 |
|
757CardbusCIS=0 758ClassCode=2 759Command=0 760DeviceID=34 761ExpansionROM=0 762HeaderType=0 763InterruptLine=30 764InterruptPin=1 765LatencyTimer=0 | 845CardbusCIS=0 846ClassCode=2 847Command=0 848DeviceID=34 849ExpansionROM=0 850HeaderType=0 851InterruptLine=30 852InterruptPin=1 853LatencyTimer=0 |
854MSICAPBaseOffset=0 855MSICAPCapId=0 856MSICAPMaskBits=0 857MSICAPMsgAddr=0 858MSICAPMsgCtrl=0 859MSICAPMsgData=0 860MSICAPMsgUpperAddr=0 861MSICAPNextCapability=0 862MSICAPPendingBits=0 863MSIXCAPBaseOffset=0 864MSIXCAPCapId=0 865MSIXCAPNextCapability=0 866MSIXMsgCtrl=0 867MSIXPbaOffset=0 868MSIXTableOffset=0 |
|
766MaximumLatency=52 767MinimumGrant=176 | 869MaximumLatency=52 870MinimumGrant=176 |
871PMCAPBaseOffset=0 872PMCAPCapId=0 873PMCAPCapabilities=0 874PMCAPCtrlStatus=0 875PMCAPNextCapability=0 876PXCAPBaseOffset=0 877PXCAPCapId=0 878PXCAPCapabilities=0 879PXCAPDevCap2=0 880PXCAPDevCapabilities=0 881PXCAPDevCtrl=0 882PXCAPDevCtrl2=0 883PXCAPDevStatus=0 884PXCAPLinkCap=0 885PXCAPLinkCtrl=0 886PXCAPLinkStatus=0 887PXCAPNextCapability=0 |
|
768ProgIF=0 769Revision=0 770Status=656 771SubClassCode=0 772SubsystemID=0 773SubsystemVendorID=0 774VendorID=4107 775clk_domain=system.clk_domain 776config_latency=20000 777dma_data_free=false 778dma_desc_free=false 779dma_no_allocate=true 780dma_read_delay=0 781dma_read_factor=0 782dma_write_delay=0 783dma_write_factor=0 | 888ProgIF=0 889Revision=0 890Status=656 891SubClassCode=0 892SubsystemID=0 893SubsystemVendorID=0 894VendorID=4107 895clk_domain=system.clk_domain 896config_latency=20000 897dma_data_free=false 898dma_desc_free=false 899dma_no_allocate=true 900dma_read_delay=0 901dma_read_factor=0 902dma_write_delay=0 903dma_write_factor=0 |
904eventq_index=0 |
|
784hardware_address=00:90:00:00:00:01 785intr_delay=10000000 786pci_bus=0 787pci_dev=1 788pci_func=0 789pio_latency=30000 790platform=system.tsunami 791rss=false --- 7 unchanged lines hidden (view full) --- 799tx_thread=false 800config=system.iobus.master[28] 801dma=system.iobus.slave[2] 802pio=system.iobus.master[27] 803 804[system.tsunami.fake_OROM] 805type=IsaFake 806clk_domain=system.clk_domain | 905hardware_address=00:90:00:00:00:01 906intr_delay=10000000 907pci_bus=0 908pci_dev=1 909pci_func=0 910pio_latency=30000 911platform=system.tsunami 912rss=false --- 7 unchanged lines hidden (view full) --- 920tx_thread=false 921config=system.iobus.master[28] 922dma=system.iobus.slave[2] 923pio=system.iobus.master[27] 924 925[system.tsunami.fake_OROM] 926type=IsaFake 927clk_domain=system.clk_domain |
928eventq_index=0 |
|
807fake_mem=false 808pio_addr=8796093677568 809pio_latency=100000 810pio_size=393216 811ret_bad_addr=false 812ret_data16=65535 813ret_data32=4294967295 814ret_data64=18446744073709551615 815ret_data8=255 816system=system 817update_data=false 818warn_access= 819pio=system.iobus.master[8] 820 821[system.tsunami.fake_ata0] 822type=IsaFake 823clk_domain=system.clk_domain | 929fake_mem=false 930pio_addr=8796093677568 931pio_latency=100000 932pio_size=393216 933ret_bad_addr=false 934ret_data16=65535 935ret_data32=4294967295 936ret_data64=18446744073709551615 937ret_data8=255 938system=system 939update_data=false 940warn_access= 941pio=system.iobus.master[8] 942 943[system.tsunami.fake_ata0] 944type=IsaFake 945clk_domain=system.clk_domain |
946eventq_index=0 |
|
824fake_mem=false 825pio_addr=8804615848432 826pio_latency=100000 827pio_size=8 828ret_bad_addr=false 829ret_data16=65535 830ret_data32=4294967295 831ret_data64=18446744073709551615 832ret_data8=255 833system=system 834update_data=false 835warn_access= 836pio=system.iobus.master[19] 837 838[system.tsunami.fake_ata1] 839type=IsaFake 840clk_domain=system.clk_domain | 947fake_mem=false 948pio_addr=8804615848432 949pio_latency=100000 950pio_size=8 951ret_bad_addr=false 952ret_data16=65535 953ret_data32=4294967295 954ret_data64=18446744073709551615 955ret_data8=255 956system=system 957update_data=false 958warn_access= 959pio=system.iobus.master[19] 960 961[system.tsunami.fake_ata1] 962type=IsaFake 963clk_domain=system.clk_domain |
964eventq_index=0 |
|
841fake_mem=false 842pio_addr=8804615848304 843pio_latency=100000 844pio_size=8 845ret_bad_addr=false 846ret_data16=65535 847ret_data32=4294967295 848ret_data64=18446744073709551615 849ret_data8=255 850system=system 851update_data=false 852warn_access= 853pio=system.iobus.master[20] 854 855[system.tsunami.fake_pnp_addr] 856type=IsaFake 857clk_domain=system.clk_domain | 965fake_mem=false 966pio_addr=8804615848304 967pio_latency=100000 968pio_size=8 969ret_bad_addr=false 970ret_data16=65535 971ret_data32=4294967295 972ret_data64=18446744073709551615 973ret_data8=255 974system=system 975update_data=false 976warn_access= 977pio=system.iobus.master[20] 978 979[system.tsunami.fake_pnp_addr] 980type=IsaFake 981clk_domain=system.clk_domain |
982eventq_index=0 |
|
858fake_mem=false 859pio_addr=8804615848569 860pio_latency=100000 861pio_size=8 862ret_bad_addr=false 863ret_data16=65535 864ret_data32=4294967295 865ret_data64=18446744073709551615 866ret_data8=255 867system=system 868update_data=false 869warn_access= 870pio=system.iobus.master[9] 871 872[system.tsunami.fake_pnp_read0] 873type=IsaFake 874clk_domain=system.clk_domain | 983fake_mem=false 984pio_addr=8804615848569 985pio_latency=100000 986pio_size=8 987ret_bad_addr=false 988ret_data16=65535 989ret_data32=4294967295 990ret_data64=18446744073709551615 991ret_data8=255 992system=system 993update_data=false 994warn_access= 995pio=system.iobus.master[9] 996 997[system.tsunami.fake_pnp_read0] 998type=IsaFake 999clk_domain=system.clk_domain |
1000eventq_index=0 |
|
875fake_mem=false 876pio_addr=8804615848451 877pio_latency=100000 878pio_size=8 879ret_bad_addr=false 880ret_data16=65535 881ret_data32=4294967295 882ret_data64=18446744073709551615 883ret_data8=255 884system=system 885update_data=false 886warn_access= 887pio=system.iobus.master[11] 888 889[system.tsunami.fake_pnp_read1] 890type=IsaFake 891clk_domain=system.clk_domain | 1001fake_mem=false 1002pio_addr=8804615848451 1003pio_latency=100000 1004pio_size=8 1005ret_bad_addr=false 1006ret_data16=65535 1007ret_data32=4294967295 1008ret_data64=18446744073709551615 1009ret_data8=255 1010system=system 1011update_data=false 1012warn_access= 1013pio=system.iobus.master[11] 1014 1015[system.tsunami.fake_pnp_read1] 1016type=IsaFake 1017clk_domain=system.clk_domain |
1018eventq_index=0 |
|
892fake_mem=false 893pio_addr=8804615848515 894pio_latency=100000 895pio_size=8 896ret_bad_addr=false 897ret_data16=65535 898ret_data32=4294967295 899ret_data64=18446744073709551615 900ret_data8=255 901system=system 902update_data=false 903warn_access= 904pio=system.iobus.master[12] 905 906[system.tsunami.fake_pnp_read2] 907type=IsaFake 908clk_domain=system.clk_domain | 1019fake_mem=false 1020pio_addr=8804615848515 1021pio_latency=100000 1022pio_size=8 1023ret_bad_addr=false 1024ret_data16=65535 1025ret_data32=4294967295 1026ret_data64=18446744073709551615 1027ret_data8=255 1028system=system 1029update_data=false 1030warn_access= 1031pio=system.iobus.master[12] 1032 1033[system.tsunami.fake_pnp_read2] 1034type=IsaFake 1035clk_domain=system.clk_domain |
1036eventq_index=0 |
|
909fake_mem=false 910pio_addr=8804615848579 911pio_latency=100000 912pio_size=8 913ret_bad_addr=false 914ret_data16=65535 915ret_data32=4294967295 916ret_data64=18446744073709551615 917ret_data8=255 918system=system 919update_data=false 920warn_access= 921pio=system.iobus.master[13] 922 923[system.tsunami.fake_pnp_read3] 924type=IsaFake 925clk_domain=system.clk_domain | 1037fake_mem=false 1038pio_addr=8804615848579 1039pio_latency=100000 1040pio_size=8 1041ret_bad_addr=false 1042ret_data16=65535 1043ret_data32=4294967295 1044ret_data64=18446744073709551615 1045ret_data8=255 1046system=system 1047update_data=false 1048warn_access= 1049pio=system.iobus.master[13] 1050 1051[system.tsunami.fake_pnp_read3] 1052type=IsaFake 1053clk_domain=system.clk_domain |
1054eventq_index=0 |
|
926fake_mem=false 927pio_addr=8804615848643 928pio_latency=100000 929pio_size=8 930ret_bad_addr=false 931ret_data16=65535 932ret_data32=4294967295 933ret_data64=18446744073709551615 934ret_data8=255 935system=system 936update_data=false 937warn_access= 938pio=system.iobus.master[14] 939 940[system.tsunami.fake_pnp_read4] 941type=IsaFake 942clk_domain=system.clk_domain | 1055fake_mem=false 1056pio_addr=8804615848643 1057pio_latency=100000 1058pio_size=8 1059ret_bad_addr=false 1060ret_data16=65535 1061ret_data32=4294967295 1062ret_data64=18446744073709551615 1063ret_data8=255 1064system=system 1065update_data=false 1066warn_access= 1067pio=system.iobus.master[14] 1068 1069[system.tsunami.fake_pnp_read4] 1070type=IsaFake 1071clk_domain=system.clk_domain |
1072eventq_index=0 |
|
943fake_mem=false 944pio_addr=8804615848707 945pio_latency=100000 946pio_size=8 947ret_bad_addr=false 948ret_data16=65535 949ret_data32=4294967295 950ret_data64=18446744073709551615 951ret_data8=255 952system=system 953update_data=false 954warn_access= 955pio=system.iobus.master[15] 956 957[system.tsunami.fake_pnp_read5] 958type=IsaFake 959clk_domain=system.clk_domain | 1073fake_mem=false 1074pio_addr=8804615848707 1075pio_latency=100000 1076pio_size=8 1077ret_bad_addr=false 1078ret_data16=65535 1079ret_data32=4294967295 1080ret_data64=18446744073709551615 1081ret_data8=255 1082system=system 1083update_data=false 1084warn_access= 1085pio=system.iobus.master[15] 1086 1087[system.tsunami.fake_pnp_read5] 1088type=IsaFake 1089clk_domain=system.clk_domain |
1090eventq_index=0 |
|
960fake_mem=false 961pio_addr=8804615848771 962pio_latency=100000 963pio_size=8 964ret_bad_addr=false 965ret_data16=65535 966ret_data32=4294967295 967ret_data64=18446744073709551615 968ret_data8=255 969system=system 970update_data=false 971warn_access= 972pio=system.iobus.master[16] 973 974[system.tsunami.fake_pnp_read6] 975type=IsaFake 976clk_domain=system.clk_domain | 1091fake_mem=false 1092pio_addr=8804615848771 1093pio_latency=100000 1094pio_size=8 1095ret_bad_addr=false 1096ret_data16=65535 1097ret_data32=4294967295 1098ret_data64=18446744073709551615 1099ret_data8=255 1100system=system 1101update_data=false 1102warn_access= 1103pio=system.iobus.master[16] 1104 1105[system.tsunami.fake_pnp_read6] 1106type=IsaFake 1107clk_domain=system.clk_domain |
1108eventq_index=0 |
|
977fake_mem=false 978pio_addr=8804615848835 979pio_latency=100000 980pio_size=8 981ret_bad_addr=false 982ret_data16=65535 983ret_data32=4294967295 984ret_data64=18446744073709551615 985ret_data8=255 986system=system 987update_data=false 988warn_access= 989pio=system.iobus.master[17] 990 991[system.tsunami.fake_pnp_read7] 992type=IsaFake 993clk_domain=system.clk_domain | 1109fake_mem=false 1110pio_addr=8804615848835 1111pio_latency=100000 1112pio_size=8 1113ret_bad_addr=false 1114ret_data16=65535 1115ret_data32=4294967295 1116ret_data64=18446744073709551615 1117ret_data8=255 1118system=system 1119update_data=false 1120warn_access= 1121pio=system.iobus.master[17] 1122 1123[system.tsunami.fake_pnp_read7] 1124type=IsaFake 1125clk_domain=system.clk_domain |
1126eventq_index=0 |
|
994fake_mem=false 995pio_addr=8804615848899 996pio_latency=100000 997pio_size=8 998ret_bad_addr=false 999ret_data16=65535 1000ret_data32=4294967295 1001ret_data64=18446744073709551615 1002ret_data8=255 1003system=system 1004update_data=false 1005warn_access= 1006pio=system.iobus.master[18] 1007 1008[system.tsunami.fake_pnp_write] 1009type=IsaFake 1010clk_domain=system.clk_domain | 1127fake_mem=false 1128pio_addr=8804615848899 1129pio_latency=100000 1130pio_size=8 1131ret_bad_addr=false 1132ret_data16=65535 1133ret_data32=4294967295 1134ret_data64=18446744073709551615 1135ret_data8=255 1136system=system 1137update_data=false 1138warn_access= 1139pio=system.iobus.master[18] 1140 1141[system.tsunami.fake_pnp_write] 1142type=IsaFake 1143clk_domain=system.clk_domain |
1144eventq_index=0 |
|
1011fake_mem=false 1012pio_addr=8804615850617 1013pio_latency=100000 1014pio_size=8 1015ret_bad_addr=false 1016ret_data16=65535 1017ret_data32=4294967295 1018ret_data64=18446744073709551615 1019ret_data8=255 1020system=system 1021update_data=false 1022warn_access= 1023pio=system.iobus.master[10] 1024 1025[system.tsunami.fake_ppc] 1026type=IsaFake 1027clk_domain=system.clk_domain | 1145fake_mem=false 1146pio_addr=8804615850617 1147pio_latency=100000 1148pio_size=8 1149ret_bad_addr=false 1150ret_data16=65535 1151ret_data32=4294967295 1152ret_data64=18446744073709551615 1153ret_data8=255 1154system=system 1155update_data=false 1156warn_access= 1157pio=system.iobus.master[10] 1158 1159[system.tsunami.fake_ppc] 1160type=IsaFake 1161clk_domain=system.clk_domain |
1162eventq_index=0 |
|
1028fake_mem=false 1029pio_addr=8804615848891 1030pio_latency=100000 1031pio_size=8 1032ret_bad_addr=false 1033ret_data16=65535 1034ret_data32=4294967295 1035ret_data64=18446744073709551615 1036ret_data8=255 1037system=system 1038update_data=false 1039warn_access= 1040pio=system.iobus.master[7] 1041 1042[system.tsunami.fake_sm_chip] 1043type=IsaFake 1044clk_domain=system.clk_domain | 1163fake_mem=false 1164pio_addr=8804615848891 1165pio_latency=100000 1166pio_size=8 1167ret_bad_addr=false 1168ret_data16=65535 1169ret_data32=4294967295 1170ret_data64=18446744073709551615 1171ret_data8=255 1172system=system 1173update_data=false 1174warn_access= 1175pio=system.iobus.master[7] 1176 1177[system.tsunami.fake_sm_chip] 1178type=IsaFake 1179clk_domain=system.clk_domain |
1180eventq_index=0 |
|
1045fake_mem=false 1046pio_addr=8804615848816 1047pio_latency=100000 1048pio_size=8 1049ret_bad_addr=false 1050ret_data16=65535 1051ret_data32=4294967295 1052ret_data64=18446744073709551615 1053ret_data8=255 1054system=system 1055update_data=false 1056warn_access= 1057pio=system.iobus.master[2] 1058 1059[system.tsunami.fake_uart1] 1060type=IsaFake 1061clk_domain=system.clk_domain | 1181fake_mem=false 1182pio_addr=8804615848816 1183pio_latency=100000 1184pio_size=8 1185ret_bad_addr=false 1186ret_data16=65535 1187ret_data32=4294967295 1188ret_data64=18446744073709551615 1189ret_data8=255 1190system=system 1191update_data=false 1192warn_access= 1193pio=system.iobus.master[2] 1194 1195[system.tsunami.fake_uart1] 1196type=IsaFake 1197clk_domain=system.clk_domain |
1198eventq_index=0 |
|
1062fake_mem=false 1063pio_addr=8804615848696 1064pio_latency=100000 1065pio_size=8 1066ret_bad_addr=false 1067ret_data16=65535 1068ret_data32=4294967295 1069ret_data64=18446744073709551615 1070ret_data8=255 1071system=system 1072update_data=false 1073warn_access= 1074pio=system.iobus.master[3] 1075 1076[system.tsunami.fake_uart2] 1077type=IsaFake 1078clk_domain=system.clk_domain | 1199fake_mem=false 1200pio_addr=8804615848696 1201pio_latency=100000 1202pio_size=8 1203ret_bad_addr=false 1204ret_data16=65535 1205ret_data32=4294967295 1206ret_data64=18446744073709551615 1207ret_data8=255 1208system=system 1209update_data=false 1210warn_access= 1211pio=system.iobus.master[3] 1212 1213[system.tsunami.fake_uart2] 1214type=IsaFake 1215clk_domain=system.clk_domain |
1216eventq_index=0 |
|
1079fake_mem=false 1080pio_addr=8804615848936 1081pio_latency=100000 1082pio_size=8 1083ret_bad_addr=false 1084ret_data16=65535 1085ret_data32=4294967295 1086ret_data64=18446744073709551615 1087ret_data8=255 1088system=system 1089update_data=false 1090warn_access= 1091pio=system.iobus.master[4] 1092 1093[system.tsunami.fake_uart3] 1094type=IsaFake 1095clk_domain=system.clk_domain | 1217fake_mem=false 1218pio_addr=8804615848936 1219pio_latency=100000 1220pio_size=8 1221ret_bad_addr=false 1222ret_data16=65535 1223ret_data32=4294967295 1224ret_data64=18446744073709551615 1225ret_data8=255 1226system=system 1227update_data=false 1228warn_access= 1229pio=system.iobus.master[4] 1230 1231[system.tsunami.fake_uart3] 1232type=IsaFake 1233clk_domain=system.clk_domain |
1234eventq_index=0 |
|
1096fake_mem=false 1097pio_addr=8804615848680 1098pio_latency=100000 1099pio_size=8 1100ret_bad_addr=false 1101ret_data16=65535 1102ret_data32=4294967295 1103ret_data64=18446744073709551615 1104ret_data8=255 1105system=system 1106update_data=false 1107warn_access= 1108pio=system.iobus.master[5] 1109 1110[system.tsunami.fake_uart4] 1111type=IsaFake 1112clk_domain=system.clk_domain | 1235fake_mem=false 1236pio_addr=8804615848680 1237pio_latency=100000 1238pio_size=8 1239ret_bad_addr=false 1240ret_data16=65535 1241ret_data32=4294967295 1242ret_data64=18446744073709551615 1243ret_data8=255 1244system=system 1245update_data=false 1246warn_access= 1247pio=system.iobus.master[5] 1248 1249[system.tsunami.fake_uart4] 1250type=IsaFake 1251clk_domain=system.clk_domain |
1252eventq_index=0 |
|
1113fake_mem=false 1114pio_addr=8804615848944 1115pio_latency=100000 1116pio_size=8 1117ret_bad_addr=false 1118ret_data16=65535 1119ret_data32=4294967295 1120ret_data64=18446744073709551615 1121ret_data8=255 1122system=system 1123update_data=false 1124warn_access= 1125pio=system.iobus.master[6] 1126 1127[system.tsunami.fb] 1128type=BadDevice 1129clk_domain=system.clk_domain 1130devicename=FrameBuffer | 1253fake_mem=false 1254pio_addr=8804615848944 1255pio_latency=100000 1256pio_size=8 1257ret_bad_addr=false 1258ret_data16=65535 1259ret_data32=4294967295 1260ret_data64=18446744073709551615 1261ret_data8=255 1262system=system 1263update_data=false 1264warn_access= 1265pio=system.iobus.master[6] 1266 1267[system.tsunami.fb] 1268type=BadDevice 1269clk_domain=system.clk_domain 1270devicename=FrameBuffer |
1271eventq_index=0 |
|
1131pio_addr=8804615848912 1132pio_latency=100000 1133system=system 1134pio=system.iobus.master[21] 1135 1136[system.tsunami.ide] 1137type=IdeController 1138BAR0=1 --- 11 unchanged lines hidden (view full) --- 1150BAR4=1 1151BAR4LegacyIO=false 1152BAR4Size=16 1153BAR5=1 1154BAR5LegacyIO=false 1155BAR5Size=0 1156BIST=0 1157CacheLineSize=0 | 1272pio_addr=8804615848912 1273pio_latency=100000 1274system=system 1275pio=system.iobus.master[21] 1276 1277[system.tsunami.ide] 1278type=IdeController 1279BAR0=1 --- 11 unchanged lines hidden (view full) --- 1291BAR4=1 1292BAR4LegacyIO=false 1293BAR4Size=16 1294BAR5=1 1295BAR5LegacyIO=false 1296BAR5Size=0 1297BIST=0 1298CacheLineSize=0 |
1299CapabilityPtr=0 |
|
1158CardbusCIS=0 1159ClassCode=1 1160Command=0 1161DeviceID=28945 1162ExpansionROM=0 1163HeaderType=0 1164InterruptLine=31 1165InterruptPin=1 1166LatencyTimer=0 | 1300CardbusCIS=0 1301ClassCode=1 1302Command=0 1303DeviceID=28945 1304ExpansionROM=0 1305HeaderType=0 1306InterruptLine=31 1307InterruptPin=1 1308LatencyTimer=0 |
1309MSICAPBaseOffset=0 1310MSICAPCapId=0 1311MSICAPMaskBits=0 1312MSICAPMsgAddr=0 1313MSICAPMsgCtrl=0 1314MSICAPMsgData=0 1315MSICAPMsgUpperAddr=0 1316MSICAPNextCapability=0 1317MSICAPPendingBits=0 1318MSIXCAPBaseOffset=0 1319MSIXCAPCapId=0 1320MSIXCAPNextCapability=0 1321MSIXMsgCtrl=0 1322MSIXPbaOffset=0 1323MSIXTableOffset=0 |
|
1167MaximumLatency=0 1168MinimumGrant=0 | 1324MaximumLatency=0 1325MinimumGrant=0 |
1326PMCAPBaseOffset=0 1327PMCAPCapId=0 1328PMCAPCapabilities=0 1329PMCAPCtrlStatus=0 1330PMCAPNextCapability=0 1331PXCAPBaseOffset=0 1332PXCAPCapId=0 1333PXCAPCapabilities=0 1334PXCAPDevCap2=0 1335PXCAPDevCapabilities=0 1336PXCAPDevCtrl=0 1337PXCAPDevCtrl2=0 1338PXCAPDevStatus=0 1339PXCAPLinkCap=0 1340PXCAPLinkCtrl=0 1341PXCAPLinkStatus=0 1342PXCAPNextCapability=0 |
|
1169ProgIF=133 1170Revision=0 1171Status=640 1172SubClassCode=1 1173SubsystemID=0 1174SubsystemVendorID=0 1175VendorID=32902 1176clk_domain=system.clk_domain 1177config_latency=20000 1178ctrl_offset=0 1179disks=system.disk0 system.disk2 | 1343ProgIF=133 1344Revision=0 1345Status=640 1346SubClassCode=1 1347SubsystemID=0 1348SubsystemVendorID=0 1349VendorID=32902 1350clk_domain=system.clk_domain 1351config_latency=20000 1352ctrl_offset=0 1353disks=system.disk0 system.disk2 |
1354eventq_index=0 |
|
1180io_shift=0 1181pci_bus=0 1182pci_dev=0 1183pci_func=0 1184pio_latency=30000 1185platform=system.tsunami 1186system=system 1187config=system.iobus.master[26] 1188dma=system.iobus.slave[1] 1189pio=system.iobus.master[25] 1190 1191[system.tsunami.io] 1192type=TsunamiIO 1193clk_domain=system.clk_domain | 1355io_shift=0 1356pci_bus=0 1357pci_dev=0 1358pci_func=0 1359pio_latency=30000 1360platform=system.tsunami 1361system=system 1362config=system.iobus.master[26] 1363dma=system.iobus.slave[1] 1364pio=system.iobus.master[25] 1365 1366[system.tsunami.io] 1367type=TsunamiIO 1368clk_domain=system.clk_domain |
1369eventq_index=0 |
|
1194frequency=976562500 1195pio_addr=8804615847936 1196pio_latency=100000 1197system=system 1198time=Thu Jan 1 00:00:00 2009 1199tsunami=system.tsunami 1200year_is_bcd=false 1201pio=system.iobus.master[22] 1202 1203[system.tsunami.pchip] 1204type=TsunamiPChip 1205clk_domain=system.clk_domain | 1370frequency=976562500 1371pio_addr=8804615847936 1372pio_latency=100000 1373system=system 1374time=Thu Jan 1 00:00:00 2009 1375tsunami=system.tsunami 1376year_is_bcd=false 1377pio=system.iobus.master[22] 1378 1379[system.tsunami.pchip] 1380type=TsunamiPChip 1381clk_domain=system.clk_domain |
1382eventq_index=0 |
|
1206pio_addr=8802535473152 1207pio_latency=100000 1208system=system 1209tsunami=system.tsunami 1210pio=system.iobus.master[1] 1211 1212[system.tsunami.pciconfig] 1213type=PciConfigAll 1214bus=0 1215clk_domain=system.clk_domain | 1383pio_addr=8802535473152 1384pio_latency=100000 1385system=system 1386tsunami=system.tsunami 1387pio=system.iobus.master[1] 1388 1389[system.tsunami.pciconfig] 1390type=PciConfigAll 1391bus=0 1392clk_domain=system.clk_domain |
1393eventq_index=0 |
|
1216pio_addr=0 1217pio_latency=30000 1218platform=system.tsunami 1219size=16777216 1220system=system 1221pio=system.iobus.default 1222 1223[system.tsunami.uart] 1224type=Uart8250 1225clk_domain=system.clk_domain | 1394pio_addr=0 1395pio_latency=30000 1396platform=system.tsunami 1397size=16777216 1398system=system 1399pio=system.iobus.default 1400 1401[system.tsunami.uart] 1402type=Uart8250 1403clk_domain=system.clk_domain |
1404eventq_index=0 |
|
1226pio_addr=8804615848952 1227pio_latency=100000 1228platform=system.tsunami 1229system=system 1230terminal=system.terminal 1231pio=system.iobus.master[23] 1232 1233[system.voltage_domain] 1234type=VoltageDomain | 1405pio_addr=8804615848952 1406pio_latency=100000 1407platform=system.tsunami 1408system=system 1409terminal=system.terminal 1410pio=system.iobus.master[23] 1411 1412[system.voltage_domain] 1413type=VoltageDomain |
1414eventq_index=0 |
|
1235voltage=1.000000 1236 | 1415voltage=1.000000 1416 |