simple-timing.py (9288:3d6da8559605) simple-timing.py (9321:7f0464326b2b)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 14 unchanged lines hidden (view full) ---

23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from Caches import *
31
33
32class MyCache(BaseCache):
33 assoc = 2
34 block_size = 64
35 hit_latency = 2
36 response_latency = 2
37 mshrs = 10
38 tgts_per_mshr = 5
39
40class MyL1Cache(MyCache):
41 is_top_level = True
42
43cpu = TimingSimpleCPU(cpu_id=0)
34cpu = TimingSimpleCPU(cpu_id=0)
44cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
45 MyL1Cache(size = '256kB'),
46 MyCache(size = '2MB', hit_latency= 20,
47 response_latency = 20))
35cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
36 L1Cache(size = '256kB'),
37 L2Cache(size = '2MB'))
48system = System(cpu = cpu,
49 physmem = SimpleMemory(),
50 membus = CoherentBus())
51system.system_port = system.membus.slave
52system.physmem.port = system.membus.master
53# create the interrupt controller
54cpu.createInterruptController()
55cpu.connectAllPorts(system.membus)
56cpu.clock = '2GHz'
57
58root = Root(full_system=False, system = system)
38system = System(cpu = cpu,
39 physmem = SimpleMemory(),
40 membus = CoherentBus())
41system.system_port = system.membus.slave
42system.physmem.port = system.membus.master
43# create the interrupt controller
44cpu.createInterruptController()
45cpu.connectAllPorts(system.membus)
46cpu.clock = '2GHz'
47
48root = Root(full_system=False, system = system)