simple-timing.py (9263:066099902102) simple-timing.py (9288:3d6da8559605)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31
32class MyCache(BaseCache):
33 assoc = 2
34 block_size = 64
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 18 unchanged lines hidden (view full) ---

27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31
32class MyCache(BaseCache):
33 assoc = 2
34 block_size = 64
35 hit_latency = '1ns'
36 response_latency = '1ns'
35 hit_latency = 2
36 response_latency = 2
37 mshrs = 10
38 tgts_per_mshr = 5
39
40class MyL1Cache(MyCache):
41 is_top_level = True
42
43cpu = TimingSimpleCPU(cpu_id=0)
44cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
45 MyL1Cache(size = '256kB'),
37 mshrs = 10
38 tgts_per_mshr = 5
39
40class MyL1Cache(MyCache):
41 is_top_level = True
42
43cpu = TimingSimpleCPU(cpu_id=0)
44cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
45 MyL1Cache(size = '256kB'),
46 MyCache(size = '2MB', hit_latency='10ns', response_latency ='10ns'))
46 MyCache(size = '2MB', hit_latency= 20,
47 response_latency = 20))
47system = System(cpu = cpu,
48 physmem = SimpleMemory(),
49 membus = CoherentBus())
50system.system_port = system.membus.slave
51system.physmem.port = system.membus.master
52# create the interrupt controller
53cpu.createInterruptController()
54cpu.connectAllPorts(system.membus)
55cpu.clock = '2GHz'
56
57root = Root(full_system=False, system = system)
48system = System(cpu = cpu,
49 physmem = SimpleMemory(),
50 membus = CoherentBus())
51system.system_port = system.membus.slave
52system.physmem.port = system.membus.master
53# create the interrupt controller
54cpu.createInterruptController()
55cpu.connectAllPorts(system.membus)
56cpu.clock = '2GHz'
57
58root = Root(full_system=False, system = system)