| simple-timing.py (8931:7a1dfb191e3f) | simple-timing.py (9036:6385cf85bf12) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 31 unchanged lines hidden (view full) --- 40 is_top_level = True 41 42cpu = TimingSimpleCPU(cpu_id=0) 43cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), 44 MyL1Cache(size = '256kB'), 45 MyCache(size = '2MB', latency='10ns')) 46system = System(cpu = cpu, 47 physmem = SimpleMemory(), | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 31 unchanged lines hidden (view full) --- 40 is_top_level = True 41 42cpu = TimingSimpleCPU(cpu_id=0) 43cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), 44 MyL1Cache(size = '256kB'), 45 MyCache(size = '2MB', latency='10ns')) 46system = System(cpu = cpu, 47 physmem = SimpleMemory(), |
| 48 membus = Bus()) | 48 membus = CoherentBus()) |
| 49system.system_port = system.membus.slave 50system.physmem.port = system.membus.master 51# create the interrupt controller 52cpu.createInterruptController() 53cpu.connectAllPorts(system.membus) 54cpu.clock = '2GHz' 55 56root = Root(full_system=False, system = system) | 49system.system_port = system.membus.slave 50system.physmem.port = system.membus.master 51# create the interrupt controller 52cpu.createInterruptController() 53cpu.connectAllPorts(system.membus) 54cpu.clock = '2GHz' 55 56root = Root(full_system=False, system = system) |