simple-timing.py (7876:189b9b258779) | simple-timing.py (8134:b01a51ff05fa) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 22 unchanged lines hidden (view full) --- 31 32class MyCache(BaseCache): 33 assoc = 2 34 block_size = 64 35 latency = '1ns' 36 mshrs = 10 37 tgts_per_mshr = 5 38 | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 22 unchanged lines hidden (view full) --- 31 32class MyCache(BaseCache): 33 assoc = 2 34 block_size = 64 35 latency = '1ns' 36 mshrs = 10 37 tgts_per_mshr = 5 38 |
39class MyL1Cache(MyCache): 40 is_top_level = True 41 |
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39cpu = TimingSimpleCPU(cpu_id=0) | 42cpu = TimingSimpleCPU(cpu_id=0) |
40cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), | 43cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), 44 MyL1Cache(size = '256kB'), |
41 MyCache(size = '2MB', latency='10ns')) 42system = System(cpu = cpu, 43 physmem = PhysicalMemory(), 44 membus = Bus()) 45system.physmem.port = system.membus.port 46cpu.connectAllPorts(system.membus) 47cpu.clock = '2GHz' 48 49root = Root(system = system) | 45 MyCache(size = '2MB', latency='10ns')) 46system = System(cpu = cpu, 47 physmem = PhysicalMemory(), 48 membus = Bus()) 49system.physmem.port = system.membus.port 50cpu.connectAllPorts(system.membus) 51cpu.clock = '2GHz' 52 53root = Root(system = system) |