| simple-timing.py (4444:0648bdc8d1c9) | simple-timing.py (7876:189b9b258779) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 29 unchanged lines hidden (view full) --- 38 39cpu = TimingSimpleCPU(cpu_id=0) 40cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), 41 MyCache(size = '2MB', latency='10ns')) 42system = System(cpu = cpu, 43 physmem = PhysicalMemory(), 44 membus = Bus()) 45system.physmem.port = system.membus.port | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 29 unchanged lines hidden (view full) --- 38 39cpu = TimingSimpleCPU(cpu_id=0) 40cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), 41 MyCache(size = '2MB', latency='10ns')) 42system = System(cpu = cpu, 43 physmem = PhysicalMemory(), 44 membus = Bus()) 45system.physmem.port = system.membus.port |
| 46cpu.connectMemPorts(system.membus) | 46cpu.connectAllPorts(system.membus) |
| 47cpu.clock = '2GHz' 48 49root = Root(system = system) | 47cpu.clock = '2GHz' 48 49root = Root(system = system) |