simple-timing.py (3051:b4f73000973b) simple-timing.py (3170:37fd1e73f836)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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31
32class MyCache(BaseCache):
33 assoc = 2
34 block_size = 64
35 latency = 1
36 mshrs = 10
37 tgts_per_mshr = 5
38
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 22 unchanged lines hidden (view full) ---

31
32class MyCache(BaseCache):
33 assoc = 2
34 block_size = 64
35 latency = 1
36 mshrs = 10
37 tgts_per_mshr = 5
38
39cpu = TimingSimpleCPU()
39cpu = TimingSimpleCPU(cpu_id=0)
40cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
41 MyCache(size = '2MB'))
42cpu.mem = cpu.dcache
43cpu.mem = cpu.dcache
44system = System(cpu = cpu,
45 physmem = PhysicalMemory(),
46 membus = Bus())
47system.physmem.port = system.membus.port
48cpu.connectMemPorts(system.membus)
49
50root = Root(system = system)
40cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
41 MyCache(size = '2MB'))
42cpu.mem = cpu.dcache
43cpu.mem = cpu.dcache
44system = System(cpu = cpu,
45 physmem = PhysicalMemory(),
46 membus = Bus())
47system.physmem.port = system.membus.port
48cpu.connectMemPorts(system.membus)
49
50root = Root(system = system)