simple-timing.py (3005:ceb86e85d62d) simple-timing.py (3017:972510aadad0)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 25 unchanged lines hidden (view full) ---

34 block_size = 64
35 latency = 1
36 mshrs = 10
37 tgts_per_mshr = 5
38
39cpu = TimingSimpleCPU()
40cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
41 MyCache(size = '2MB'))
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 25 unchanged lines hidden (view full) ---

34 block_size = 64
35 latency = 1
36 mshrs = 10
37 tgts_per_mshr = 5
38
39cpu = TimingSimpleCPU()
40cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
41 MyCache(size = '2MB'))
42
42cpu.mem = cpu.dcache
43system = System(cpu = cpu,
44 physmem = PhysicalMemory(),
45 membus = Bus())
46system.physmem.port = system.membus.port
47cpu.connectMemPorts(system.membus)
48
49root = Root(system = system)
43system = System(cpu = cpu,
44 physmem = PhysicalMemory(),
45 membus = Bus())
46system.physmem.port = system.membus.port
47cpu.connectMemPorts(system.membus)
48
49root = Root(system = system)