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> # Copyright (c) 2013 ARM Limited
> # All rights reserved.
> #
> # The license below extends only to copyright in the software and shall
> # not be construed as granting a license to any other intellectual
> # property including but not limited to intellectual property relating
> # to a hardware implementation of the functionality of the software
> # licensed hereunder. You may use the software subject to the license
> # terms below provided that you ensure that this notice is replicated
> # unmodified and in its entirety in all distributions of the software,
> # modified or unmodified, in source code or in binary form.
> #
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< # Authors: Steve Reinhardt
---
> # Authors: Andreas Hansson
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< import m5
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< m5.util.addToPath('../configs/common')
< from Caches import *
---
> from base_config import *
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< cpu = TimingSimpleCPU(cpu_id=0)
< cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
< L1Cache(size = '256kB'),
< L2Cache(size = '2MB'))
< system = System(cpu = cpu,
< physmem = SimpleMemory(),
< membus = CoherentBus(),
< mem_mode = "timing")
< system.clock = '1GHz'
< system.system_port = system.membus.slave
< system.physmem.port = system.membus.master
< # create the interrupt controller
< cpu.createInterruptController()
< cpu.connectAllPorts(system.membus)
< cpu.clock = '2GHz'
<
< root = Root(full_system=False, system = system)
---
> root = BaseSESystemUniprocessor(mem_mode='timing',
> cpu_class=TimingSimpleCPU).create_root()