simple-timing.py (9381:ffec48040ac1) | simple-timing.py (9790:ccc428657233) |
---|---|
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 25 unchanged lines hidden (view full) --- 34cpu = TimingSimpleCPU(cpu_id=0) 35cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'), 36 L1Cache(size = '256kB'), 37 L2Cache(size = '2MB')) 38system = System(cpu = cpu, 39 physmem = SimpleMemory(), 40 membus = CoherentBus(), 41 mem_mode = "timing") | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 25 unchanged lines hidden (view full) --- 34cpu = TimingSimpleCPU(cpu_id=0) 35cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'), 36 L1Cache(size = '256kB'), 37 L2Cache(size = '2MB')) 38system = System(cpu = cpu, 39 physmem = SimpleMemory(), 40 membus = CoherentBus(), 41 mem_mode = "timing") |
42system.clock = '1GHz' |
|
42system.system_port = system.membus.slave 43system.physmem.port = system.membus.master 44# create the interrupt controller 45cpu.createInterruptController() 46cpu.connectAllPorts(system.membus) 47cpu.clock = '2GHz' 48 49root = Root(full_system=False, system = system) | 43system.system_port = system.membus.slave 44system.physmem.port = system.membus.master 45# create the interrupt controller 46cpu.createInterruptController() 47cpu.connectAllPorts(system.membus) 48cpu.clock = '2GHz' 49 50root = Root(full_system=False, system = system) |