1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from Caches import *
33
34cpu = TimingSimpleCPU(cpu_id=0)
35cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
36 L1Cache(size = '256kB'),
37 L2Cache(size = '2MB'))
38system = System(cpu = cpu,
39 physmem = SimpleMemory(),
40 membus = CoherentBus(),
41 mem_mode = "timing")
42system.clock = '1GHz'
43system.system_port = system.membus.slave
44system.physmem.port = system.membus.master
45# create the interrupt controller
46cpu.createInterruptController()
47cpu.connectAllPorts(system.membus)
48cpu.clock = '2GHz'
49
50root = Root(full_system=False, system = system)