1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31
32class MyCache(BaseCache):
33 assoc = 2
34 block_size = 64
35 latency = '1ns'
36 mshrs = 10
37 tgts_per_mshr = 5
38
39class MyL1Cache(MyCache):
40 is_top_level = True
41
42cpu = TimingSimpleCPU(cpu_id=0)
43cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
44 MyL1Cache(size = '256kB'),
45 MyCache(size = '2MB', latency='10ns'))
46system = System(cpu = cpu,
47 physmem = SimpleMemory(),
48 membus = CoherentBus())
49system.system_port = system.membus.slave
50system.physmem.port = system.membus.master
51# create the interrupt controller
52cpu.createInterruptController()
53cpu.connectAllPorts(system.membus)
54cpu.clock = '2GHz'
55
56root = Root(full_system=False, system = system)