simple-atomic-dummychecker.py (9790:ccc428657233) | simple-atomic-dummychecker.py (9792:c02004c2cc5b) |
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1# Copyright (c) 2011 ARM Limited 2# All rights reserved | 1# Copyright (c) 2013 ARM Limited 2# All rights reserved. |
3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, --- 17 unchanged lines hidden (view full) --- 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# | 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, --- 17 unchanged lines hidden (view full) --- 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# |
36# Authors: Geoffrey Blake | 36# Authors: Andreas Hansson |
37 | 37 |
38import m5 | |
39from m5.objects import * | 38from m5.objects import * |
39from base_config import * |
|
40 | 40 |
41system = System(cpu = AtomicSimpleCPU(cpu_id=0), 42 physmem = SimpleMemory(), 43 membus = CoherentBus()) 44system.clock = '1GHz' 45system.system_port = system.membus.slave 46system.physmem.port = system.membus.master 47system.cpu.addCheckerCpu() 48system.cpu.createInterruptController() 49system.cpu.connectAllPorts(system.membus) 50system.cpu.clock = '2GHz' 51 52root = Root(full_system = False, system = system) | 41root = BaseSESystemUniprocessor(mem_mode='atomic', 42 cpu_class=AtomicSimpleCPU, 43 checker=True).create_root() |