| simple-atomic-dummychecker.py (9036:6385cf85bf12) | simple-atomic-dummychecker.py (9790:ccc428657233) |
|---|---|
| 1# Copyright (c) 2011 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 27 unchanged lines hidden (view full) --- 36# Authors: Geoffrey Blake 37 38import m5 39from m5.objects import * 40 41system = System(cpu = AtomicSimpleCPU(cpu_id=0), 42 physmem = SimpleMemory(), 43 membus = CoherentBus()) | 1# Copyright (c) 2011 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 27 unchanged lines hidden (view full) --- 36# Authors: Geoffrey Blake 37 38import m5 39from m5.objects import * 40 41system = System(cpu = AtomicSimpleCPU(cpu_id=0), 42 physmem = SimpleMemory(), 43 membus = CoherentBus()) |
| 44system.clock = '1GHz' |
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| 44system.system_port = system.membus.slave 45system.physmem.port = system.membus.master 46system.cpu.addCheckerCpu() 47system.cpu.createInterruptController() 48system.cpu.connectAllPorts(system.membus) 49system.cpu.clock = '2GHz' 50 51root = Root(full_system = False, system = system) | 45system.system_port = system.membus.slave 46system.physmem.port = system.membus.master 47system.cpu.addCheckerCpu() 48system.cpu.createInterruptController() 49system.cpu.connectAllPorts(system.membus) 50system.cpu.clock = '2GHz' 51 52root = Root(full_system = False, system = system) |