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< # Copyright (c) 2011 ARM Limited
< # All rights reserved
---
> # Copyright (c) 2013 ARM Limited
> # All rights reserved.
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< # Authors: Geoffrey Blake
---
> # Authors: Andreas Hansson
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< import m5
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> from base_config import *
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< system = System(cpu = AtomicSimpleCPU(cpu_id=0),
< physmem = SimpleMemory(),
< membus = CoherentBus())
< system.clock = '1GHz'
< system.system_port = system.membus.slave
< system.physmem.port = system.membus.master
< system.cpu.addCheckerCpu()
< system.cpu.createInterruptController()
< system.cpu.connectAllPorts(system.membus)
< system.cpu.clock = '2GHz'
<
< root = Root(full_system = False, system = system)
---
> root = BaseSESystemUniprocessor(mem_mode='atomic',
> cpu_class=AtomicSimpleCPU,
> checker=True).create_root()