pc-simple-timing-ruby.py (9728:7daeab1685e9) pc-simple-timing-ruby.py (9793:6e6cefc1db1f)
1# Copyright (c) 2012 Mark D. Hill and David A. Wood
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 42 unchanged lines hidden (view full) ---

51options.l1d_assoc=2
52options.l1i_assoc=2
53options.l2_assoc=2
54options.num_cpus = 2
55
56#the system
57mdesc = SysConfig(disk = 'linux-x86.img')
58system = FSConfig.makeLinuxX86System('timing', DDR3_1600_x64, options.num_cpus,
1# Copyright (c) 2012 Mark D. Hill and David A. Wood
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 42 unchanged lines hidden (view full) ---

51options.l1d_assoc=2
52options.l1i_assoc=2
53options.l2_assoc=2
54options.num_cpus = 2
55
56#the system
57mdesc = SysConfig(disk = 'linux-x86.img')
58system = FSConfig.makeLinuxX86System('timing', DDR3_1600_x64, options.num_cpus,
59 mdesc=mdesc, Ruby=True)
59 mdesc=mdesc, Ruby=True,
60
60system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
61system.cpu = [TimingSimpleCPU(cpu_id=i) for i in xrange(options.num_cpus)]
61system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
62system.cpu = [TimingSimpleCPU(cpu_id=i) for i in xrange(options.num_cpus)]
63
62Ruby.create_system(options, system, system.piobus, system._dma_ports)
63
64Ruby.create_system(options, system, system.piobus, system._dma_ports)
65
66# Create a seperate clock domain for Ruby
67system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
68
64for (i, cpu) in enumerate(system.cpu):
65 # create the interrupt controller
66 cpu.createInterruptController()
67 # Tie the cpu ports to the correct ruby system ports
68 cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
69 cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
70 cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
71 cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
72 cpu.interrupts.pio = system.piobus.master
73 cpu.interrupts.int_master = system.piobus.slave
74 cpu.interrupts.int_slave = system.piobus.master
69for (i, cpu) in enumerate(system.cpu):
70 # create the interrupt controller
71 cpu.createInterruptController()
72 # Tie the cpu ports to the correct ruby system ports
73 cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
74 cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
75 cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
76 cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
77 cpu.interrupts.pio = system.piobus.master
78 cpu.interrupts.int_master = system.piobus.slave
79 cpu.interrupts.int_slave = system.piobus.master
75 cpu.clock = '2GHz'
76
77 # Set access_phys_mem to True for ruby port
78 system.ruby._cpu_ruby_ports[i].access_phys_mem = True
79
80root = Root(full_system = True, system = system)
81m5.ticks.setGlobalFrequency('1THz')
80
81 # Set access_phys_mem to True for ruby port
82 system.ruby._cpu_ruby_ports[i].access_phys_mem = True
83
84root = Root(full_system = True, system = system)
85m5.ticks.setGlobalFrequency('1THz')