pc-simple-timing-ruby.py (9123:281b3ac0e0a1) pc-simple-timing-ruby.py (9577:91cac7c9c636)
1# Copyright (c) 2012 Mark D. Hill and David A. Wood
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 60 unchanged lines hidden (view full) ---

69 cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
70 cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
71 cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
72 cpu.interrupts.pio = system.piobus.master
73 cpu.interrupts.int_master = system.piobus.slave
74 cpu.interrupts.int_slave = system.piobus.master
75 cpu.clock = '2GHz'
76
1# Copyright (c) 2012 Mark D. Hill and David A. Wood
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 60 unchanged lines hidden (view full) ---

69 cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
70 cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
71 cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
72 cpu.interrupts.pio = system.piobus.master
73 cpu.interrupts.int_master = system.piobus.slave
74 cpu.interrupts.int_slave = system.piobus.master
75 cpu.clock = '2GHz'
76
77 # Set access_phys_mem to True for ruby port
78 system.ruby._cpu_ruby_ports[i].access_phys_mem = True
79
77root = Root(full_system = True, system = system)
78m5.ticks.setGlobalFrequency('1THz')
80root = Root(full_system = True, system = system)
81m5.ticks.setGlobalFrequency('1THz')