pc-simple-timing-ruby.py (10519:7a3ad4b09ce4) | pc-simple-timing-ruby.py (10524:fff17530cef6) |
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1# Copyright (c) 2012 Mark D. Hill and David A. Wood 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 77 unchanged lines hidden (view full) --- 86 cpu.dcache_port = system.ruby._cpu_ports[i].slave 87 cpu.itb.walker.port = system.ruby._cpu_ports[i].slave 88 cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave 89 90 cpu.interrupts.pio = system.ruby._cpu_ports[i].master 91 cpu.interrupts.int_master = system.ruby._cpu_ports[i].slave 92 cpu.interrupts.int_slave = system.ruby._cpu_ports[i].master 93 | 1# Copyright (c) 2012 Mark D. Hill and David A. Wood 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 77 unchanged lines hidden (view full) --- 86 cpu.dcache_port = system.ruby._cpu_ports[i].slave 87 cpu.itb.walker.port = system.ruby._cpu_ports[i].slave 88 cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave 89 90 cpu.interrupts.pio = system.ruby._cpu_ports[i].master 91 cpu.interrupts.int_master = system.ruby._cpu_ports[i].slave 92 cpu.interrupts.int_slave = system.ruby._cpu_ports[i].master 93 |
94system.physmem = [SimpleMemory(range = r, null = True) 95 for r in system.mem_ranges] 96 | |
97root = Root(full_system = True, system = system) 98m5.ticks.setGlobalFrequency('1THz') | 94root = Root(full_system = True, system = system) 95m5.ticks.setGlobalFrequency('1THz') |