pc-simple-timing-ruby.py (10090:4eec7bdde5b0) pc-simple-timing-ruby.py (10118:5e1f04b4d5e4)
1# Copyright (c) 2012 Mark D. Hill and David A. Wood
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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63system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
64system.clk_domain = SrcClockDomain(clock = '1GHz',
65 voltage_domain = system.voltage_domain)
66system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
67 voltage_domain = system.voltage_domain)
68system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain)
69 for i in xrange(options.num_cpus)]
70
1# Copyright (c) 2012 Mark D. Hill and David A. Wood
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 54 unchanged lines hidden (view full) ---

63system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
64system.clk_domain = SrcClockDomain(clock = '1GHz',
65 voltage_domain = system.voltage_domain)
66system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
67 voltage_domain = system.voltage_domain)
68system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain)
69 for i in xrange(options.num_cpus)]
70
71Ruby.create_system(options, system, system.piobus, system._dma_ports)
71Ruby.create_system(options, system, system.iobus, system._dma_ports)
72
73# Create a seperate clock domain for Ruby
74system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
75 voltage_domain = system.voltage_domain)
76
77for (i, cpu) in enumerate(system.cpu):
78 # create the interrupt controller
79 cpu.createInterruptController()

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87 cpu.interrupts.int_slave = system.ruby._cpu_ruby_ports[i].master
88
89 # Set access_phys_mem to True for ruby port
90 system.ruby._cpu_ruby_ports[i].access_phys_mem = True
91
92system.physmem = [DDR3_1600_x64(range = r)
93 for r in system.mem_ranges]
94for i in xrange(len(system.physmem)):
72
73# Create a seperate clock domain for Ruby
74system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
75 voltage_domain = system.voltage_domain)
76
77for (i, cpu) in enumerate(system.cpu):
78 # create the interrupt controller
79 cpu.createInterruptController()

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87 cpu.interrupts.int_slave = system.ruby._cpu_ruby_ports[i].master
88
89 # Set access_phys_mem to True for ruby port
90 system.ruby._cpu_ruby_ports[i].access_phys_mem = True
91
92system.physmem = [DDR3_1600_x64(range = r)
93 for r in system.mem_ranges]
94for i in xrange(len(system.physmem)):
95 system.physmem[i].port = system.piobus.master
95 system.physmem[i].port = system.iobus.master
96
97root = Root(full_system = True, system = system)
98m5.ticks.setGlobalFrequency('1THz')
96
97root = Root(full_system = True, system = system)
98m5.ticks.setGlobalFrequency('1THz')