pc-simple-timing-ruby.py (9827:f47274776aa0) | pc-simple-timing-ruby.py (9835:cc7a7fc71c42) |
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1# Copyright (c) 2012 Mark D. Hill and David A. Wood 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 75 unchanged lines hidden (view full) --- 84 cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave 85 cpu.interrupts.pio = system.piobus.master 86 cpu.interrupts.int_master = system.piobus.slave 87 cpu.interrupts.int_slave = system.piobus.master 88 89 # Set access_phys_mem to True for ruby port 90 system.ruby._cpu_ruby_ports[i].access_phys_mem = True 91 | 1# Copyright (c) 2012 Mark D. Hill and David A. Wood 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 75 unchanged lines hidden (view full) --- 84 cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave 85 cpu.interrupts.pio = system.piobus.master 86 cpu.interrupts.int_master = system.piobus.slave 87 cpu.interrupts.int_slave = system.piobus.master 88 89 # Set access_phys_mem to True for ruby port 90 system.ruby._cpu_ruby_ports[i].access_phys_mem = True 91 |
92system.physmem = [DDR3_1600_x64(range = r, 93 conf_table_reported = True) | 92system.physmem = [DDR3_1600_x64(range = r) |
94 for r in system.mem_ranges] 95for i in xrange(len(system.physmem)): 96 system.physmem[i].port = system.piobus.master 97 98root = Root(full_system = True, system = system) 99m5.ticks.setGlobalFrequency('1THz') | 93 for r in system.mem_ranges] 94for i in xrange(len(system.physmem)): 95 system.physmem[i].port = system.piobus.master 96 97root = Root(full_system = True, system = system) 98m5.ticks.setGlobalFrequency('1THz') |