pc-simple-timing-ruby.py (9802:eec242a5252d) | pc-simple-timing-ruby.py (9826:014ff1fbff6d) |
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1# Copyright (c) 2012 Mark D. Hill and David A. Wood 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 41 unchanged lines hidden (view full) --- 50options.l2_size="4MB" 51options.l1d_assoc=2 52options.l1i_assoc=2 53options.l2_assoc=2 54options.num_cpus = 2 55 56#the system 57mdesc = SysConfig(disk = 'linux-x86.img') | 1# Copyright (c) 2012 Mark D. Hill and David A. Wood 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 41 unchanged lines hidden (view full) --- 50options.l2_size="4MB" 51options.l1d_assoc=2 52options.l1i_assoc=2 53options.l2_assoc=2 54options.num_cpus = 2 55 56#the system 57mdesc = SysConfig(disk = 'linux-x86.img') |
58system = FSConfig.makeLinuxX86System('timing', DDR3_1600_x64, options.num_cpus, | 58system = FSConfig.makeLinuxX86System('timing', options.num_cpus, |
59 mdesc=mdesc, Ruby=True) 60 61system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp') 62system.clk_domain = SrcClockDomain(clock = '1GHz') 63system.cpu_clk_domain = SrcClockDomain(clock = '2GHz') 64system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain) 65 for i in xrange(options.num_cpus)] 66 --- 12 unchanged lines hidden (view full) --- 79 cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave 80 cpu.interrupts.pio = system.piobus.master 81 cpu.interrupts.int_master = system.piobus.slave 82 cpu.interrupts.int_slave = system.piobus.master 83 84 # Set access_phys_mem to True for ruby port 85 system.ruby._cpu_ruby_ports[i].access_phys_mem = True 86 | 59 mdesc=mdesc, Ruby=True) 60 61system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp') 62system.clk_domain = SrcClockDomain(clock = '1GHz') 63system.cpu_clk_domain = SrcClockDomain(clock = '2GHz') 64system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain) 65 for i in xrange(options.num_cpus)] 66 --- 12 unchanged lines hidden (view full) --- 79 cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave 80 cpu.interrupts.pio = system.piobus.master 81 cpu.interrupts.int_master = system.piobus.slave 82 cpu.interrupts.int_slave = system.piobus.master 83 84 # Set access_phys_mem to True for ruby port 85 system.ruby._cpu_ruby_ports[i].access_phys_mem = True 86 |
87system.physmem = [DDR3_1600_x64(range = r, 88 conf_table_reported = True) 89 for r in system.mem_ranges] 90for i in xrange(len(system.physmem)): 91 system.physmem[i].port = system.piobus.master 92 |
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87root = Root(full_system = True, system = system) 88m5.ticks.setGlobalFrequency('1THz') | 93root = Root(full_system = True, system = system) 94m5.ticks.setGlobalFrequency('1THz') |