1# Copyright (c) 2012 Mark D. Hill and David A. Wood
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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63system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
64system.clk_domain = SrcClockDomain(clock = '1GHz',
65 voltage_domain = system.voltage_domain)
66system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
67 voltage_domain = system.voltage_domain)
68system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain)
69 for i in xrange(options.num_cpus)]
70
71Ruby.create_system(options, True, system, system.iobus, system._dma_ports)
72
73# Create a seperate clock domain for Ruby
74system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
75 voltage_domain = system.voltage_domain)
76
77# Connect the ruby io port to the PIO bus,
78# assuming that there is just one such port.
79system.iobus.master = system.ruby._io_port.slave
80
81for (i, cpu) in enumerate(system.cpu):
82 # create the interrupt controller
83 cpu.createInterruptController()
84 # Tie the cpu ports to the correct ruby system ports
85 cpu.icache_port = system.ruby._cpu_ports[i].slave
86 cpu.dcache_port = system.ruby._cpu_ports[i].slave
87 cpu.itb.walker.port = system.ruby._cpu_ports[i].slave
88 cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave
89
90 cpu.interrupts.pio = system.ruby._cpu_ports[i].master
91 cpu.interrupts.int_master = system.ruby._cpu_ports[i].slave
92 cpu.interrupts.int_slave = system.ruby._cpu_ports[i].master
93
94system.physmem = [SimpleMemory(range = r, null = True)
95 for r in system.mem_ranges]
96
97root = Root(full_system = True, system = system)
98m5.ticks.setGlobalFrequency('1THz')