| o3-timing-ruby.py (9793:6e6cefc1db1f) | o3-timing-ruby.py (10405:7a618c07e663) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 25 unchanged lines hidden (view full) --- 34 35import ruby_config 36ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1) 37 38cpu = DerivO3CPU(cpu_id=0) 39 40system = System(cpu = cpu, 41 physmem = ruby_memory, | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 25 unchanged lines hidden (view full) --- 34 35import ruby_config 36ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1) 37 38cpu = DerivO3CPU(cpu_id=0) 39 40system = System(cpu = cpu, 41 physmem = ruby_memory, |
| 42 membus = CoherentBus(), | 42 membus = CoherentXBar(), |
| 43 mem_mode = "timing", 44 clk_domain = SrcClockDomain(clock = '1GHz')) 45 46# Create a seperate clock domain for components that should run at 47# CPUs frequency 48system.cpu.clk_domain = SrcClockDomain(clock = '2GHz') 49 50system.physmem.port = system.membus.master 51# create the interrupt controller 52cpu.createInterruptController() 53cpu.connectAllPorts(system.membus) 54 55# Connect the system port for loading of binaries etc 56system.system_port = system.membus.slave 57 58root = Root(full_system = False, system = system) | 43 mem_mode = "timing", 44 clk_domain = SrcClockDomain(clock = '1GHz')) 45 46# Create a seperate clock domain for components that should run at 47# CPUs frequency 48system.cpu.clk_domain = SrcClockDomain(clock = '2GHz') 49 50system.physmem.port = system.membus.master 51# create the interrupt controller 52cpu.createInterruptController() 53cpu.connectAllPorts(system.membus) 54 55# Connect the system port for loading of binaries etc 56system.system_port = system.membus.slave 57 58root = Root(full_system = False, system = system) |