| o3-timing-ruby.py (9790:ccc428657233) | o3-timing-ruby.py (9793:6e6cefc1db1f) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 22 unchanged lines hidden (view full) --- 31m5.util.addToPath('../configs/common') 32m5.util.addToPath('../configs/topologies') 33 34 35import ruby_config 36ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1) 37 38cpu = DerivO3CPU(cpu_id=0) | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 22 unchanged lines hidden (view full) --- 31m5.util.addToPath('../configs/common') 32m5.util.addToPath('../configs/topologies') 33 34 35import ruby_config 36ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1) 37 38cpu = DerivO3CPU(cpu_id=0) |
| 39cpu.clock = '2GHz' | |
| 40 41system = System(cpu = cpu, 42 physmem = ruby_memory, 43 membus = CoherentBus(), | 39 40system = System(cpu = cpu, 41 physmem = ruby_memory, 42 membus = CoherentBus(), |
| 44 mem_mode = "timing") 45system.clock = '1GHz' | 43 mem_mode = "timing", 44 clk_domain = SrcClockDomain(clock = '1GHz')) 45 46# Create a seperate clock domain for components that should run at 47# CPUs frequency 48system.cpu.clk_domain = SrcClockDomain(clock = '2GHz') 49 |
| 46system.physmem.port = system.membus.master 47# create the interrupt controller 48cpu.createInterruptController() 49cpu.connectAllPorts(system.membus) 50 51# Connect the system port for loading of binaries etc 52system.system_port = system.membus.slave 53 54root = Root(full_system = False, system = system) | 50system.physmem.port = system.membus.master 51# create the interrupt controller 52cpu.createInterruptController() 53cpu.connectAllPorts(system.membus) 54 55# Connect the system port for loading of binaries etc 56system.system_port = system.membus.slave 57 58root = Root(full_system = False, system = system) |