o3-timing-ruby.py (8808:8af87554ad7e) | o3-timing-ruby.py (8839:eeb293859255) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 26 unchanged lines hidden (view full) --- 35ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1) 36 37cpu = DerivO3CPU(cpu_id=0) 38cpu.clock = '2GHz' 39 40system = System(cpu = cpu, 41 physmem = ruby_memory, 42 membus = Bus()) | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 26 unchanged lines hidden (view full) --- 35ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1) 36 37cpu = DerivO3CPU(cpu_id=0) 38cpu.clock = '2GHz' 39 40system = System(cpu = cpu, 41 physmem = ruby_memory, 42 membus = Bus()) |
43system.physmem.port = system.membus.port | 43system.physmem.port = system.membus.master |
44cpu.connectAllPorts(system.membus) 45 46# Connect the system port for loading of binaries etc | 44cpu.connectAllPorts(system.membus) 45 46# Connect the system port for loading of binaries etc |
47system.system_port = system.membus.port | 47system.system_port = system.membus.slave |
48 49root = Root(full_system = False, system = system) | 48 49root = Root(full_system = False, system = system) |