| o3-timing-ruby.py (6654:4c84e771cca7) | o3-timing-ruby.py (6870:5707ef3691b5) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 18 unchanged lines hidden (view full) --- 27# Authors: Steve Reinhardt 28 29import m5 30from m5.objects import * 31m5.util.addToPath('../configs/common') 32 33 34import ruby_config | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 18 unchanged lines hidden (view full) --- 27# Authors: Steve Reinhardt 28 29import m5 30from m5.objects import * 31m5.util.addToPath('../configs/common') 32 33 34import ruby_config |
| 35ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", 1) | 35ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1) |
| 36 37cpu = DerivO3CPU(cpu_id=0) 38cpu.clock = '2GHz' 39 40system = System(cpu = cpu, 41 physmem = ruby_memory, 42 membus = Bus()) 43system.physmem.port = system.membus.port 44cpu.connectMemPorts(system.membus) 45 46root = Root(system = system) | 36 37cpu = DerivO3CPU(cpu_id=0) 38cpu.clock = '2GHz' 39 40system = System(cpu = cpu, 41 physmem = ruby_memory, 42 membus = Bus()) 43system.physmem.port = system.membus.port 44cpu.connectMemPorts(system.membus) 45 46root = Root(system = system) |