o3-timing-ruby.py (6166:6fad2d8345b7) o3-timing-ruby.py (6289:a9e7d19871b5)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.AddToPath('../configs/common')
32
33
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 17 unchanged lines hidden (view full) ---

26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.AddToPath('../configs/common')
32
33
34import ruby_config
35ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", 1)
36
34cpu = DerivO3CPU(cpu_id=0)
35cpu.clock = '2GHz'
36
37system = System(cpu = cpu,
37cpu = DerivO3CPU(cpu_id=0)
38cpu.clock = '2GHz'
39
40system = System(cpu = cpu,
38 physmem = RubyMemory(),
41 physmem = ruby_memory,
39 membus = Bus())
40system.physmem.port = system.membus.port
41cpu.connectMemPorts(system.membus)
42
43root = Root(system = system)
42 membus = Bus())
43system.physmem.port = system.membus.port
44cpu.connectMemPorts(system.membus)
45
46root = Root(system = system)