o3-timing-ruby.py (9381:ffec48040ac1) | o3-timing-ruby.py (9790:ccc428657233) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 28 unchanged lines hidden (view full) --- 37 38cpu = DerivO3CPU(cpu_id=0) 39cpu.clock = '2GHz' 40 41system = System(cpu = cpu, 42 physmem = ruby_memory, 43 membus = CoherentBus(), 44 mem_mode = "timing") | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 28 unchanged lines hidden (view full) --- 37 38cpu = DerivO3CPU(cpu_id=0) 39cpu.clock = '2GHz' 40 41system = System(cpu = cpu, 42 physmem = ruby_memory, 43 membus = CoherentBus(), 44 mem_mode = "timing") |
45system.clock = '1GHz' |
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45system.physmem.port = system.membus.master 46# create the interrupt controller 47cpu.createInterruptController() 48cpu.connectAllPorts(system.membus) 49 50# Connect the system port for loading of binaries etc 51system.system_port = system.membus.slave 52 53root = Root(full_system = False, system = system) | 46system.physmem.port = system.membus.master 47# create the interrupt controller 48cpu.createInterruptController() 49cpu.connectAllPorts(system.membus) 50 51# Connect the system port for loading of binaries etc 52system.system_port = system.membus.slave 53 54root = Root(full_system = False, system = system) |