o3-timing-ruby.py (8876:44f8e7bb7fdf) | o3-timing-ruby.py (9036:6385cf85bf12) |
---|---|
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 25 unchanged lines hidden (view full) --- 34import ruby_config 35ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1) 36 37cpu = DerivO3CPU(cpu_id=0) 38cpu.clock = '2GHz' 39 40system = System(cpu = cpu, 41 physmem = ruby_memory, | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 25 unchanged lines hidden (view full) --- 34import ruby_config 35ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1) 36 37cpu = DerivO3CPU(cpu_id=0) 38cpu.clock = '2GHz' 39 40system = System(cpu = cpu, 41 physmem = ruby_memory, |
42 membus = Bus()) | 42 membus = CoherentBus()) |
43system.physmem.port = system.membus.master 44# create the interrupt controller 45cpu.createInterruptController() 46cpu.connectAllPorts(system.membus) 47 48# Connect the system port for loading of binaries etc 49system.system_port = system.membus.slave 50 51root = Root(full_system = False, system = system) | 43system.physmem.port = system.membus.master 44# create the interrupt controller 45cpu.createInterruptController() 46cpu.connectAllPorts(system.membus) 47 48# Connect the system port for loading of binaries etc 49system.system_port = system.membus.slave 50 51root = Root(full_system = False, system = system) |