| memtest-filter.py (10688:22452667fd5c) | memtest-filter.py (10720:67b3e74de9ae) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 24 unchanged lines hidden (view full) --- 33 34#MAX CORES IS 8 with the fals sharing method 35nb_cores = 8 36cpus = [ MemTest() for i in xrange(nb_cores) ] 37 38# system simulated 39system = System(cpu = cpus, 40 physmem = SimpleMemory(), | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 24 unchanged lines hidden (view full) --- 33 34#MAX CORES IS 8 with the fals sharing method 35nb_cores = 8 36cpus = [ MemTest() for i in xrange(nb_cores) ] 37 38# system simulated 39system = System(cpu = cpus, 40 physmem = SimpleMemory(), |
| 41 membus = CoherentXBar(width=16, snoop_filter = SnoopFilter())) | 41 membus = SystemXBar(width=16, snoop_filter = SnoopFilter())) |
| 42# Dummy voltage domain for all our clock domains 43system.voltage_domain = VoltageDomain() 44system.clk_domain = SrcClockDomain(clock = '1GHz', 45 voltage_domain = system.voltage_domain) 46 47# Create a seperate clock domain for components that should run at 48# CPUs frequency 49system.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 50 voltage_domain = system.voltage_domain) 51 | 42# Dummy voltage domain for all our clock domains 43system.voltage_domain = VoltageDomain() 44system.clk_domain = SrcClockDomain(clock = '1GHz', 45 voltage_domain = system.voltage_domain) 46 47# Create a seperate clock domain for components that should run at 48# CPUs frequency 49system.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 50 voltage_domain = system.voltage_domain) 51 |
| 52system.toL2Bus = CoherentXBar(clk_domain = system.cpu_clk_domain, width=16, 53 snoop_filter = SnoopFilter()) | 52system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain, 53 snoop_filter = SnoopFilter()) |
| 54system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8) 55system.l2c.cpu_side = system.toL2Bus.master 56 57# connect l2c to membus 58system.l2c.mem_side = system.membus.slave 59 60# add L1 caches 61for cpu in cpus: --- 18 unchanged lines hidden --- | 54system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8) 55system.l2c.cpu_side = system.toL2Bus.master 56 57# connect l2c to membus 58system.l2c.mem_side = system.membus.slave 59 60# add L1 caches 61for cpu in cpus: --- 18 unchanged lines hidden --- |