39,40c39
< system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
< funcbus = NoncoherentXBar(),
---
> system = System(cpu = cpus,
66c65
< cpu.l1c.cpu_side = cpu.test
---
> cpu.l1c.cpu_side = cpu.port
68d66
< system.funcbus.slave = cpu.functional
72,74d69
< # connect reference memory to funcbus
< system.funcmem.port = system.funcbus.master
<
85,87d79
< #root.trace.flags="Cache CachePort MemoryAccess"
< #root.trace.cycle=1
<