1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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31m5.util.addToPath('../configs/common')
32from Caches import *
33
34#MAX CORES IS 8 with the fals sharing method
35nb_cores = 8
36cpus = [ MemTest() for i in xrange(nb_cores) ]
37
38# system simulated
39system = System(cpu = cpus,
40 physmem = SimpleMemory(),
41 membus = CoherentXBar(width=16, snoop_filter = SnoopFilter()))
42# Dummy voltage domain for all our clock domains
43system.voltage_domain = VoltageDomain()
44system.clk_domain = SrcClockDomain(clock = '1GHz',
45 voltage_domain = system.voltage_domain)
46
47# Create a seperate clock domain for components that should run at

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57# connect l2c to membus
58system.l2c.mem_side = system.membus.slave
59
60# add L1 caches
61for cpu in cpus:
62 # All cpus are associated with cpu_clk_domain
63 cpu.clk_domain = system.cpu_clk_domain
64 cpu.l1c = L1Cache(size = '32kB', assoc = 4)
65 cpu.l1c.cpu_side = cpu.port
66 cpu.l1c.mem_side = system.toL2Bus.slave
67
68system.system_port = system.membus.slave
69
70# connect memory to membus
71system.physmem.port = system.membus.master
72
73
74# -----------------------
75# run simulation
76# -----------------------
77
78root = Root( full_system = False, system = system )
79root.system.mem_mode = 'timing'