1/*
2 * Copyright (c) 2015-2017 ARM Limited
3 * All rights reserved
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Andreas Sandberg
29 */
30
31/ {
32 arm,hbi = <0x0>;
33 arm,vexpress,site = <0xf>;
34 interrupt-parent = <&gic>;
35 #address-cells = <2>;
36 #size-cells = <2>;
37
38 gic: interrupt-controller@2c001000 {
39 compatible = "gem5,gic", "arm,gic-400";
40 #interrupt-cells = <3>;
41 #address-cells = <0>;
42 interrupt-controller;
43 reg = <0 0x2c001000 0 0x1000>,
44 <0 0x2c002000 0 0x1000>,
45 <0 0x2c004000 0 0x2000>,
46 <0 0x2c006000 0 0x2000>;
47 interrupts = <1 9 0xf04>;
48 };
49
50
51 timer {
52 compatible = "arm,cortex-a15-timer",
53 "arm,armv7-timer";
54 interrupts = <1 13 0xf08>,
55 <1 14 0xf08>,
56 <1 11 0xf08>;
57 clocks = <&osc_sys>;
58 clock-names="apb_pclk";
59 };
60
61 pci {
62 compatible = "pci-host-ecam-generic";
63 device_type = "pci";
64 #address-cells = <0x3>;
65 #size-cells = <0x2>;
66 #interrupt-cells = <0x1>;
67
68 reg = <0x0 0x30000000 0x0 0x10000000>;
69
70 ranges = <0x01000000 0x0 0x00000000 0x0 0x2f000000 0x0 0x00010000>,
71 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
72
73 interrupt-map = <0x000000 0x0 0x0 0 &gic 0 68 1>,
74 <0x000800 0x0 0x0 0 &gic 0 69 1>,
75 <0x001000 0x0 0x0 0 &gic 0 70 1>,
76 <0x001800 0x0 0x0 0 &gic 0 71 1>;
77
78 interrupt-map-mask = <0x001800 0x0 0x0 0x0>;
79 dma-coherent;
80 };
81
82 kmi@1c060000 {
83 compatible = "arm,pl050", "arm,primecell";
84 reg = <0x0 0x1c060000 0x0 0x1000>;
85 interrupts = <0 12 4>;
86 clocks = <&v2m_clk24mhz>, <&osc_smb>;
87 clock-names = "KMIREFCLK", "apb_pclk";
88 };
89
90 kmi@1c070000 {
91 compatible = "arm,pl050", "arm,primecell";
92 reg = <0x0 0x1c070000 0x0 0x1000>;
93 interrupts = <0 13 4>;
94 clocks = <&v2m_clk24mhz>, <&osc_smb>;
95 clock-names = "KMIREFCLK", "apb_pclk";
96 };
97
98 uart0: uart@1c090000 {
99 compatible = "arm,pl011", "arm,primecell";
100 reg = <0x0 0x1c090000 0x0 0x1000>;
101 interrupts = <0 5 4>;
102 clocks = <&osc_peripheral>, <&osc_smb>;
103 clock-names = "uartclk", "apb_pclk";
104 };
105
106 rtc@1c170000 {
107 compatible = "arm,pl031", "arm,primecell";
108 reg = <0x0 0x1c170000 0x0 0x1000>;
109 interrupts = <0 4 4>;
110 clocks = <&osc_smb>;
111 clock-names = "apb_pclk";
112 };
113
114 v2m_clk24mhz: clk24mhz {
115 compatible = "fixed-clock";
116 #clock-cells = <0>;
117 clock-frequency = <24000000>;
118 clock-output-names = "v2m:clk24mhz";
119 };
120
121
122 v2m_sysreg: sysreg@1c010000 {
123 compatible = "arm,vexpress-sysreg";
124 reg = <0 0x1c010000 0x0 0x1000>;
125 gpio-controller;
126 #gpio-cells = <2>;
127 };
128
129 vio@1c130000 {
130 compatible = "virtio,mmio";
131 reg = <0 0x1c130000 0x0 0x1000>;
132 interrupts = <0 42 4>;
133 };
134
135 vio@1c140000 {
136 compatible = "virtio,mmio";
137 reg = <0 0x1c140000 0x0 0x1000>;
138 interrupts = <0 43 4>;
139 };
140
141 dcc {
142 compatible = "arm,vexpress,config-bus";
143 arm,vexpress,config-bridge = <&v2m_sysreg>;
144
145 osc_pxl: osc@5 {
146 compatible = "arm,vexpress-osc";
147 arm,vexpress-sysreg,func = <1 5>;
148 freq-range = <23750000 1000000000>;
149 #clock-cells = <0>;
150 clock-output-names = "oscclk5";
151 };
152
153 osc_smb: osc@6 {
154 compatible = "arm,vexpress-osc";
155 arm,vexpress-sysreg,func = <1 6>;
156 freq-range = <20000000 50000000>;
157 #clock-cells = <0>;
158 clock-output-names = "oscclk6";
159 };
160
161 osc_sys: osc@7 {
162 compatible = "arm,vexpress-osc";
163 arm,vexpress-sysreg,func = <1 7>;
164 freq-range = <20000000 60000000>;
165 #clock-cells = <0>;
166 clock-output-names = "oscclk7";
167 };
168 };
169
170
171 mcc {
172 compatible = "arm,vexpress,config-bus";
173 arm,vexpress,config-bridge = <&v2m_sysreg>;
174 arm,vexpress,site = <0>;
175
176 osc_peripheral: osc@2 {
177 compatible = "arm,vexpress-osc";
178 arm,vexpress-sysreg,func = <1 2>;
179 freq-range = <24000000 24000000>;
180 #clock-cells = <0>;
181 clock-output-names = "v2m:oscclk2";
182 };
183 };
184};