1/*
2 * "@(#)rpb.h 9.2 (ULTRIX/OSF) 10/30/91"
3 */
4/************************************************************************
5 * *
6 * Copyright (c) 1990 by *
7 * Digital Equipment Corporation, Maynard, MA *
8 * All rights reserved. *
9 * *
10 * This software is furnished under a license and may be used and *
11 * copied only in accordance with the terms of such license and *
12 * with the inclusion of the above copyright notice. This *
13 * software or any other copies thereof may not be provided or *
14 * otherwise made available to any other person. No title to and *
15 * ownership of the software is hereby transferred. *
16 * *
17 * The information in this software is subject to change without *
18 * notice and should not be construed as a commitment by Digital *
19 * Equipment Corporation. *
20 * *
21 * Digital assumes no responsibility for the use or reliability *
22 * of its software on equipment which is not supplied by Digital. *
23 * *
24 ************************************************************************/
25
26/*
27 * Defines for the architected startup addresses.
28 */
29
30#define HWRPB_ADDR 0x10000000 /* 256 MB */
31#define BOOT_ADDR 0x20000000 /* 512 MB */
32#define PGTBL_ADDR 0x40000000 /* 1 GB */
33
34/*
35 * Values for the "haltcode" field in the per-cpu portion of the HWRPB
36 *
37 * Bit defines for the "sysvar" field in the HWRPB.
38 * Each platform has different values for SYSBOARD and IOBOARD bits.
39 */
40#define HALT_PWRUP 0 /* power up */
41#define HALT_OPR 1 /* operator issued halt cmd */
42#define HALT_KSTK 2 /* kernel stack not valid */
43#define HALT_SCBB 3 /* invalid SCBB */
44#define HALT_PTBR 4 /* invalid PTBR */
45#define HALT_EXE 5 /* kernel executed halt instruction */
46#define HALT_DBLE 6 /* double error abort */
47
48/*
49 * Bit defines for the "state" field in the per-cpu portion of the HWRPB
50 */
51#define STATE_BIP 0x00000001 /* bootstrap in progress */
52#define STATE_RC 0x00000002 /* restart capable */
53#define STATE_PA 0x00000004 /* processor available to OS */
54#define STATE_PP 0x00000008 /* processor present */
55#define STATE_OH 0x00000010 /* operator halted */
56#define STATE_CV 0x00000020 /* context valid */
57#define STATE_PV 0x00000040 /* PALcode valid */
58#define STATE_PMV 0x00000080 /* PALcode memory valid */
59#define STATE_PL 0x00000100 /* PALcode loaded */
60#define STATE_HALT_MASK 0x00ff0000 /* Mask for Halt Requested field */
61#define STATE_DEFAULT 0x00000000 /* Default (no specific action) */
62#define STATE_SVRS_TERM 0x00010000 /* SAVE_TERM/RESTORE_TERM Exit */
63#define STATE_COLD_BOOT 0x00020000 /* Cold Bootstrap Requested */
64#define STATE_WARM_BOOT 0x00030000 /* Warm Bootstrap Requested */
65#define STATE_HALT 0x00040000 /* Remain halted (no restart) */
66
67
68#define SV_PF_RSVD 0x00000000 /* RESERVED */
69#define SV_RESERVED 0x00000000 /* All STS bits; zero for backward compat. */
70#define SV_MPCAP 0x00000001 /* MP capable */
71#define SV_PF_UNITED 0x00000020 /* United */
72#define SV_PF_SEPARATE 0x00000040 /* Separate */
73#define SV_PF_FULLBB 0x00000060 /* Full battery backup */
74#define SV_POWERFAIL 0x000000e0 /* Powerfail implementation */
75#define SV_PF_RESTART 0x00000100 /* Powerfail restart */
76
77#define SV_GRAPHICS 0x00000200 /* Embedded graphics processor */
78
79#define SV_STS_MASK 0x0000fc00 /* STS bits - system and I/O board */
80#define SV_SANDPIPER 0x00000400 /* others define system platforms. */
81#define SV_FLAMINGO 0x00000800 /* STS BIT SETTINGS */
82#define SV_HOTPINK 0x00000c00 /* STS BIT SETTINGS */
83#define SV_FLAMINGOPLUS 0x00001000 /* STS BIT SETTINGS */
84#define SV_ULTRA 0x00001400 /* STS BIT SETTINGS */
85#define SV_SANDPLUS 0x00001800 /* STS BIT SETTINGS */
86#define SV_SANDPIPER45 0x00001c00 /* STS BIT SETTINGS */
87#define SV_FLAMINGO45 0x00002000 /* STS BIT SETTINGS */
88
89#define SV_SABLE 0x00000400 /* STS BIT SETTINGS */
90
91#define SV_KN20AA 0x00000400 /* STS BIT SETTINGS */
92
93/*
94 * Values for the "console type" field in the CTB portion of the HWRPB
95 */
96#define CONS_NONE 0 /* no console present */
97#define CONS_SRVC 1 /* console is service processor */
98#define CONS_DZ 2 /* console is dz/dl VT device */
99#define CONS_GRPH 3 /* cons is graphics dev w/ dz/dl keybd*/
100#define CONS_REM 4 /* cons is remote, protocal enet/MOP */
101
102/*
103 * PALcode variants that we're interested in.
104 * Used as indices into the "palrev_avail" array in the per-cpu portion
105 * of the HWRPB.
106 */
107#define PALvar_reserved 0
108#define PALvar_OpenVMS 1
109#define PALvar_OSF1 2
110
111#include <sys/types.h>
112/*
113 * The Alpha restart parameter block, which is a page or 2 in low memory
114 */
115struct rpb {
116 struct rpb *rpb_selfref; /* 000: physical self-reference */
117 long rpb_string; /* 008: contains string "HWRPB" */
118 long rpb_vers; /* 010: HWRPB version number */
119 u_long rpb_size; /* 018: bytes in RPB perCPU CTB CRB MEMDSC */
120 u_long rpb_cpuid; /* 020: primary cpu id */
121 u_long rpb_pagesize; /* 028: page size in bytes */
122 u_long rpb_addrbits; /* 030: number of phys addr bits */
123 u_long rpb_maxasn; /* 038: max valid ASN */
124 char rpb_ssn[16]; /* 040: system serial num: 10 ascii chars */
125 u_long rpb_systype; /* 050: system type */
126 long rpb_sysvar; /* 058: system variation */
127 long rpb_sysrev; /* 060: system revision */
128 u_long rpb_clock; /* 068: scaled interval clock intr freq */
129 u_long rpb_counter; /* 070: cycle counter frequency */
130 u_long rpb_vptb; /* 078: virtual page table base */
131 long rpb_res1; /* 080: reserved */
132 u_long rpb_trans_off; /* 088: offset to translation buffer hint */
133 u_long rpb_numprocs; /* 090: number of processor slots */
134 u_long rpb_slotsize; /* 098: per-cpu slot size */
135 u_long rpb_percpu_off; /* 0A0: offset to per_cpu slots */
136 u_long rpb_num_ctb; /* 0A8: number of CTBs */
137 u_long rpb_ctb_size; /* 0B0: bytes in largest CTB */
138 u_long rpb_ctb_off; /* 0B8: offset to CTB (cons term block) */
139 u_long rpb_crb_off; /* 0C0: offset to CRB (cons routine block) */
140 u_long rpb_mdt_off; /* 0C8: offset to memory descriptor table */
141 u_long rpb_config_off; /* 0D0: offset to config data block */
142 u_long rpb_fru_off; /* 0D8: offset to FRU table */
143 void (*rpb_saveterm)(); /* 0E0: virt addr of save term routine */
144 long rpb_saveterm_pv; /* 0E8: proc value for save term routine */
145 void (*rpb_rstrterm)(); /* 0F0: virt addr of restore term routine */
146 long rpb_rstrterm_pv; /* 0F8: proc value for restore term routine */
147 void (*rpb_restart)(); /* 100: virt addr of CPU restart routine */
148 long rpb_restart_pv; /* 108: proc value for CPU restart routine */
149 long rpb_software; /* 110: used to determine presence of kdebug */
150 long rpb_hardware; /* 118: reserved for hardware */
151 long rpb_checksum; /* 120: checksum of prior entries in rpb */
152 long rpb_rxrdy; /* 128: receive ready bitmask */
153 long rpb_txrdy; /* 130: transmit ready bitmask */
154 u_long rpb_dsr_off; /* 138: Dynamic System Recog. offset */
155};
156
157#define rpb_kdebug rpb_software
158
159#define OSF_HWRPB_ADDR ((vm_offset_t)(-1L << 23))
160
161/*
162 * This is the format for the boot/restart HWPCB. It must match the
163 * initial fields of the pcb structure as defined in pcb.h, but must
164 * additionally contain the appropriate amount of padding to line up
165 * with formats used by other palcode types.
166 */
167struct bootpcb {
168 long rpb_ksp; /* 000: kernel stack pointer */
169 long rpb_usp; /* 008: user stack pointer */
170 long rpb_ptbr; /* 010: page table base register */
171 int rpb_cc; /* 018: cycle counter */
172 int rpb_asn; /* 01C: address space number */
173 long rpb_proc_uniq; /* 020: proc/thread unique value */
174 long rpb_fen; /* 028: floating point enable */
175 long rpb_palscr[2]; /* 030: pal scratch area */
176 long rpb_pcbpad[8]; /* 040: padding for fixed size */
177};
178
179/*
180 * Inter-Console Communications Buffer
181 * Used for the primary processor to communcate with the console
182 * of secondary processors.
183 */
184struct iccb {
185 u_int iccb_rxlen; /* receive length in bytes */
186 u_int iccb_txlen; /* transmit length in bytes */
187 char iccb_rxbuf[80]; /* receive buffer */
188 char iccb_txbuf[80]; /* transmit buffer */
189};
190
191/*
192 * The per-cpu portion of the Alpha HWRPB.
193 * Note that the main portion of the HWRPB is of variable size,
194 * hence this must be a separate structure.
195 *
196 */
197struct rpb_percpu {
198 struct bootpcb rpb_pcb; /* 000: boot/restart HWPCB */
199 long rpb_state; /* 080: per-cpu state bits */
200 long rpb_palmem; /* 088: palcode memory length */
201 long rpb_palscratch; /* 090: palcode scratch length */
202 long rpb_palmem_addr; /* 098: phys addr of palcode mem space */
203 long rpb_palscratch_addr; /* 0A0: phys addr of palcode scratch space */
204 long rpb_palrev; /* 0A8: PALcode rev required */
205 long rpb_proctype; /* 0B0: processor type */
206 long rpb_procvar; /* 0B8: processor variation */
207 long rpb_procrev; /* 0C0: processor revision */
208 char rpb_procsn[16]; /* 0C8: proc serial num: 10 ascii chars */
209 long rpb_logout; /* 0D8: phys addr of logout area */
210 long rpb_logout_len; /* 0E0: length in bytes of logout area */
211 long rpb_haltpb; /* 0E8: halt pcb base */
212 long rpb_haltpc; /* 0F0: halt pc */
213 long rpb_haltps; /* 0F8: halt ps */
214 long rpb_haltal; /* 100: halt arg list (R25) */
215 long rpb_haltra; /* 108: halt return address (R26) */
216 long rpb_haltpv; /* 110: halt procedure value (R27) */
217 long rpb_haltcode; /* 118: reason for halt */
218 long rpb_software; /* 120: for software */
219 struct iccb rpb_iccb; /* 128: inter-console communications buffer */
220 long rpb_palrev_avail[16];/* 1D0: PALcode revs available */
221 long rpb_pcrsvd[6]; /* 250: reserved for arch use */
222/* the dump stack grows from the end of the rpb page not to reach here */
223};
224
225/* The firmware revision is in the (unused) first entry of palrevs available */
226#define rpb_firmrev rpb_palrev_avail[0]
227
228/*
229 * The memory cluster descriptor.
230 */
231struct rpb_cluster {
232 long rpb_pfn; /* 000: starting PFN of this cluster */
233 long rpb_pfncount; /* 008: count of PFNs in this cluster */
234 long rpb_pfntested; /* 010: count of tested PFNs in cluster */
235 long rpb_va; /* 018: va of bitmap */
236 long rpb_pa; /* 020: pa of bitmap */
237 long rpb_checksum; /* 028: checksum of bitmap */
238 long rpb_usage; /* 030: usage of cluster */
239};
240#define CLUSTER_USAGE_OS ((long)0)
241#define CLUSTER_USAGE_PAL ((long)1)
242#define CLUSTER_USAGE_NVRAM ((long)2)
243
244/*
245 * The "memory descriptor table" portion of the HWRPB.
246 * Note that the main portion of the HWRPB is of variable size and there is a
247 * variable number of per-cpu slots, hence this must be a separate structure.
248 * Also note that the memory descriptor table contains a fixed portion plus
249 * a variable number of "memory cluster descriptors" (one for each "cluster"
250 * of memory).
251 */
252struct rpb_mdt {
253 long rpb_checksum; /* 000: checksum of entire mem desc table */
254 long rpb_impaddr; /* 008: PA of implementation dep info */
255 long rpb_numcl; /* 010: number of clusters */
256 struct rpb_cluster rpb_cluster[1]; /* first instance of a cluster */
257};
258
259/*
260 * The "Console Terminal Block" portion of the HWRPB, for serial line
261 * UART console device.
262 */
263struct ctb_tt {
264 long ctb_type; /* 000: console type */
265 long ctb_unit; /* 008: console unit */
266 long ctb_resv; /* 010: reserved */
267 long ctb_length; /* 018: byte length of device dep */
268 /* portion */
269 long ctb_csr; /* 020: CSR Address */
270 long ctb_tivec; /* 028: <63>=tie; interrupt vector */
271 long ctb_rivec; /* 030: <63>=rie; interrupt vector */
272 long ctb_baud; /* 038: baud rate */
273 long ctb_put_sts; /* 040: PUTS callback extended status */
274 long ctb_get_sts; /* 048: GETS callback extended status */
275 long ctb_rsvd[1]; /* 050: reserved for console use */
276};
277
278/*
279 * The "Console Terminal Block" portion of the HWRPB.
280 */
281struct rpb_ctb {
282 long rpb_type; /* 000: console type */
283 long rpb_unit; /* 008: console unit */
284 long rpb_resv; /* 010: reserved */
285 long rpb_length; /* 018: byte length of device dep portion */
286 long rpb_first; /* 000: first field of device dep portion */
287};
288
289/*
290 * The physical/virtual map for the console routine block.
291 */
292struct rpb_map {
293 long rpb_virt; /* virtual address for map entry */
294 long rpb_phys; /* phys address for map entry */
295 long rpb_pgcount; /* page count for map entry */
296};
297
298/*
299 * The "Console Routine Block" portion of the HWRPB.
300 * Note: the "offsets" are all relative to the start of the HWRPB (HWRPB_ADDR).
301 */
302struct rpb_crb {
303 long rpb_va_disp; /* va of call-back dispatch rtn */
304 long rpb_pa_disp; /* pa of call-back dispatch rtn */
305 long rpb_va_fixup; /* va of call-back fixup rtn */
306 long rpb_pa_fixup; /* pa of call-back fixup rtn */
307 long rpb_num; /* number of entries in phys/virt map */
308 long rpb_mapped_pages; /* Number of pages to be mapped */
309 struct rpb_map rpb_map[1]; /* first instance of a map entry */
310};
311
312/*
313 * These macros define where within the HWRPB the CTB and CRB are located.
314 */
315#define CTB_SETUP ((struct rpb_ctb *) ((long)hwrpb_addr + \
316 (long)(hwrpb_addr->rpb_ctb_off)))
317#define CRB_SETUP ((struct rpb_crb *) ((long)hwrpb_addr + \
318 (long)(hwrpb_addr->rpb_crb_off)))
319
320/*
321 * The "Dynamic System Recognition" portion of the HWRPB.
322 * It is used to obtain the platform specific data need to allow
323 * the platform define the platform name, the platform SMM and LURT
324 * data for software licensing
325 */
326struct rpb_dsr {
327 long rpb_smm; /* SMM nubber used by LMF */
328 u_long rpb_lurt_off; /* offset to LURT table */
329 u_long rpb_sysname_off; /* offset to sysname char count */
330 int lurt[10]; /* XXM has one LURT entry */
331};