ev5_impure.h (8012:2f71125bf413) | ev5_impure.h (8013:2dfcde2e9998) |
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1/* | 1/* |
2Copyright 1993 Hewlett-Packard Development Company, L.P. | 2 * Copyright 1993 Hewlett-Packard Development Company, L.P. 3 * 4 * Permission is hereby granted, free of charge, to any person 5 * obtaining a copy of this software and associated documentation 6 * files (the "Software"), to deal in the Software without 7 * restriction, including without limitation the rights to use, copy, 8 * modify, merge, publish, distribute, sublicense, and/or sell copies 9 * of the Software, and to permit persons to whom the Software is 10 * furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be 13 * included in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ |
3 | 24 |
4Permission is hereby granted, free of charge, to any person obtaining a copy of 5this software and associated documentation files (the "Software"), to deal in 6the Software without restriction, including without limitation the rights to 7use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 8of the Software, and to permit persons to whom the Software is furnished to do 9so, subject to the following conditions: 10 11The above copyright notice and this permission notice shall be included in all 12copies or substantial portions of the Software. 13 14THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20SOFTWARE. 21*/ 22 | |
23#ifndef EV5_IMPURE_INCLUDED 24#define EV5_IMPURE_INCLUDED 25 | 25#ifndef EV5_IMPURE_INCLUDED 26#define EV5_IMPURE_INCLUDED 27 |
26/* | |
27// This uses the Hudson file format from "impure.h" but with the fields from 28// the distrubuted palcode "ev5_impure.sdl" .. pboyle Nov/95 29 | 28// This uses the Hudson file format from "impure.h" but with the fields from 29// the distrubuted palcode "ev5_impure.sdl" .. pboyle Nov/95 30 |
30//orig file: impure.sdl | 31// file: impure.sdl 32// 33// PAL impure scratch area and logout area data structure definitions for 34// Alpha firmware. 35// 36// 37// module $pal_impure; 38// 39// Edit Date Who Description 40// ---- --------- --- --------------------- 41// 1 7-Jul-93 JEM Initial Entry 42// 2 18-nov-93 JEM Add shadow bc_ctl and pmctr_ctl to impure area 43// Delete mvptbr 44// Calculate pal$logout from end of impure area 45// 3 6-dec-93 JEM Add pmctr_ctl bitfield definitions 46// 4 3-feb-94 JEM Remove f31,r31 from impure area; Remove bc_ctl, 47// pmctr_ctl; add ic_perr_stat, pmctr, dc_perr_stat, 48// sc_stat, sc_addr, sc_ctl, bc_tag_addr, ei_stat, 49// ei_addr, fill_syn, ld_lock 50// 5 19-feb-94 JEM add gpr constants, and add f31,r31 back in to be 51// consistent with ev4 52// add cns$ipr_offset 53// 6 18-apr-94 JEM Add shadow bc_ctl and pmctr_ctl to impure area again. 54// 7 18-jul-94 JEM Add bc_config shadow. Add mchk$sys_base constant 55// to mchk logout frame 56// 57// 58// constant REVISION equals 7 prefix IMPURE$; // Revision number of this file |
31//orig | 59//orig |
32//orig Abstract: PAL impure scratch area and logout area data structure definitions for 33//orig Alpha firmware. 34//orig 35//orig 36//orig module $pal_impure; 37//orig 38//orig Edit Date Who Description 39//orig ---- --------- --- --------------------- 40//orig 1 7-Jul-93 JEM Initial Entry 41//orig 2 18-nov-93 JEM Add shadow bc_ctl and pmctr_ctl to impure area 42//orig Delete mvptbr 43//orig Calculate pal$logout from end of impure area 44//orig 3 6-dec-93 JEM Add pmctr_ctl bitfield definitions 45//orig 4 3-feb-94 JEM Remove f31,r31 from impure area; Remove bc_ctl, pmctr_ctl; 46//orig add ic_perr_stat, pmctr, dc_perr_stat, sc_stat, sc_addr, sc_ctl, 47//orig bc_tag_addr, ei_stat, ei_addr, fill_syn, ld_lock 48//orig 5 19-feb-94 JEM add gpr constants, and add f31,r31 back in to be consistent with ev4 49//orig add cns$ipr_offset 50//orig 6 18-apr-94 JEM Add shadow bc_ctl and pmctr_ctl to impure area again. 51//orig 7 18-jul-94 JEM Add bc_config shadow. Add mchk$sys_base constant to mchk logout frame 52//orig 53//orig 54//orig constant REVISION equals 7 prefix IMPURE$; // Revision number of this file 55//orig | |
56 | 60 |
61/* |
|
57** Macros for saving/restoring data to/from the PAL impure scratch 58** area. 59** 60** The console save state area is larger than the addressibility 61** of the HW_LD/ST instructions (10-bit signed byte displacement), 62** so some adjustments to the base offsets, as well as the offsets 63** within each base region, are necessary. 64** 65** The console save state area is divided into two segments; the 66** CPU-specific segment and the platform-specific segment. The 67** state that is saved in the CPU-specific segment includes GPRs, 68** FPRs, IPRs, halt code, MCHK flag, etc. All other state is saved 69** in the platform-specific segment. 70** 71** The impure pointer will need to be adjusted by a different offset 72** value for each region within a given segment. The SAVE and RESTORE 73** macros will auto-magically adjust the offsets accordingly. 74** 75*/ | 62** Macros for saving/restoring data to/from the PAL impure scratch 63** area. 64** 65** The console save state area is larger than the addressibility 66** of the HW_LD/ST instructions (10-bit signed byte displacement), 67** so some adjustments to the base offsets, as well as the offsets 68** within each base region, are necessary. 69** 70** The console save state area is divided into two segments; the 71** CPU-specific segment and the platform-specific segment. The 72** state that is saved in the CPU-specific segment includes GPRs, 73** FPRs, IPRs, halt code, MCHK flag, etc. All other state is saved 74** in the platform-specific segment. 75** 76** The impure pointer will need to be adjusted by a different offset 77** value for each region within a given segment. The SAVE and RESTORE 78** macros will auto-magically adjust the offsets accordingly. 79** 80*/ |
76#if 0 77#define SAVE_GPR(reg,offset,base) \ 78 stq_p reg, ((offset-0x200)&0x3FF)(base) 79 80#define RESTORE_GPR(reg,offset,base) \ 81 ldq_p reg, ((offset-0x200)&0x3FF)(base) 82 83 84#define SAVE_FPR(reg,offset,base) \ 85 stt reg, ((offset-0x200)&0x3FF)(base) 86 87#define RESTORE_FPR(reg,offset,base) \ 88 ldt reg, ((offset-0x200)&0x3FF)(base) 89 90#define SAVE_IPR(reg,offset,base) \ 91 mfpr v0, reg; \ 92 stq_p v0, ((offset-CNS_Q_IPR)&0x3FF)(base) 93 94#define RESTORE_IPR(reg,offset,base) \ 95 ldq_p v0, ((offset-CNS_Q_IPR)&0x3FF)(base); \ 96 mtpr v0, reg 97 98#define SAVE_SHADOW(reg,offset,base) \ 99 stq_p reg, ((offset-CNS_Q_IPR)&0x3FF)(base) 100 101#define RESTORE_SHADOW(reg,offset,base)\ 102 ldq_p reg, ((offset-CNS_Q_IPR)&0x3FF)(base) 103#else | |
104//#define SEXT10(X) (((X) & 0x200) ? ((X) | 0xfffffffffffffc00) : (X)) 105#define SEXT10(X) ((X) & 0x3ff) 106//#define SEXT10(X) (((X) << 55) >> 55) 107 108#define SAVE_GPR(reg,offset,base) \ 109 stq_p reg, (SEXT10(offset-0x200))(base) 110 111#define RESTORE_GPR(reg,offset,base) \ --- 14 unchanged lines hidden (view full) --- 126 ldq_p v0, (SEXT10(offset-CNS_Q_IPR))(base); \ 127 mtpr v0, reg 128 129#define SAVE_SHADOW(reg,offset,base) \ 130 stq_p reg, (SEXT10(offset-CNS_Q_IPR))(base) 131 132#define RESTORE_SHADOW(reg,offset,base)\ 133 ldq_p reg, (SEXT10(offset-CNS_Q_IPR))(base) | 81//#define SEXT10(X) (((X) & 0x200) ? ((X) | 0xfffffffffffffc00) : (X)) 82#define SEXT10(X) ((X) & 0x3ff) 83//#define SEXT10(X) (((X) << 55) >> 55) 84 85#define SAVE_GPR(reg,offset,base) \ 86 stq_p reg, (SEXT10(offset-0x200))(base) 87 88#define RESTORE_GPR(reg,offset,base) \ --- 14 unchanged lines hidden (view full) --- 103 ldq_p v0, (SEXT10(offset-CNS_Q_IPR))(base); \ 104 mtpr v0, reg 105 106#define SAVE_SHADOW(reg,offset,base) \ 107 stq_p reg, (SEXT10(offset-CNS_Q_IPR))(base) 108 109#define RESTORE_SHADOW(reg,offset,base)\ 110 ldq_p reg, (SEXT10(offset-CNS_Q_IPR))(base) |
134#endif 135/* orig Structure of the processor-specific impure area */ | |
136 | 111 |
137/* orig aggregate impure struct prefix "" tag ""; 138 * orig cns$flag quadword; 139 * orig cns$hlt quadword; 140*/ | 112/* Structure of the processor-specific impure area */ |
141 | 113 |
114/* aggregate impure struct prefix "" tag ""; 115 * cns$flag quadword; 116 * cns$hlt quadword; 117 */ 118 |
|
142/* Define base for debug monitor compatibility */ 143#define CNS_Q_BASE 0x000 144#define CNS_Q_FLAG 0x100 145#define CNS_Q_HALT 0x108 146 147 | 119/* Define base for debug monitor compatibility */ 120#define CNS_Q_BASE 0x000 121#define CNS_Q_FLAG 0x100 122#define CNS_Q_HALT 0x108 123 124 |
148/* orig constant ( 149 * orig cns$r0,cns$r1,cns$r2,cns$r3,cns$r4,cns$r5,cns$r6,cns$r7, 150 * orig cns$r8,cns$r9,cns$r10,cns$r11,cns$r12,cns$r13,cns$r14,cns$r15, 151 * orig cns$r16,cns$r17,cns$r18,cns$r19,cns$r20,cns$r21,cns$r22,cns$r23, 152 * orig cns$r24,cns$r25,cns$r26,cns$r27,cns$r28,cns$r29,cns$r30,cns$r31 153 * orig ) equals . increment 8 prefix "" tag ""; 154 * orig cns$gpr quadword dimension 32; 155*/ | 125/* constant ( 126 * cns$r0,cns$r1,cns$r2,cns$r3,cns$r4,cns$r5,cns$r6,cns$r7, 127 * cns$r8,cns$r9,cns$r10,cns$r11,cns$r12,cns$r13,cns$r14,cns$r15, 128 * cns$r16,cns$r17,cns$r18,cns$r19,cns$r20,cns$r21,cns$r22,cns$r23, 129 * cns$r24,cns$r25,cns$r26,cns$r27,cns$r28,cns$r29,cns$r30,cns$r31 130 * ) equals . increment 8 prefix "" tag ""; 131 * cns$gpr quadword dimension 32; 132 */ 133 |
156/* Offset to base of saved GPR area - 32 quadword */ 157#define CNS_Q_GPR 0x110 158#define cns_gpr CNS_Q_GPR 159 | 134/* Offset to base of saved GPR area - 32 quadword */ 135#define CNS_Q_GPR 0x110 136#define cns_gpr CNS_Q_GPR 137 |
160/* orig constant ( 161 * orig cns$f0,cns$f1,cns$f2,cns$f3,cns$f4,cns$f5,cns$f6,cns$f7, 162 * orig cns$f8,cns$f9,cns$f10,cns$f11,cns$f12,cns$f13,cns$f14,cns$f15, 163 * orig cns$f16,cns$f17,cns$f18,cns$f19,cns$f20,cns$f21,cns$f22,cns$f23, 164 * orig cns$f24,cns$f25,cns$f26,cns$f27,cns$f28,cns$f29,cns$f30,cns$f31 165 * orig ) equals . increment 8 prefix "" tag ""; 166 * orig cns$fpr quadword dimension 32; 167*/ | 138/* constant ( 139 * cns$f0,cns$f1,cns$f2,cns$f3,cns$f4,cns$f5,cns$f6,cns$f7, 140 * cns$f8,cns$f9,cns$f10,cns$f11,cns$f12,cns$f13,cns$f14,cns$f15, 141 * cns$f16,cns$f17,cns$f18,cns$f19,cns$f20,cns$f21,cns$f22,cns$f23, 142 * cns$f24,cns$f25,cns$f26,cns$f27,cns$f28,cns$f29,cns$f30,cns$f31 143 * ) equals . increment 8 prefix "" tag ""; 144 * cns$fpr quadword dimension 32; 145 */ 146 |
168/* Offset to base of saved FPR area - 32 quadwords */ 169#define CNS_Q_FPR 0x210 170 | 147/* Offset to base of saved FPR area - 32 quadwords */ 148#define CNS_Q_FPR 0x210 149 |
171/* orig #t=.; 172 * orig cns$mchkflag quadword; 173*/ | 150/* #t=.; 151 * cns$mchkflag quadword; 152 */ |
174#define CNS_Q_MCHK 0x310 175 | 153#define CNS_Q_MCHK 0x310 154 |
176/* orig constant cns$pt_offset equals .; 177 * orig constant ( 178 * orig cns$pt0,cns$pt1,cns$pt2,cns$pt3,cns$pt4,cns$pt5,cns$pt6, 179 * orig cns$pt7,cns$pt8,cns$pt9,cns$pt10,cns$pt11,cns$pt12,cns$pt13, 180 * orig cns$pt14,cns$pt15,cns$pt16,cns$pt17,cns$pt18,cns$pt19,cns$pt20, 181 * orig cns$pt21,cns$pt22,cns$pt23 182 * orig ) equals . increment 8 prefix "" tag ""; 183 * orig cns$pt quadword dimension 24; 184*/ | 155/* constant cns$pt_offset equals .; 156 * constant ( 157 * cns$pt0,cns$pt1,cns$pt2,cns$pt3,cns$pt4,cns$pt5,cns$pt6, 158 * cns$pt7,cns$pt8,cns$pt9,cns$pt10,cns$pt11,cns$pt12,cns$pt13, 159 * cns$pt14,cns$pt15,cns$pt16,cns$pt17,cns$pt18,cns$pt19,cns$pt20, 160 * cns$pt21,cns$pt22,cns$pt23 161 * ) equals . increment 8 prefix "" tag ""; 162 * cns$pt quadword dimension 24; 163 */ |
185/* Offset to base of saved PALtemp area - 25 quadwords */ 186#define CNS_Q_PT 0x318 187 | 164/* Offset to base of saved PALtemp area - 25 quadwords */ 165#define CNS_Q_PT 0x318 166 |
188/* orig cns$shadow8 quadword; 189 * orig cns$shadow9 quadword; 190 * orig cns$shadow10 quadword; 191 * orig cns$shadow11 quadword; 192 * orig cns$shadow12 quadword; 193 * orig cns$shadow13 quadword; 194 * orig cns$shadow14 quadword; 195 * orig cns$shadow25 quadword; 196*/ | 167/* cns$shadow8 quadword; 168 * cns$shadow9 quadword; 169 * cns$shadow10 quadword; 170 * cns$shadow11 quadword; 171 * cns$shadow12 quadword; 172 * cns$shadow13 quadword; 173 * cns$shadow14 quadword; 174 * cns$shadow25 quadword; 175 */ |
197/* Offset to base of saved PALshadow area - 8 quadwords */ 198#define CNS_Q_SHADOW 0x3D8 199 200/* Offset to base of saved IPR area */ 201#define CNS_Q_IPR 0x418 202 | 176/* Offset to base of saved PALshadow area - 8 quadwords */ 177#define CNS_Q_SHADOW 0x3D8 178 179/* Offset to base of saved IPR area */ 180#define CNS_Q_IPR 0x418 181 |
203/* orig constant cns$ipr_offset equals .; */ 204/* orig cns$exc_addr quadword; */ | 182/* constant cns$ipr_offset equals .; */ 183/* cns$exc_addr quadword; */ |
205#define CNS_Q_EXC_ADDR 0x418 | 184#define CNS_Q_EXC_ADDR 0x418 |
206/* orig cns$pal_base quadword; */ | 185/* cns$pal_base quadword; */ |
207#define CNS_Q_PAL_BASE 0x420 | 186#define CNS_Q_PAL_BASE 0x420 |
208/* orig cns$mm_stat quadword; */ | 187/* cns$mm_stat quadword; */ |
209#define CNS_Q_MM_STAT 0x428 | 188#define CNS_Q_MM_STAT 0x428 |
210/* orig cns$va quadword; */ | 189/* cns$va quadword; */ |
211#define CNS_Q_VA 0x430 | 190#define CNS_Q_VA 0x430 |
212/* orig cns$icsr quadword; */ | 191/* cns$icsr quadword; */ |
213#define CNS_Q_ICSR 0x438 | 192#define CNS_Q_ICSR 0x438 |
214/* orig cns$ipl quadword; */ | 193/* cns$ipl quadword; */ |
215#define CNS_Q_IPL 0x440 | 194#define CNS_Q_IPL 0x440 |
216/* orig cns$ps quadword; // Ibox current mode */ | 195/* cns$ps quadword; // Ibox current mode */ |
217#define CNS_Q_IPS 0x448 | 196#define CNS_Q_IPS 0x448 |
218/* orig cns$itb_asn quadword; */ | 197/* cns$itb_asn quadword; */ |
219#define CNS_Q_ITB_ASN 0x450 | 198#define CNS_Q_ITB_ASN 0x450 |
220/* orig cns$aster quadword; */ | 199/* cns$aster quadword; */ |
221#define CNS_Q_ASTER 0x458 | 200#define CNS_Q_ASTER 0x458 |
222/* orig cns$astrr quadword; */ | 201/* cns$astrr quadword; */ |
223#define CNS_Q_ASTRR 0x460 | 202#define CNS_Q_ASTRR 0x460 |
224/* orig cns$isr quadword; */ | 203/* cns$isr quadword; */ |
225#define CNS_Q_ISR 0x468 | 204#define CNS_Q_ISR 0x468 |
226/* orig cns$ivptbr quadword; */ | 205/* cns$ivptbr quadword; */ |
227#define CNS_Q_IVPTBR 0x470 | 206#define CNS_Q_IVPTBR 0x470 |
228/* orig cns$mcsr quadword; */ | 207/* cns$mcsr quadword; */ |
229#define CNS_Q_MCSR 0x478 | 208#define CNS_Q_MCSR 0x478 |
230/* orig cns$dc_mode quadword; */ | 209/* cns$dc_mode quadword; */ |
231#define CNS_Q_DC_MODE 0x480 | 210#define CNS_Q_DC_MODE 0x480 |
232/* orig cns$maf_mode quadword; */ | 211/* cns$maf_mode quadword; */ |
233#define CNS_Q_MAF_MODE 0x488 | 212#define CNS_Q_MAF_MODE 0x488 |
234/* orig cns$sirr quadword; */ | 213/* cns$sirr quadword; */ |
235#define CNS_Q_SIRR 0x490 | 214#define CNS_Q_SIRR 0x490 |
236/* orig cns$fpcsr quadword; */ | 215/* cns$fpcsr quadword; */ |
237#define CNS_Q_FPCSR 0x498 | 216#define CNS_Q_FPCSR 0x498 |
238/* orig cns$icperr_stat quadword; */ | 217/* cns$icperr_stat quadword; */ |
239#define CNS_Q_ICPERR_STAT 0x4A0 | 218#define CNS_Q_ICPERR_STAT 0x4A0 |
240/* orig cns$pmctr quadword; */ | 219/* cns$pmctr quadword; */ |
241#define CNS_Q_PM_CTR 0x4A8 | 220#define CNS_Q_PM_CTR 0x4A8 |
242/* orig cns$exc_sum quadword; */ | 221/* cns$exc_sum quadword; */ |
243#define CNS_Q_EXC_SUM 0x4B0 | 222#define CNS_Q_EXC_SUM 0x4B0 |
244/* orig cns$exc_mask quadword; */ | 223/* cns$exc_mask quadword; */ |
245#define CNS_Q_EXC_MASK 0x4B8 | 224#define CNS_Q_EXC_MASK 0x4B8 |
246/* orig cns$intid quadword; */ | 225/* cns$intid quadword; */ |
247#define CNS_Q_INT_ID 0x4C0 | 226#define CNS_Q_INT_ID 0x4C0 |
248/* orig cns$dcperr_stat quadword; */ | 227/* cns$dcperr_stat quadword; */ |
249#define CNS_Q_DCPERR_STAT 0x4C8 | 228#define CNS_Q_DCPERR_STAT 0x4C8 |
250/* orig cns$sc_stat quadword; */ | 229/* cns$sc_stat quadword; */ |
251#define CNS_Q_SC_STAT 0x4D0 | 230#define CNS_Q_SC_STAT 0x4D0 |
252/* orig cns$sc_addr quadword; */ | 231/* cns$sc_addr quadword; */ |
253#define CNS_Q_SC_ADDR 0x4D8 | 232#define CNS_Q_SC_ADDR 0x4D8 |
254/* orig cns$sc_ctl quadword; */ | 233/* cns$sc_ctl quadword; */ |
255#define CNS_Q_SC_CTL 0x4E0 | 234#define CNS_Q_SC_CTL 0x4E0 |
256/* orig cns$bc_tag_addr quadword; */ | 235/* cns$bc_tag_addr quadword; */ |
257#define CNS_Q_BC_TAG_ADDR 0x4E8 | 236#define CNS_Q_BC_TAG_ADDR 0x4E8 |
258/* orig cns$ei_stat quadword; */ | 237/* cns$ei_stat quadword; */ |
259#define CNS_Q_EI_STAT 0x4F0 | 238#define CNS_Q_EI_STAT 0x4F0 |
260/* orig cns$ei_addr quadword; */ | 239/* cns$ei_addr quadword; */ |
261#define CNS_Q_EI_ADDR 0x4F8 | 240#define CNS_Q_EI_ADDR 0x4F8 |
262/* orig cns$fill_syn quadword; */ | 241/* cns$fill_syn quadword; */ |
263#define CNS_Q_FILL_SYN 0x500 | 242#define CNS_Q_FILL_SYN 0x500 |
264/* orig cns$ld_lock quadword; */ | 243/* cns$ld_lock quadword; */ |
265#define CNS_Q_LD_LOCK 0x508 | 244#define CNS_Q_LD_LOCK 0x508 |
266/* orig cns$bc_ctl quadword; // shadow of on chip bc_ctl */ | 245/* cns$bc_ctl quadword; // shadow of on chip bc_ctl */ |
267#define CNS_Q_BC_CTL 0x510 | 246#define CNS_Q_BC_CTL 0x510 |
268/* orig cns$pmctr_ctl quadword; // saved frequency select info for performance monitor counter */ | 247/* cns$pmctr_ctl quadword; // saved frequency select info for performance monitor counter */ |
269#define CNS_Q_PM_CTL 0x518 | 248#define CNS_Q_PM_CTL 0x518 |
270/* orig cns$bc_config quadword; // shadow of on chip bc_config */ | 249/* cns$bc_config quadword; // shadow of on chip bc_config */ |
271#define CNS_Q_BC_CFG 0x520 272 | 250#define CNS_Q_BC_CFG 0x520 251 |
273/* orig constant cns$size equals .; 274 * orig 275 * orig constant pal$impure_common_size equals (%x0200 +7) & %xfff8; 276 * orig constant pal$impure_specific_size equals (.+7) & %xfff8; 277 * orig constant cns$mchksize equals (.+7-#t) & %xfff8; 278 * orig constant pal$logout_area equals pal$impure_specific_size ; 279 * orig end impure; | 252/* constant cns$size equals .; 253 * 254 * constant pal$impure_common_size equals (%x0200 +7) & %xfff8; 255 * constant pal$impure_specific_size equals (.+7) & %xfff8; 256 * constant cns$mchksize equals (.+7-#t) & %xfff8; 257 * constant pal$logout_area equals pal$impure_specific_size ; 258 * end impure; |
280*/ 281 282/* This next set of stuff came from the old code ..pb */ 283#define CNS_Q_SROM_REV 0x528 284#define CNS_Q_PROC_ID 0x530 285#define CNS_Q_MEM_SIZE 0x538 286#define CNS_Q_CYCLE_CNT 0x540 287#define CNS_Q_SIGNATURE 0x548 288#define CNS_Q_PROC_MASK 0x550 289#define CNS_Q_SYSCTX 0x558 290 291 292 293#define MACHINE_CHECK_CRD_BASE 0 294#define MACHINE_CHECK_SIZE ((CNS_Q_SYSCTX + 7 - CNS_Q_MCHK) & 0xfff8) 295 296 297 | 259*/ 260 261/* This next set of stuff came from the old code ..pb */ 262#define CNS_Q_SROM_REV 0x528 263#define CNS_Q_PROC_ID 0x530 264#define CNS_Q_MEM_SIZE 0x538 265#define CNS_Q_CYCLE_CNT 0x540 266#define CNS_Q_SIGNATURE 0x548 267#define CNS_Q_PROC_MASK 0x550 268#define CNS_Q_SYSCTX 0x558 269 270 271 272#define MACHINE_CHECK_CRD_BASE 0 273#define MACHINE_CHECK_SIZE ((CNS_Q_SYSCTX + 7 - CNS_Q_MCHK) & 0xfff8) 274 275 276 |
298/* orig 299 * orig aggregate EV5PMCTRCTL_BITS structure fill prefix PMCTR_CTL$; 300 * orig SPROCESS bitfield length 1 ; 301 * orig FILL_0 bitfield length 3 fill tag $$; 302 * orig FRQ2 bitfield length 2 ; 303 * orig FRQ1 bitfield length 2 ; 304 * orig FRQ0 bitfield length 2 ; 305 * orig CTL2 bitfield length 2 ; 306 * orig CTL1 bitfield length 2 ; 307 * orig CTL0 bitfield length 2 ; 308 * orig FILL_1 bitfield length 16 fill tag $$; 309 * orig FILL_2 bitfield length 32 fill tag $$; 310 * orig end EV5PMCTRCTL_BITS; 311 * orig 312 * orig end_module $pal_impure; 313 * orig 314 * orig module $pal_logout; 315 * orig 316 * orig // 317 * orig // Start definition of Corrected Error Frame 318 * orig // | 277/* 278 * aggregate EV5PMCTRCTL_BITS structure fill prefix PMCTR_CTL$; 279 * SPROCESS bitfield length 1 ; 280 * FILL_0 bitfield length 3 fill tag $$; 281 * FRQ2 bitfield length 2 ; 282 * FRQ1 bitfield length 2 ; 283 * FRQ0 bitfield length 2 ; 284 * CTL2 bitfield length 2 ; 285 * CTL1 bitfield length 2 ; 286 * CTL0 bitfield length 2 ; 287 * FILL_1 bitfield length 16 fill tag $$; 288 * FILL_2 bitfield length 32 fill tag $$; 289 * end EV5PMCTRCTL_BITS; 290 * 291 * end_module $pal_impure; 292 * 293 * module $pal_logout; 294 * 295 * // 296 * // Start definition of Corrected Error Frame 297 * // |
319 */ 320 321/* | 298 */ 299 300/* |
322 * orig aggregate crd_logout struct prefix "" tag ""; | 301 * aggregate crd_logout struct prefix "" tag ""; |
323 */ 324 | 302 */ 303 |
325#ifdef SIMOS | |
326#define pal_logout_area 0x600 327#define mchk_crd_base 0 | 304#define pal_logout_area 0x600 305#define mchk_crd_base 0 |
328#endif | |
329 | 306 |
330/* orig mchk$crd_flag quadword; */ | 307/* mchk$crd_flag quadword; */ |
331#define mchk_crd_flag 0 | 308#define mchk_crd_flag 0 |
332/* orig mchk$crd_offsets quadword; */ | 309/* mchk$crd_offsets quadword; */ |
333#define mchk_crd_offsets 8 | 310#define mchk_crd_offsets 8 |
334/* orig 335 * orig // Pal-specific information */ | 311/* 312 * // Pal-specific information */ |
336#define mchk_crd_mchk_code 0x10 | 313#define mchk_crd_mchk_code 0x10 |
337/* orig mchk$crd_mchk_code quadword; 338 * orig 339 * orig // CPU-specific information 340 * orig constant mchk$crd_cpu_base equals . ; 341 * orig mchk$crd_ei_addr quadword; */ | 314/* mchk$crd_mchk_code quadword; 315 * 316 * // CPU-specific information 317 * constant mchk$crd_cpu_base equals . ; 318 * mchk$crd_ei_addr quadword; */ |
342#define mchk_crd_ei_addr 0x18 | 319#define mchk_crd_ei_addr 0x18 |
343/* orig mchk$crd_fill_syn quadword; */ | 320/* mchk$crd_fill_syn quadword; */ |
344#define mchk_crd_fill_syn 0x20 | 321#define mchk_crd_fill_syn 0x20 |
345/* orig mchk$crd_ei_stat quadword; */ | 322/* mchk$crd_ei_stat quadword; */ |
346#define mchk_crd_ei_stat 0x28 | 323#define mchk_crd_ei_stat 0x28 |
347/* orig mchk$crd_isr quadword; */ | 324/* mchk$crd_isr quadword; */ |
348#define mchk_crd_isr 0x30 349 350/* 351 * Hacked up constants for the turbolaser build. Hope 352 * this is moreless correct 353 */ 354 355#define mchk_crd_whami 0x38 356#define mchk_crd_tldev 0x40 357#define mchk_crd_tlber 0x48 358#define mchk_crd_tlesr0 0x50 359#define mchk_crd_tlesr1 0x58 360#define mchk_crd_tlesr2 0x60 361#define mchk_crd_tlesr3 0x68 362#define mchk_crd_rsvd 0x70 363 364 | 325#define mchk_crd_isr 0x30 326 327/* 328 * Hacked up constants for the turbolaser build. Hope 329 * this is moreless correct 330 */ 331 332#define mchk_crd_whami 0x38 333#define mchk_crd_tldev 0x40 334#define mchk_crd_tlber 0x48 335#define mchk_crd_tlesr0 0x50 336#define mchk_crd_tlesr1 0x58 337#define mchk_crd_tlesr2 0x60 338#define mchk_crd_tlesr3 0x68 339#define mchk_crd_rsvd 0x70 340 341 |
365#ifdef SIMOS | |
366/* 367 * mchk area seems different for tlaser 368 */ 369 370#define mchk_crd_size 0x80 371#define mchk_mchk_base (mchk_crd_size) 372 373#define mchk_tlber 0x0 374#define mchk_tlepaerr 0x8 375#define mchk_tlepderr 0x10 376#define mchk_tlepmerr 0x18 377 378 | 342/* 343 * mchk area seems different for tlaser 344 */ 345 346#define mchk_crd_size 0x80 347#define mchk_mchk_base (mchk_crd_size) 348 349#define mchk_tlber 0x0 350#define mchk_tlepaerr 0x8 351#define mchk_tlepderr 0x10 352#define mchk_tlepmerr 0x18 353 354 |
379#endif 380 381 382/* orig 383 * orig // System-specific information 384 * orig constant mchk$crd_sys_base equals . ; 385 * orig constant mchk$crd_size equals (.+7) & %xfff8; 386 * orig 387 * orig end crd_logout; 388 * orig // 389 * orig // Start definition of Machine check logout Frame 390 * orig // 391 * orig aggregate logout struct prefix "" tag ""; 392 * orig mchk$flag quadword; */ 393/* orig mchk$offsets quadword; */ 394/* orig 395 * orig // Pal-specific information 396 * orig mchk$mchk_code quadword; */ | |
397/* | 355/* |
356 * // System-specific information 357 * constant mchk$crd_sys_base equals . ; 358 * constant mchk$crd_size equals (.+7) & %xfff8; 359 * 360 * end crd_logout; 361 * // 362 * // Start definition of Machine check logout Frame 363 * // 364 * aggregate logout struct prefix "" tag ""; 365 * mchk$flag quadword; */ 366/* mchk$offsets quadword; */ 367/* 368 * // Pal-specific information 369 * mchk$mchk_code quadword; */ 370/* |
|
398 | 371 |
399 * orig mchk$pt quadword dimension 24; 400 * orig 401 * orig // CPU-specific information 402 * orig constant mchk$cpu_base equals . ; 403 * orig mchk$exc_addr quadword; 404 * orig mchk$exc_sum quadword; 405 * orig mchk$exc_mask quadword; 406 * orig mchk$pal_base quadword; 407 * orig mchk$isr quadword; 408 * orig mchk$icsr quadword; 409 * orig mchk$ic_perr_stat quadword; 410 * orig mchk$dc_perr_stat quadword; 411 * orig mchk$va quadword; 412 * orig mchk$mm_stat quadword; 413 * orig mchk$sc_addr quadword; 414 * orig mchk$sc_stat quadword; 415 * orig mchk$bc_tag_addr quadword; 416 * orig mchk$ei_addr quadword; 417 * orig mchk$fill_syn quadword; 418 * orig mchk$ei_stat quadword; 419 * orig mchk$ld_lock quadword; 420 * orig 421 * orig // System-specific information 422 * orig 423 * orig constant mchk$sys_base equals . ; 424 * orig mchk$sys_ipr1 quadword ; // Holder for system-specific stuff 425 * orig 426 * orig constant mchk$size equals (.+7) & %xfff8; 427 * orig 428 * orig 429 * orig constant mchk$crd_base equals 0 ; 430 * orig constant mchk$mchk_base equals mchk$crd_size ; 431 * orig 432 * orig 433 * orig end logout; 434 * orig 435 * orig end_module $pal_logout; | 372 * mchk$pt quadword dimension 24; 373 * 374 * // CPU-specific information 375 * constant mchk$cpu_base equals . ; 376 * mchk$exc_addr quadword; 377 * mchk$exc_sum quadword; 378 * mchk$exc_mask quadword; 379 * mchk$pal_base quadword; 380 * mchk$isr quadword; 381 * mchk$icsr quadword; 382 * mchk$ic_perr_stat quadword; 383 * mchk$dc_perr_stat quadword; 384 * mchk$va quadword; 385 * mchk$mm_stat quadword; 386 * mchk$sc_addr quadword; 387 * mchk$sc_stat quadword; 388 * mchk$bc_tag_addr quadword; 389 * mchk$ei_addr quadword; 390 * mchk$fill_syn quadword; 391 * mchk$ei_stat quadword; 392 * mchk$ld_lock quadword; 393 * 394 * // System-specific information 395 * 396 * constant mchk$sys_base equals . ; 397 * mchk$sys_ipr1 quadword ; // Holder for system-specific stuff 398 * 399 * constant mchk$size equals (.+7) & %xfff8; 400 * 401 * 402 * constant mchk$crd_base equals 0 ; 403 * constant mchk$mchk_base equals mchk$crd_size ; 404 * 405 * 406 * end logout; 407 * 408 * end_module $pal_logout; |
436*/ 437 | 409*/ 410 |
438 439 440 441/* this is lingering in the old ladbx code but looks like it was from ev4 days. 442 * This was 0x160 in the old days..pb 443*/ | 411/* 412 * this is lingering in the old ladbx code but looks like it was from 413 * ev4 days. This was 0x160 in the old days..pb 414 */ |
444#define LAF_K_SIZE MACHINE_CHECK_SIZE 445#endif | 415#define LAF_K_SIZE MACHINE_CHECK_SIZE 416#endif |