system.cc (9524:d6ffa982a68b) | system.cc (9814:7ad2b0186a32) |
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1/* | 1/* |
2 * Copyright (c) 2011-2012 ARM Limited | 2 * Copyright (c) 2011-2013 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 62 unchanged lines hidden (view full) --- 73 74int System::numSystemsRunning = 0; 75 76System::System(Params *p) 77 : MemObject(p), _systemPort("system_port", this), 78 _numContexts(0), 79 pagePtr(0), 80 init_param(p->init_param), | 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 62 unchanged lines hidden (view full) --- 73 74int System::numSystemsRunning = 0; 75 76System::System(Params *p) 77 : MemObject(p), _systemPort("system_port", this), 78 _numContexts(0), 79 pagePtr(0), 80 init_param(p->init_param), |
81 physProxy(_systemPort), 82 virtProxy(_systemPort), | 81 physProxy(_systemPort, p->cache_line_size), 82 virtProxy(_systemPort, p->cache_line_size), |
83 loadAddrMask(p->load_addr_mask), 84 nextPID(0), 85 physmem(name() + ".physmem", p->memories), 86 memoryMode(p->mem_mode), | 83 loadAddrMask(p->load_addr_mask), 84 nextPID(0), 85 physmem(name() + ".physmem", p->memories), 86 memoryMode(p->mem_mode), |
87 _cacheLineSize(p->cache_line_size), |
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87 workItemsBegin(0), 88 workItemsEnd(0), 89 numWorkIds(p->num_work_ids), 90 _params(p), 91 totalNumInsts(0), 92 instEventQueue("system instruction-based event queue") 93{ 94 // add self to global system list 95 systemList.push_back(this); 96 97 if (FullSystem) { 98 kernelSymtab = new SymbolTable; 99 if (!debugSymbolTable) 100 debugSymbolTable = new SymbolTable; 101 } 102 | 88 workItemsBegin(0), 89 workItemsEnd(0), 90 numWorkIds(p->num_work_ids), 91 _params(p), 92 totalNumInsts(0), 93 instEventQueue("system instruction-based event queue") 94{ 95 // add self to global system list 96 systemList.push_back(this); 97 98 if (FullSystem) { 99 kernelSymtab = new SymbolTable; 100 if (!debugSymbolTable) 101 debugSymbolTable = new SymbolTable; 102 } 103 |
104 // check if the cache line size is a value known to work 105 if (!(_cacheLineSize == 16 || _cacheLineSize == 32 || 106 _cacheLineSize == 64 || _cacheLineSize == 128)) 107 warn_once("Cache line size is neither 16, 32, 64 nor 128 bytes.\n"); 108 |
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103 // Get the generic system master IDs 104 MasterID tmp_id M5_VAR_USED; 105 tmp_id = getMasterId("writebacks"); 106 assert(tmp_id == Request::wbMasterId); 107 tmp_id = getMasterId("functional"); 108 assert(tmp_id == Request::funcMasterId); 109 tmp_id = getMasterId("interrupt"); 110 assert(tmp_id == Request::intMasterId); --- 354 unchanged lines hidden --- | 109 // Get the generic system master IDs 110 MasterID tmp_id M5_VAR_USED; 111 tmp_id = getMasterId("writebacks"); 112 assert(tmp_id == Request::wbMasterId); 113 tmp_id = getMasterId("functional"); 114 assert(tmp_id == Request::funcMasterId); 115 tmp_id = getMasterId("interrupt"); 116 assert(tmp_id == Request::intMasterId); --- 354 unchanged lines hidden --- |