system.cc (12515:e3d1a64d0260) system.cc (12680:91f4d6668b4f)
1/*
1/*
2 * Copyright (c) 2011-2014,2017 ARM Limited
2 * Copyright (c) 2011-2014,2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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130
131 // check if the cache line size is a value known to work
132 if (!(_cacheLineSize == 16 || _cacheLineSize == 32 ||
133 _cacheLineSize == 64 || _cacheLineSize == 128))
134 warn_once("Cache line size is neither 16, 32, 64 nor 128 bytes.\n");
135
136 // Get the generic system master IDs
137 MasterID tmp_id M5_VAR_USED;
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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130
131 // check if the cache line size is a value known to work
132 if (!(_cacheLineSize == 16 || _cacheLineSize == 32 ||
133 _cacheLineSize == 64 || _cacheLineSize == 128))
134 warn_once("Cache line size is neither 16, 32, 64 nor 128 bytes.\n");
135
136 // Get the generic system master IDs
137 MasterID tmp_id M5_VAR_USED;
138 tmp_id = getMasterId("writebacks");
138 tmp_id = getMasterId(this, "writebacks");
139 assert(tmp_id == Request::wbMasterId);
139 assert(tmp_id == Request::wbMasterId);
140 tmp_id = getMasterId("functional");
140 tmp_id = getMasterId(this, "functional");
141 assert(tmp_id == Request::funcMasterId);
141 assert(tmp_id == Request::funcMasterId);
142 tmp_id = getMasterId("interrupt");
142 tmp_id = getMasterId(this, "interrupt");
143 assert(tmp_id == Request::intMasterId);
144
145 if (FullSystem) {
146 if (params()->kernel == "") {
147 inform("No kernel set for full system simulation. "
148 "Assuming you know what you're doing\n");
149 } else {
150 // Get the kernel code

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487
488void
489printSystems()
490{
491 System::printSystems();
492}
493
494MasterID
143 assert(tmp_id == Request::intMasterId);
144
145 if (FullSystem) {
146 if (params()->kernel == "") {
147 inform("No kernel set for full system simulation. "
148 "Assuming you know what you're doing\n");
149 } else {
150 // Get the kernel code

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487
488void
489printSystems()
490{
491 System::printSystems();
492}
493
494MasterID
495System::getMasterId(std::string master_name)
495System::getGlobalMasterId(std::string master_name)
496{
496{
497 // strip off system name if the string starts with it
497 return _getMasterId(nullptr, master_name);
498}
499
500MasterID
501System::getMasterId(const SimObject* master, std::string submaster)
502{
503 auto master_name = leafMasterName(master, submaster);
504 return _getMasterId(master, master_name);
505}
506
507MasterID
508System::_getMasterId(const SimObject* master, std::string master_name)
509{
498 if (startswith(master_name, name()))
499 master_name = master_name.erase(0, name().size() + 1);
500
501 // CPUs in switch_cpus ask for ids again after switching
510 if (startswith(master_name, name()))
511 master_name = master_name.erase(0, name().size() + 1);
512
513 // CPUs in switch_cpus ask for ids again after switching
502 for (int i = 0; i < masterIds.size(); i++) {
503 if (masterIds[i] == master_name) {
514 for (int i = 0; i < masters.size(); i++) {
515 if (masters[i].masterName == master_name) {
504 return i;
505 }
506 }
507
508 // Verify that the statistics haven't been enabled yet
509 // Otherwise objects will have sized their stat buckets and
510 // they will be too small
511
512 if (Stats::enabled()) {
513 fatal("Can't request a masterId after regStats(). "
514 "You must do so in init().\n");
515 }
516
516 return i;
517 }
518 }
519
520 // Verify that the statistics haven't been enabled yet
521 // Otherwise objects will have sized their stat buckets and
522 // they will be too small
523
524 if (Stats::enabled()) {
525 fatal("Can't request a masterId after regStats(). "
526 "You must do so in init().\n");
527 }
528
517 masterIds.push_back(master_name);
529 // Generate a new MasterID incrementally
530 MasterID master_id = masters.size();
518
531
519 return masterIds.size() - 1;
532 // Append the new Master metadata to the group of system Masters.
533 masters.emplace_back(master, master_name, master_id);
534
535 return masters.back().masterId;
520}
521
522std::string
536}
537
538std::string
539System::leafMasterName(const SimObject* master, const std::string& submaster)
540{
541 // Get the full master name by appending the submaster name to
542 // the root SimObject master name
543 auto master_name = master->name() + "." + submaster;
544 return master_name;
545}
546
547std::string
523System::getMasterName(MasterID master_id)
524{
548System::getMasterName(MasterID master_id)
549{
525 if (master_id >= masterIds.size())
550 if (master_id >= masters.size())
526 fatal("Invalid master_id passed to getMasterName()\n");
527
551 fatal("Invalid master_id passed to getMasterName()\n");
552
528 return masterIds[master_id];
553 const auto& master_info = masters[master_id];
554 return master_info.masterName;
529}
530
531System *
532SystemParams::create()
533{
534 return new System(this);
535}
555}
556
557System *
558SystemParams::create()
559{
560 return new System(this);
561}