pseudo_inst.cc (9952:7437cc334df1) | pseudo_inst.cc (10553:c1ad57c53a36) |
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1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 38 unchanged lines hidden (view full) --- 47#include <cerrno> 48#include <fstream> 49#include <string> 50#include <vector> 51 52#include "arch/kernel_stats.hh" 53#include "arch/utility.hh" 54#include "arch/vtophys.hh" | 1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 38 unchanged lines hidden (view full) --- 47#include <cerrno> 48#include <fstream> 49#include <string> 50#include <vector> 51 52#include "arch/kernel_stats.hh" 53#include "arch/utility.hh" 54#include "arch/vtophys.hh" |
55#include "arch/pseudo_inst.hh" |
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55#include "base/debug.hh" 56#include "base/output.hh" 57#include "config/the_isa.hh" 58#include "cpu/base.hh" 59#include "cpu/quiesce_event.hh" 60#include "cpu/thread_context.hh" 61#include "debug/Loader.hh" 62#include "debug/PseudoInst.hh" 63#include "debug/Quiesce.hh" 64#include "debug/WorkItems.hh" 65#include "params/BaseCPU.hh" 66#include "sim/full_system.hh" | 56#include "base/debug.hh" 57#include "base/output.hh" 58#include "config/the_isa.hh" 59#include "cpu/base.hh" 60#include "cpu/quiesce_event.hh" 61#include "cpu/thread_context.hh" 62#include "debug/Loader.hh" 63#include "debug/PseudoInst.hh" 64#include "debug/Quiesce.hh" 65#include "debug/WorkItems.hh" 66#include "params/BaseCPU.hh" 67#include "sim/full_system.hh" |
68#include "sim/process.hh" |
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67#include "sim/pseudo_inst.hh" 68#include "sim/serialize.hh" 69#include "sim/sim_events.hh" 70#include "sim/sim_exit.hh" 71#include "sim/stat_control.hh" 72#include "sim/stats.hh" 73#include "sim/system.hh" 74#include "sim/vptr.hh" --- 118 unchanged lines hidden (view full) --- 193 case 0x55: // annotate_func 194 case 0x56: // reserved2_func 195 case 0x57: // reserved3_func 196 case 0x58: // reserved4_func 197 case 0x59: // reserved5_func 198 warn("Unimplemented m5 op (0x%x)\n", func); 199 break; 200 | 69#include "sim/pseudo_inst.hh" 70#include "sim/serialize.hh" 71#include "sim/sim_events.hh" 72#include "sim/sim_exit.hh" 73#include "sim/stat_control.hh" 74#include "sim/stats.hh" 75#include "sim/system.hh" 76#include "sim/vptr.hh" --- 118 unchanged lines hidden (view full) --- 195 case 0x55: // annotate_func 196 case 0x56: // reserved2_func 197 case 0x57: // reserved3_func 198 case 0x58: // reserved4_func 199 case 0x59: // reserved5_func 200 warn("Unimplemented m5 op (0x%x)\n", func); 201 break; 202 |
203 /* SE mode functions */ 204 case 0x60: // syscall_func 205 m5Syscall(tc); 206 break; 207 208 case 0x61: // pagefault_func 209 m5PageFault(tc); 210 break; 211 |
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201 default: 202 warn("Unhandled m5 op: 0x%x\n", func); 203 break; 204 } 205 206 return 0; 207} 208 --- 501 unchanged lines hidden --- | 212 default: 213 warn("Unhandled m5 op: 0x%x\n", func); 214 break; 215 } 216 217 return 0; 218} 219 --- 501 unchanged lines hidden --- |