pseudo_inst.cc (5529:9ae69b9cd7fd) pseudo_inst.cc (5606:6da7a58b0bc8)
1/*
2 * Copyright (c) 2003-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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39#include "arch/vtophys.hh"
40#include "base/annotate.hh"
41#include "cpu/base.hh"
42#include "cpu/thread_context.hh"
43#include "cpu/quiesce_event.hh"
44#include "params/BaseCPU.hh"
45#include "sim/pseudo_inst.hh"
46#include "sim/serialize.hh"
1/*
2 * Copyright (c) 2003-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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39#include "arch/vtophys.hh"
40#include "base/annotate.hh"
41#include "cpu/base.hh"
42#include "cpu/thread_context.hh"
43#include "cpu/quiesce_event.hh"
44#include "params/BaseCPU.hh"
45#include "sim/pseudo_inst.hh"
46#include "sim/serialize.hh"
47#include "sim/sim_events.hh"
47#include "sim/sim_exit.hh"
48#include "sim/stat_control.hh"
49#include "sim/stats.hh"
50#include "sim/system.hh"
51#include "sim/debug.hh"
52#include "sim/vptr.hh"
53
54using namespace std;

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83{
84 if (!tc->getCpuPtr()->params()->do_quiesce || ns == 0)
85 return;
86
87 EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
88
89 Tick resume = curTick + Clock::Int::ns * ns;
90
48#include "sim/sim_exit.hh"
49#include "sim/stat_control.hh"
50#include "sim/stats.hh"
51#include "sim/system.hh"
52#include "sim/debug.hh"
53#include "sim/vptr.hh"
54
55using namespace std;

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84{
85 if (!tc->getCpuPtr()->params()->do_quiesce || ns == 0)
86 return;
87
88 EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
89
90 Tick resume = curTick + Clock::Int::ns * ns;
91
91 quiesceEvent->reschedule(resume, true);
92 mainEventQueue.reschedule(quiesceEvent, resume, true);
92
93 DPRINTF(Quiesce, "%s: quiesceNs(%d) until %d\n",
94 tc->getCpuPtr()->name(), ns, resume);
95
96 tc->suspend();
97 if (tc->getKernelStats())
98 tc->getKernelStats()->quiesce();
99}
100
101void
102quiesceCycles(ThreadContext *tc, uint64_t cycles)
103{
104 if (!tc->getCpuPtr()->params()->do_quiesce || cycles == 0)
105 return;
106
107 EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
108
109 Tick resume = curTick + tc->getCpuPtr()->ticks(cycles);
110
93
94 DPRINTF(Quiesce, "%s: quiesceNs(%d) until %d\n",
95 tc->getCpuPtr()->name(), ns, resume);
96
97 tc->suspend();
98 if (tc->getKernelStats())
99 tc->getKernelStats()->quiesce();
100}
101
102void
103quiesceCycles(ThreadContext *tc, uint64_t cycles)
104{
105 if (!tc->getCpuPtr()->params()->do_quiesce || cycles == 0)
106 return;
107
108 EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
109
110 Tick resume = curTick + tc->getCpuPtr()->ticks(cycles);
111
111 quiesceEvent->reschedule(resume, true);
112 mainEventQueue.reschedule(quiesceEvent, resume, true);
112
113 DPRINTF(Quiesce, "%s: quiesceCycles(%d) until %d\n",
114 tc->getCpuPtr()->name(), cycles, resume);
115
116 tc->suspend();
117 if (tc->getKernelStats())
118 tc->getKernelStats()->quiesce();
119}
120
121uint64_t
122quiesceTime(ThreadContext *tc)
123{
124 return (tc->readLastActivate() - tc->readLastSuspend()) / Clock::Int::ns;
125}
126
127void
128m5exit(ThreadContext *tc, Tick delay)
129{
130 Tick when = curTick + delay * Clock::Int::ns;
113
114 DPRINTF(Quiesce, "%s: quiesceCycles(%d) until %d\n",
115 tc->getCpuPtr()->name(), cycles, resume);
116
117 tc->suspend();
118 if (tc->getKernelStats())
119 tc->getKernelStats()->quiesce();
120}
121
122uint64_t
123quiesceTime(ThreadContext *tc)
124{
125 return (tc->readLastActivate() - tc->readLastSuspend()) / Clock::Int::ns;
126}
127
128void
129m5exit(ThreadContext *tc, Tick delay)
130{
131 Tick when = curTick + delay * Clock::Int::ns;
131 schedExitSimLoop("m5_exit instruction encountered", when);
132 Event *event = new SimLoopExitEvent("m5_exit instruction encountered", 0);
133 mainEventQueue.schedule(event, when);
132}
133
134void
135loadsymbol(ThreadContext *tc)
136{
137 const string &filename = tc->getCpuPtr()->system->params()->symbolfile;
138 if (filename.empty()) {
139 return;

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234m5checkpoint(ThreadContext *tc, Tick delay, Tick period)
235{
236 if (!tc->getCpuPtr()->params()->do_checkpoint_insts)
237 return;
238
239 Tick when = curTick + delay * Clock::Int::ns;
240 Tick repeat = period * Clock::Int::ns;
241
134}
135
136void
137loadsymbol(ThreadContext *tc)
138{
139 const string &filename = tc->getCpuPtr()->system->params()->symbolfile;
140 if (filename.empty()) {
141 return;

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236m5checkpoint(ThreadContext *tc, Tick delay, Tick period)
237{
238 if (!tc->getCpuPtr()->params()->do_checkpoint_insts)
239 return;
240
241 Tick when = curTick + delay * Clock::Int::ns;
242 Tick repeat = period * Clock::Int::ns;
243
242 schedExitSimLoop("checkpoint", when, repeat);
244 Event *event = new SimLoopExitEvent("checkpoint", 0, repeat);
245 mainEventQueue.schedule(event, when);
243}
244
245uint64_t
246readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset)
247{
248 const string &file = tc->getSystemPtr()->params()->readfile;
249 if (file.empty()) {
250 return ULL(0);

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247
248uint64_t
249readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset)
250{
251 const string &file = tc->getSystemPtr()->params()->readfile;
252 if (file.empty()) {
253 return ULL(0);

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