pseudo_inst.cc (2799:1c93aed5aa4a) | pseudo_inst.cc (2840:227f7c4f8c81) |
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1/* 2 * Copyright (c) 2003-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 38 unchanged lines hidden (view full) --- 47#include "sim/stat_control.hh" 48#include "sim/stats.hh" 49#include "sim/system.hh" 50#include "sim/debug.hh" 51#include "sim/vptr.hh" 52 53using namespace std; 54 | 1/* 2 * Copyright (c) 2003-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 38 unchanged lines hidden (view full) --- 47#include "sim/stat_control.hh" 48#include "sim/stats.hh" 49#include "sim/system.hh" 50#include "sim/debug.hh" 51#include "sim/vptr.hh" 52 53using namespace std; 54 |
55extern Sampler *SampCPU; 56 | |
57using namespace Stats; 58using namespace TheISA; 59 60namespace AlphaPseudo 61{ 62 bool doStatisticsInsts; 63 bool doCheckpointInsts; 64 bool doQuiesce; --- 210 unchanged lines hidden (view full) --- 275 276 void debugbreak(ThreadContext *tc) 277 { 278 debug_break(); 279 } 280 281 void switchcpu(ThreadContext *tc) 282 { | 55using namespace Stats; 56using namespace TheISA; 57 58namespace AlphaPseudo 59{ 60 bool doStatisticsInsts; 61 bool doCheckpointInsts; 62 bool doQuiesce; --- 210 unchanged lines hidden (view full) --- 273 274 void debugbreak(ThreadContext *tc) 275 { 276 debug_break(); 277 } 278 279 void switchcpu(ThreadContext *tc) 280 { |
283 if (SampCPU) 284 SampCPU->switchCPUs(); | |
285 } 286} | 281 } 282} |