pseudo_inst.cc (11289:ab19693da8c9) pseudo_inst.cc (11290:1640dd68b0a4)
1/*
2 * Copyright (c) 2010-2012, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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58#include "config/the_isa.hh"
59#include "cpu/base.hh"
60#include "cpu/quiesce_event.hh"
61#include "cpu/thread_context.hh"
62#include "debug/Loader.hh"
63#include "debug/PseudoInst.hh"
64#include "debug/Quiesce.hh"
65#include "debug/WorkItems.hh"
1/*
2 * Copyright (c) 2010-2012, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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58#include "config/the_isa.hh"
59#include "cpu/base.hh"
60#include "cpu/quiesce_event.hh"
61#include "cpu/thread_context.hh"
62#include "debug/Loader.hh"
63#include "debug/PseudoInst.hh"
64#include "debug/Quiesce.hh"
65#include "debug/WorkItems.hh"
66#include "dev/net/dist_iface.hh"
66#include "params/BaseCPU.hh"
67#include "sim/full_system.hh"
67#include "params/BaseCPU.hh"
68#include "sim/full_system.hh"
69#include "sim/initparam_keys.hh"
68#include "sim/process.hh"
69#include "sim/pseudo_inst.hh"
70#include "sim/serialize.hh"
71#include "sim/sim_events.hh"
72#include "sim/sim_exit.hh"
73#include "sim/stat_control.hh"
74#include "sim/stats.hh"
75#include "sim/system.hh"

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352 if (other_tc->status() == ThreadContext::Suspended)
353 other_tc->activate();
354}
355
356void
357m5exit(ThreadContext *tc, Tick delay)
358{
359 DPRINTF(PseudoInst, "PseudoInst::m5exit(%i)\n", delay);
70#include "sim/process.hh"
71#include "sim/pseudo_inst.hh"
72#include "sim/serialize.hh"
73#include "sim/sim_events.hh"
74#include "sim/sim_exit.hh"
75#include "sim/stat_control.hh"
76#include "sim/stats.hh"
77#include "sim/system.hh"

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354 if (other_tc->status() == ThreadContext::Suspended)
355 other_tc->activate();
356}
357
358void
359m5exit(ThreadContext *tc, Tick delay)
360{
361 DPRINTF(PseudoInst, "PseudoInst::m5exit(%i)\n", delay);
360 Tick when = curTick() + delay * SimClock::Int::ns;
361 exitSimLoop("m5_exit instruction encountered", 0, when, 0, true);
362 if (DistIface::readyToExit(delay)) {
363 Tick when = curTick() + delay * SimClock::Int::ns;
364 exitSimLoop("m5_exit instruction encountered", 0, when, 0, true);
365 }
362}
363
364void
365m5fail(ThreadContext *tc, Tick delay, uint64_t code)
366{
367 DPRINTF(PseudoInst, "PseudoInst::m5fail(%i, %i)\n", delay, code);
368 Tick when = curTick() + delay * SimClock::Int::ns;
369 exitSimLoop("m5_fail instruction encountered", code, when, 0, true);

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466 sizeof(uint64_t));
467 } else {
468 assert(key_str2 == 0);
469 }
470
471 // Compare the key parameter with the known values to select the return
472 // value
473 uint64_t val;
366}
367
368void
369m5fail(ThreadContext *tc, Tick delay, uint64_t code)
370{
371 DPRINTF(PseudoInst, "PseudoInst::m5fail(%i, %i)\n", delay, code);
372 Tick when = curTick() + delay * SimClock::Int::ns;
373 exitSimLoop("m5_fail instruction encountered", code, when, 0, true);

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470 sizeof(uint64_t));
471 } else {
472 assert(key_str2 == 0);
473 }
474
475 // Compare the key parameter with the known values to select the return
476 // value
477 uint64_t val;
474 if (strlen(key_str) == 0) {
478 if (strcmp(key_str, InitParamKey::DEFAULT) == 0) {
475 val = tc->getCpuPtr()->system->init_param;
479 val = tc->getCpuPtr()->system->init_param;
480 } else if (strcmp(key_str, InitParamKey::DIST_RANK) == 0) {
481 val = DistIface::rankParam();
482 } else if (strcmp(key_str, InitParamKey::DIST_SIZE) == 0) {
483 val = DistIface::sizeParam();
476 } else {
484 } else {
477 panic("Unknown key for initparam pseudo instruction");
485 panic("Unknown key for initparam pseudo instruction:\"%s\"", key_str);
478 }
479 return val;
480}
481
482
483void
484resetstats(ThreadContext *tc, Tick delay, Tick period)
485{

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524
525void
526m5checkpoint(ThreadContext *tc, Tick delay, Tick period)
527{
528 DPRINTF(PseudoInst, "PseudoInst::m5checkpoint(%i, %i)\n", delay, period);
529 if (!tc->getCpuPtr()->params()->do_checkpoint_insts)
530 return;
531
486 }
487 return val;
488}
489
490
491void
492resetstats(ThreadContext *tc, Tick delay, Tick period)
493{

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532
533void
534m5checkpoint(ThreadContext *tc, Tick delay, Tick period)
535{
536 DPRINTF(PseudoInst, "PseudoInst::m5checkpoint(%i, %i)\n", delay, period);
537 if (!tc->getCpuPtr()->params()->do_checkpoint_insts)
538 return;
539
532 Tick when = curTick() + delay * SimClock::Int::ns;
533 Tick repeat = period * SimClock::Int::ns;
534
535 exitSimLoop("checkpoint", 0, when, repeat);
540 if (DistIface::readyToCkpt(delay, period)) {
541 Tick when = curTick() + delay * SimClock::Int::ns;
542 Tick repeat = period * SimClock::Int::ns;
543 exitSimLoop("checkpoint", 0, when, repeat);
544 }
536}
537
538uint64_t
539readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset)
540{
541 DPRINTF(PseudoInst, "PseudoInst::readfile(0x%x, 0x%x, 0x%x)\n",
542 vaddr, len, offset);
543 if (!FullSystem) {

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546
547uint64_t
548readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset)
549{
550 DPRINTF(PseudoInst, "PseudoInst::readfile(0x%x, 0x%x, 0x%x)\n",
551 vaddr, len, offset);
552 if (!FullSystem) {

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